dell inspiron 1440 - wistron alba uma

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Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.

Alba UMA -1Cover Page

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1 61Monday, April 06, 2009

Alba UMA

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Alba UMA

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Alba UMA

Intel Cantiga-GM + ICH9M

2009-04-06

REV : -1

Alba UMA Schematics

uFCPGA Mobile Penryn

DY : Nopop Component

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Alba UMA -1Block Diagram

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Alba UMA

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Alba UMA

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Alba UMA

EMC2102

FSB800/1066MHz

DMIx4

KBC

Thermal& Fan Int. KB

LPC Bus

2MBFlash ROM

Intel Mobile CPU

DDRII 800 Channel A

DDR II 800 Channel B

ALBA UMA Block Diagram

Penryn

Cantiga-GMAGTL+ CPU I/F

External GraphicsDDR Memory I/F

ICH9-MUSB 2.0/1.1 ports (12)

SATA ports (4)High Definition Audio

ACPI 1.1LPC I/F

PCI/PCI BRIDGE

PCI Express ports (6)

WINBONDWPCE773L

SPI

8,9

10,11,12,13,14,15

Clock GeneratorSLG8SP513VTR

26

7

47 45 28,44

18,19,20,21

TouchPAD 45

Project code : 91.4BK01.001Part Number : 48.4BK04.0SAPCB P/N : 08243Revision : SA

CONTROL-LINK

45BluetoothUSB 2.0 x 1

PCIE

2510/100 LOMRTL8103EL

PCIE x 1

Left Side:USB x 2

Right Side:USB x 1

CAMERA(Option) 47

51

USB 2.0 x 1

USB 2.0 x 1

USB 2.0

802.11a/b/g/n 43Mini-Card

New Card

PCIE x 1

TPS2231RGPPower SW

RJ45CONN

PCIE x 1 & USB 2.0 x 1

Intel

Intel

Socket P

ODD

S

A

T

A

44 44

S

A

T

A

HDD

RealtekRTS5159

CardReader(7 in 1)SD/MMCMS/MS Pro/xD USB2.0

AzaliaCODEC

IDT92HD81

AZALIA

OP AMP

22

2CH SPEAKER

MIC IN

HP OUT

Digital Mic Array

USB 2.0 x 2

42

46

DDRII800

Slot 0

Slot 1

16

17DDRII800

LVDS(Dual Channel)

CRT

LCD

RGB CRT

41

RJ11 MDC MODEM4642

AZALIA

42

50

(On Express Card board)


(Option)Internal Mic

50

50


47

44

44

34,35

+3.3V_RTC_LDO

33

32

ISL6266A/CPU_CORE

38

+0.9V_DDR_VTT

36

+VCC_CORE

OUTPUTS

+V_DDR_MCH_REF

+PWR_SRC

INPUTS

+1.8V_SUS

+PWR_SRC +5V_ALW

OUTPUTS

+3.3V_ALW

TPS51117/1.05V

+1.05V_VCCP

OUTPUTS

INPUTS

+PWR_SRC

INPUTS

OUTPUTS

INPUTS OUTPUTS

INPUTS

+PWR_SRC+PBATT

+5V_ALW2

+DC_IN

MAX8731A/CHARGER

PCB LAYER

TPS51116/1.8V,0.9V

+PWR_SRC

L6: Signal

L4: SignalL5: VCC

L2: GNDL3: Signal

OUTPUTS

30

L7: GNDL8: Bottom

L1: Top

INPUTS+5V_RUN

+3.3V_ALW+5V_ALW

RUN PWR/3V,5V

+3.3V_RUN

TPS51125/3V,5V

37

+1.5V_RUN

INPUTS OUTPUTS

L6935TR/1.5V

+1.8V_SUS

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

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Alba UMA -1Power Block Diagram

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Alba UMA

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Alba UMA

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Alba UMA

Charger

MAX8731A

+PBATT

Adapter

Battery

TPS51125

3D3V_AUX_S5

Regulator LDO Switch

+5V_ALW

+3.3V_RTC_LDO AO4468

+5V_RUN

TPS2062AD

+5V_USB1

TPS2062AD

+5V_USB2

+3.3V_ALW

AO3403

+3.3V_LAN

AO4468

+3.3V_RUN+3.3V_CARDAUX

RTL8103EL

+DVDD12

ISL6266A

+VCC_CORE

+3.3V_CARD

SI3456BDV

+LCDVDD

TPS51117

+1.05V_VCCP

+PWR_SRC TPS51116

+0.9V_DDR_VTT+V_DDR_MCH_REF

+1.5V_RUN

+1.8V_SUSLDO

TPS2231RGP

+1.5V_CARD

Power Shape

+3.3V_MIC+5V_CAMERA

SI4835BDY

30 30

TPS2231RGP5025

25TPS2231RGP

50

41

34,35 36

38

L6935TR 37

50

32

32

+5V_ALW2

33

46 51

AA

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

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Alba UMA -1SMBUS Block Diagram

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Alba UMA

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Alba UMA

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Alba UMA

TPDATA

TPCLK

+5V_RUN

TouchPad Conn.TPDATA

TPCLK

PSCLK1

PSDAT1

ICH9M SMBus Block Diagram

ICH9MSMBCLK

SMBDATA

GPIO74/SDA2

GPIO73/SCL2

KBCWPC773L

CLK_SMB

ThermalSCL

SDA

+3.3V_RUN

SRN2K2J-1-GP

+3.3V_ALW

SRN2K2J-1-GP+3.3V_RUN

2N7002SPT

DAT_SMB

KBC_SCL1

KBC_SDA1

SCL1

SDA1

BAT_SCL

ExpressCardSMB_CLK

BAT_SDA

SMB_DATA

SMBus address:D2

SMBus Address:A0

SMBus Address:A4

DIMM 1SCL

SDA

+3.3V_RTC_LDO

DIMM 2SCL

SDA

SMBus address:16

SMB_CLK

SMB_DATA

ICH_SMBCLK

ICH_SMBDATA

PBAT_SMBCLK1

PBAT_SMBDAT1

KBC SMBus Block Diagram

Battery Conn.

ICH_SMBCLK

ICH_SMBDATA

ClockGeneratorSCLK

SDATA

ICH_SMBCLK

ICH_SMBDATA

SMB_CLK

SMB_DATA

MAX8731SCL

SDA

TPDATA

TPCLK

+3.3V_RUN

2N7002DW-1-GP

THERM_SCL

THERM_SDA

SMBus address:7A

SMBus address:12

+3.3V_RUN

SRN10KJ-5-GP

SRN4K7J-8-GP

SRN100J-3-GP

SRN4K7J-8-GP

+3.3V_RTC_LDO

SRN4K7J-8-GP

54

26

50

20

16

17

09

28

32

31

45

MinicardWLANSMB_DATA

SMB_CLKSMB_DATA

SMB_CLK

43

SRN2K2J-1-GP

LDDC_CLK

LDDC_DATA

+3.3V_RUN

LCD Conn.

+3.3V_RUN

2N7002DW-1-GP

SRN2K2J-1-GP

+5V_CRT_RUN

SRN2K2J-1-GP

CRT CONNDDC_CLK_CONDDC_DATA_CON

41

54

42

+3.3V_RUN

GM45

L_DDC_CLK

L_DDC_DATA

CRT_DDC_CLK

CRT_DDC_DATA

GMCH_DDCCLK

GMCH_DDCDATA

AA

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

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Alba UMA -1Thermal/Audio Block Diagram

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Alba UMA

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Alba UMA

Thermal Block Diagram Audio Block Diagram

Codec92HD81

HPOUT

MICIN

SPEAKER

VREFOUT_A_OR_F

HP1_PORT_B_L

DigitalMICArray

DMIC_CLK/GPIO1

DMIC0/GPIO2

PORT_C_L

PORT_C_R

VREFOUT_C

InternalMIC

22

SPKR_PORT_D_L+

SPKR_PORT_D_L-

SPKR_PORT_D_R-

SPKR_PORT_D_R+

0R3-0-U-GP

AUD_SPK_L1_R

AUD_SPK_L2_R

AUD_SPK_R2_R

AUD_SPK_R1_R

AUD_SPK_L1

AUD_SPK_L2

AUD_SPK_R2

AUD_SPK_R1

HP1_PORT_B_R

AUD_HP1_JACK_L

AUD_HP1_JACK_R

50

44

HP0_PORT_A_L

HP0_PORT_A_R

AUD_EXT_MIC_L

AUD_EXT_MIC_R

AUD_VREFOUT_B

0R3-0-U-V-GP

47

50

SC1U10V3KX-3GP

4K7R2J-2-GP

INT_MIC_L_R

44

AUD_INT_MIC_L

AUD_INT_MIC_R

AUD_VREFOUT_C

33R2J-2-GP

AUD_DMIC_CLK

AUD_DMIC_IN033R2J-2-GP AUD_DMIC_IN0_R

AUD_DMIC_CLK_G_R

T8_THERMDA

T8_THERMDC

SC470P50V3JN-2GPMMBT3904-3-GP

3.HW T8 sensor

H_THERMDA

H_THERMDC

ThermalEMC2102

DP1

DN1

EMC2102_DP2

EMC2102_DN2

SC470P50V3JN-2GP

SC470P50V3JN-2GP

DP2

DN2

DP3

DN3

MMBT3904-3-GP

System sensor, putbetween CPU and NB.

CPUTHRMDA

THRMDC8

28

AA

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

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Alba UMA -1Table of Content

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Alba UMA

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Alba UMA

CFG19 DMI Lane Reversal 0 = Normal operation (Default): Lane Numbered inOrder

1 = Reverse LanesDMI x4 mode [MCH->ICH]: (3->0, 2->1, 1->2 and 0->3)DMI x2 mode [MCH->ICH]: (3->0, 2->1)

Pair Device01234567891011

HDA_SDOUTSignal

XOR Chain Entrance/PCIE Port Config1 bit1,Rising Edge of PWROK.

Usage/When SampledAllows entrance to XOR Chain testing when TP3pulled low. When TP3 not pulled low at rising edgeof PWROK, sets bit1 of RPC.PC (Cofig Registers:offset 224h). This signal has weak internal pull-down.

Comment

SATALED# PCI Express LaneReversal. Rising Edgeof PWROK.

Signal has weak internal pull-up. Sets bit 27of MPC.LR (Device 28: Function 0:Offset D8).

SPKRNo Reboot.Rising Edge of PWROK.

If sampled high, the system is strapped to the"No Reboot" mode (ICH9 will disable the TCO Timersystem reboot feature). The status is readablevia the NO REBOOT bit.

TP3XOR Chain Entrance.Rising Edge of PWROK.

The pull-up or pull-downactive when configured for native GLAN_DOCK#functionality and determinedby LAN controller.

CFG6 iTPM Host Interface1 = The iTPM Host Interface is disabled (default)

CFG7 Intel Managementengine crypto strap

CFG9

0 = Transport Layer Security (TLS) cipher

CFG20 Digital Display Port(SDVO/DP/iHDMI)Concurrent with PCIe

0 = Only Digital Display Port or PCIE isoperational (Default)

1 = Digital display Port and PCIe are operatingsimulataneously via the PEG port

SDVO_CTRLDATA

SDVO Present 0 = No SDVO Card Present (Default)

ICH9 EDS 642879 Rev.1.5

HDA_SYNC PCIE config1 bit0,Rising Edge of PWROK.

This signal has a weak internal pull-down.Sets bit0 of PRC.PC (Config Registers: Offset 224h).

GNT2#/GPIO53

PCIE config2 bit2,Rising Edge of PWROK.

This signal has a weak internal pull-up.Sets bit2 of PRC.PC2 (Config Registers: Offset 224h).

GPIO20 Reserved.

This signal should not be pull low unless usingXOR Chain testing.

GPIO33/HDA_DOCK_EN#

Flash DescriptorSecurity Override Strap. Rising Edge of PWROK.

Sampled low: the Flash Descriptor Security will beoverridden. If high, the security measures will bein effect. This should only be enabled inmanufacturing environments using an external pull-up resister.

Cantiga chipset and ICH9M I/O controllerHub strapping configuration

suite with no confidentiality1 = TLS cipher suite with confidentiality(Default)

PCIE Graphics Lane 0 = Reserved Lanes, 15->0, 14->1 ect..1 = Normal operation (Default): Lane Numbered in

Order

1 = SDVO Card Present

L_DDC_DATA Local Flat Panel(LFP) Present

0 = LFP Disabled (Default)1 = LFP Card Present; PCIE disabled

USB1USB2

RESERVED

Card Reader

MINI CARD

BLUETOOTH

CAMERA

NEW CARD

RESERVED

RESERVED

RESERVED

PULL-DOWN 20K

PULL-DOWN 20K

GPIO49

PULL-UP 20K

ICH9M Functional Strap Definitions ICH9 Integrated pull-upand pull-down Resistors

SIGNAL Resistor Type/Value

HDA_BIT_CLK

HDA_RST#HDA_SDIN[3:0]HDA_SDOUT

HDA_SYNC

GNT[3:0]#/GPIO[55,53,51]

GPIO20

LDA[3:0]#/FHW[3:0]#

LDRQ[0]

PME#PWRBTN#SATALED#

LAN_RXD[2:0]

LDRQ[1]/GPIO23

TP[3]

SPKR

SPI_CS1#/GPIO58/CLGPIO6

USB[11:0][P,N]

SPI_MOSI

SPI_MISO

TACH_[3:0]PULL-DOWN 20K

PULL-DOWN 15K

PULL-UP 20K

PULL-UP 20K

PULL-UP 20K

PULL-UP 20KPULL-UP 20KPULL-UP 20KPULL-UP 20KPULL-UP 15K

PULL-UP 20KPULL-DOWN 20KPULL-UP 20K

PULL-UP 20KPULL-UP 20K

PULL-DOWN 20KPULL-DOWN 20KPULL-DOWN 20KPULL-DOWN 20K

This signal should not be pulled high.

GNT1#/GPIO51

ESI Strap (Server Only)Rising Edge of PWROK.

ESI compatible mode is for server platforms only.This signal should not be pulled low for desktopand mobile.

GNT3#/GPIO55

Top-Block Swap override. Rising Edgeof PWROK.

Sampled low: Top-Block Swap mode (inverts A16 forall cycles targeting FWH BIOS space).Note: Software will not be able to clear theTop-Swap bit until the system is rebootedwithout GNT3# being pulled down.

GNT0#:SPI_CS1#/GPIO58

ICH9 EDS 642879 Rev.1.5 Montevina Platform Design guide 22339 Rev.0.5

CFG10 PCIE Loopback enable 0 = Enable (Note 3)1 = Disable (Default)

CFG[13:12] XOR/ALL

NOTE:

1. All strap signals are sampled with respect to the leading edge of the (G)MCH Power OK (PWROK) signal.2. iTPM can be disabled by a 'Soft-Strap' option in the Flash-decriptor section of the Firmware. This 'Soft-Strap' is activated only after enabling iTPM via CFG6. Only one of the CFG10/CFG12/CFG13 straps can be enabled at any time.

CL_CLK[1:0]CL_DATA[1:0]CL_RST0#DPRSLPVR/GPIO16ENERGY_DETECT

HDA_DOCK_EN#/GPIO33

011 = FSB667010 = FSB800others = Reserved

CFG[4:3]CFG[15:14]CFG[18:17]

00 = Reserve10 = XOR mode Enabled01 = ALLZ mode Enable (Note 3)11 = Disabled (Default)

CFG16 FSB Dynamic ODT 0 = Dynamic ODT Disabled1 = Dynamic ODT Enabled (Default)Boot BIOS Destination

Selection 0:1.Rising Edge of PWROK.

Controllable via Boot BIOS Destination bit(Config Registers: Offset 3410h:bit 11:10).GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC

SPI_MOSI Integrated TPM Enable,Rising Edge of CLPWROK.

Sample low: the Integrated TPM will be disable.Sample high: the MCH TPM enable strap is sampledlow and the TPM Disable bit is clear, theIntegrated TPM will be enable.

GLAN_DOCK#

PULL-UP 20K

PULL-DOWN 20KPULL-UP 20K

PULL-UP 20KPULL-UP 20KPULL-UP 20K

Pin Name

USBUSB TablePCIE Routing

LANE2

LANE3 LAN

MiniCard WLAN

GPIO49 DMI TerminationVoltage. Rising Edgeof CLPWROK.

The signal is required to be low for desktopapplications and required to be high for mobileapplications.

Strap Description Configuration

0 = The iTPM Host Interface is enabled (Note 2)

CFG[2:0] FSB Frequency Select 000 = FSB1067

CFG8Reserved

CFG5 DMI x2 Select 0 = DMI x21 = DMI x4 (Default)

LANE5 New Card USB3

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CLK_PCIE_NEWCLK_PCIE_NEW#

MINI1_CLKREQ#NEWCARD_CLKREQ#

NEWCARD_CLKREQ#

PCI2_TME

FSB

FSA

PCI2_TME

CLK_XTAL_OUT

CLKSATAREQ#

27_SELITP_EN

FSB

FSA

FSC

ITP_EN

CLK_XTAL_IN

CLKREQ#_1

FSC

27_SEL CLK_MCH_DREFCLK CLK_MCH_DREFCLK#

MCH_SSCDREFCLK1MCH_SSCDREFCLK1#

CLK_MCH_DREFCLK1#CLK_MCH_DREFCLK1

CLK_CPU_ITP1CLK_CPU_ITP1#

CLK_PCIE_MINI1_1#CLK_PCIE_MINI1_1

CLK_PCIE_ICH1

CLK_MCH_3GPLL1#CLK_MCH_3GPLL1

CLK_CPU_BCLK1#

CLK_MCH_BCLK1CLK_MCH_BCLK1#

CLK_CPU_BCLK1

CLK_PCIE_NEW1

CLK_PCIE_ICH1#

CLK_PCIE_NEW1#

CLK_PCIE_LAN1CLK_PCIE_LAN1#

CLK_PCIE_SATA1#CLK_PCIE_SATA1

CLK_PCIE_MINI2#CLK_PCIE_MINI2

3D3V_S0_CK505

+3.3V_RUN 3D3V_S0_CK505

3D3V_S0_CK505_IO

3D3V_S0_CK505

3D3V_S0_CK505_IO3D3V_S0_CK505+3.3V_RUN

+3.3V_RUN

CLK_48M_CARD50

PCLK_FWH43

CLK_48M_ICH20

H_STP_PCI#20H_STP_CPU#20

ICH_SMBCLK16,17,20,43ICH_SMBDATA16,17,20,43

CK_PWRGD20

CLKSATAREQ#20CLKREQ#_B11

PCLK_KBC26CLK_PCI_ICH19

CLK_14M_ICH20

CPU_BSEL28

CPU_BSEL18

CPU_BSEL08

MCH_CLKSEL0 11

MCH_CLKSEL1 11

MCH_CLKSEL2 11

CLK_CPU_ITP# 43CLK_CPU_ITP 43

CLK_PCIE_MINI1# 43CLK_PCIE_MINI1 43

CLK_CPU_BCLK 8CLK_CPU_BCLK# 8

CLK_MCH_BCLK# 10CLK_MCH_BCLK 10

NEWCARD_CLKREQ# 50

CLK_PCIE_NEW# 50CLK_PCIE_NEW 50

CLK_PCIE_ICH# 19CLK_PCIE_ICH 19

CLK_MCH_3GPLL# 11CLK_MCH_3GPLL 11

CLK_PCIE_SATA# 18CLK_PCIE_SATA 18

CLK_PCIE_LAN 25CLK_PCIE_LAN# 25

MINI1_CLKREQ# 43

MCH_SSCDREFCLK 11MCH_SSCDREFCLK# 11

CLK_MCH_DREFCLK 11CLK_MCH_DREFCLK# 11

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Alba UMA -1Clock Generator SLG8SP513VTR

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Alba UMA

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Alba UMA

SRCC11

Main source: 71.08513.003 (SLG8SP513VTR) Second source: 71.00875.C03 (RTM875N-606-VD-GRT)

SRCT11

PCI2_TME Output

0

1

Overclocking of CPU and SRC allowed

Overclocking of CPU and SRC not allowed

ITP_EN Output

0 SRC81 CPU_ITP

SSID = CLOCK

SEL1FSB

SEL0FSA

133M100M

166M800M

0 101 X

667M200M

0 1

CPUSEL2FSC FSB

0 10

101

1067M266M0 0 0

533M

UMADiscrete

27_SEL PIN 20 PIN 21

0 DOT96T DOT96C

1 SRCT0 SRCC0

for UMA

for UMA Rename for GPU clock

A00-0402

A00-0402

A00-0402

G

N

D

R

E

F

1

X22X13

V

D

D

R

E

F

4

REF0/FSLC/TEST_SEL5

SDATA6SCLK7

PCI0/CR#_A8

V

D

D

P

C

I

9

PCI1/CR#_B10PCI2/TME11PCI312PCI4/27_SELECT13PCI_F5/ITP_EN14

G

N

D

P

C

I

1

5

V

D

D

4

8

1

6

USB_48MHZ/FSLA17

G

N

D

4

8

1

8

V

D

D

9

6

_

I

O

1

9

SRCT0/DOTT_96 20SRCC0/DOTC_96 21

G

N

D

2

2

V

D

D

P

L

L

3

2

3

27MHZ_NONSS/SRCT1/SE1 2427MHZ_SS/SRCC1/SE2 25

G

N

D

2

6

V

D

D

P

L

L

3

_

I

O

2

7

SRCT2/SATAT 28SRCC2/SATAC 29

G

N

D

S

R

C

3

0

SRCT3/CR#_C 31SRCC3/CR#_D 32

V

D

D

S

R

C

_

I

O

3

3

SRCT4 34SRCC4 35

G

N

D

S

R

C

3

6

SRCT9 37SRCC9 38

SRCC11/CR#_G 39SRCT11/CR#_H 40

SRCT10 41SRCC10 42

V

D

D

S

R

C

_

I

O

4

3

CPU_STOP#44PCI_STOP#45

V

D

D

S

R

C

4

6

SRCC6 47SRCT6 48

G

N

D

S

R

C

4

9

SRCC7/CR#_E 50SRCT7/CR#_F 51

V

D

D

S

R

C

_

I

O

5

2

CPUC2_ITP/SRCC8 53CPUT2_ITP/SRCT8 54

NC#5555

V

D

D

C

P

U

_

I

O

5

6

CPUC1_F 57CPUT1_F 58

G

N

D

C

P

U

5

9

CPUC0 60CPUT0 61V

D

D

C

P

U

6

2

CK_PWRGD/PD#63

FSLB/TEST_MODE64

G

N

D

6

5

U701ICS9LPRS355BKLFT-GP-U

U701ICS9LPRS355BKLFT-GP-U

1

2

C

7

0

3

S

C

D

1

U

1

6

V

2

K

X

-

3

G

P

C

7

0

3

S

C

D

1

U

1

6

V

2

K

X

-

3

G

P

1

2

R717Do Not StuffDYR717Do Not StuffDY

1 2R708 475R2F-L1-GPR708 475R2F-L1-GP

1

2

EC702Do Not StuffDY EC702Do Not StuffDY

12 3

4

RN

Do Not StuffRN711

RN

Do Not StuffRN711

1 2R710 33R2J-2-GPR710 33R2J-2-GP

12 3

4

RN

Do Not StuffRN705

RN

Do Not StuffRN705

12 R703Do Not Stuff

R703Do Not Stuff

1

2

C

7

1

5

S

C

1

U

1

0

V

3

K

X

-

3

G

P

C

7

1

5

S

C

1

U

1

0

V

3

K

X

-

3

G

P

12 3

4

RN

Do Not StuffRN706

RN

Do Not StuffRN706

1

2

C

7

1

6

S

C

1

0

U

6

D

3

V

5

M

X

-

3

G

P

C

7

1

6

S

C

1

0

U

6

D

3

V

5

M

X

-

3

G

P

1

2

C711SC12P50V2JN-3GPC711SC12P50V2JN-3GP

1

2

C

7

0

9

D

o

N

o

t

S

t

u

f

f

DY C 70

9

D

o

N

o

t

S

t

u

f

f

DY

1

2

C

7

2

0

S

C

D

1

U

1

6

V

2

K

X

-

3

G

P

C

7

2

0

S

C

D

1

U

1

6

V

2

K

X

-

3

G

P

1 2R707 Do Not StuffDYR707 Do Not StuffDY

1

2

C

7

0

4

S

C

D

1

U

1

6

V

2

K

X

-

3

G

P

C

7

0

4

S

C

D

1

U

1

6

V

2

K

X

-

3

G

P

1

2

C

7

2

3

D

o

N

o

t

S

t

u

f

f

DY C 72

3

D

o

N

o

t

S

t

u

f

f

DY

1 2R709 33R2J-2-GPR709 33R2J-2-GP

1

2

C

7

0

1

S

C

1

U

1

0

V

3

K

X

-

3

G

P

C

7

0

1

S

C

1

U

1

0

V

3

K

X

-

3

G

P

1 2R721 1KR2J-1-GPR721 1KR2J-1-GP

1

2

R71410KR2J-3-GPR71410KR2J-3-GP

1

2

R716Do Not StuffDY R716Do Not StuffDY

12 3

4

RN

Do Not StuffRN709

RN

Do Not StuffRN709

12 3

4

RN

Do Not StuffRN704

RN

Do Not StuffRN704

1 TP701TP701

1 2R701 10KR2J-3-GPR701 10KR2J-3-GP

1

2

C

7

1

3

D

o

N

o

t

S

t

u

f

f

DY C 71

3

D

o

N

o

t

S

t

u

f

f

DY

1

2

E

C

7

0

1

S

C

2

2

P

5

0

V

2

J

N

-

4

G

P

E

C

7

0

1

S

C

2

2

P

5

0

V

2

J

N

-

4

G

P

1 2C714 Do Not StuffDYC714 Do Not StuffDY

1 2R719 0R2J-2-GPR719 0R2J-2-GP

1 2R70622R2J-2-GP

R70622R2J-2-GP

1 TP702TP702

1

2

C

7

1

7

S

C

D

1

U

1

6

V

2

K

X

-

3

G

P

C

7

1

7

S

C

D

1

U

1

6

V

2

K

X

-

3

G

P

1 2R723 1KR2J-1-GPR723 1KR2J-1-GP

1 2R704Do Not Stuff

R704Do Not Stuff

1

2

C

7

1

9

S

C

D

1

U

1

6

V

2

K

X

-

3

G

P

C

7

1

9

S

C

D

1

U

1

6

V

2

K

X

-

3

G

P

1

2

C

7

1

8

S

C

D

1

U

1

6

V

2

K

X

-

3

G

P

C

7

1

8

S

C

D

1

U

1

6

V

2

K

X

-

3

G

P

12 3

4

RN

Do Not StuffRN707

RN

Do Not StuffRN707

12 3

4

RN

Do Not StuffRN702

RN

Do Not StuffRN702

1 2R705 22R2J-2-GPR705 22R2J-2-GP

1 2R722 1KR2J-1-GPR722 1KR2J-1-GP

1

2

C

7

0

2

D

o

N

o

t

S

t

u

f

f

DY C 70

2

D

o

N

o

t

S

t

u

f

f

DY

1

2

C

7

0

5

S

C

D

1

U

1

6

V

2

K

X

-

3

G

P

C

7

0

5

S

C

D

1

U

1

6

V

2

K

X

-

3

G

P

1 2R720 2K2R2J-2-GPR720 2K2R2J-2-GP

12 3

4

RN

Do Not StuffRN710

RN

Do Not StuffRN7101

2

C708SC12P50V2JN-3GPC708SC12P50V2JN-3GP

1

2

C

7

1

2

S

C

D

1

U

1

6

V

2

K

X

-

3

G

P

C

7

1

2

S

C

D

1

U

1

6

V

2

K

X

-

3

G

P

1

2

C

7

2

2

D

o

N

o

t

S

t

u

f

f

DY C 72

2

D

o

N

o

t

S

t

u

f

f

DY

1

2

C

7

0

7

S

C

D

1

U

1

6

V

2

K

X

-

3

G

P

C

7

0

7

S

C

D

1

U

1

6

V

2

K

X

-

3

G

P

1

2

C

7

1

0

D

o

N

o

t

S

t

u

f

f

DY C 71

0

D

o

N

o

t

S

t

u

f

f

DY1 2X701

X-14D31818M-50GP

X701

X-14D31818M-50GP

1

2

C

7

0

6

S

C

D

1

U

1

6

V

2

K

X

-

3

G

P

C

7

0

6

S

C

D

1

U

1

6

V

2

K

X

-

3

G

P

1 2R702 10KR2J-3-GPR702 10KR2J-3-GP

1

2

EC703Do Not StuffDY EC703Do Not StuffDY

1

2

C

7

2

4

D

o

N

o

t

S

t

u

f

f

DY C 72

4

D

o

N

o

t

S

t

u

f

f

DY

1 2R718 10KR2J-3-GPR718 10KR2J-3-GP

1

2


12 3

4

RN

Do Not StuffRN708

RN

Do Not StuffRN708

1

2


12 3

4RN

Do Not StuffRN703RN

Do Not StuffRN703

1

2

C

7

2

1

D

o

N

o

t

S

t

u

f

f

DY C 72

1

D

o

N

o

t

S

t

u

f

f

DY

12 3

4

RN

Do Not StuffRN701

RN

Do Not StuffRN701

1 2R711 33R2J-2-GPR711 33R2J-2-GP

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

H_A#3H_A#4H_A#5H_A#6H_A#7H_A#8H_A#9H_A#10H_A#11H_A#12H_A#13H_A#14H_A#15H_A#16

H_REQ#0H_REQ#1H_REQ#2H_REQ#3H_REQ#4

H_A#[35..3]

ITP_TCKITP_TDI

ITP_TMSITP_TRST#

ITP_TDO

ITP_DBRESET#

ITP_BPM#5

RSVD_CPU_4

RSVD_CPU_1

RSVD_CPU_8

RSVD_CPU_5RSVD_CPU_6RSVD_CPU_7

RSVD_CPU_2RSVD_CPU_3

H_A#35

H_A#33

RSVD_CPU_9RSVD_CPU_10

H_A#18

H_A#20H_A#21H_A#22

H_A#17

H_A#19

H_A#23H_A#24H_A#25H_A#26H_A#27H_A#28H_A#29H_A#30H_A#31

H_RS#1H_RS#0

H_RS#2

H_CPURST#

RSVD_CPU_11

H_A#34

H_A#32

CPU_IERR#

ITP_BPM#0ITP_BPM#1ITP_BPM#2ITP_BPM#3ITP_BPM#4

H_THERMDCH_THERMDA

CPU_TEST3

H_D#32H_D#33H_D#34H_D#35H_D#36H_D#37H_D#38H_D#39

H_D#41H_D#40

H_D#42H_D#43H_D#44H_D#45H_D#46H_D#47

TEST1TEST2

COMP0COMP1COMP2COMP3

H_D#0H_D#1H_D#2H_D#3H_D#4H_D#5H_D#6H_D#7H_D#8H_D#9H_D#10H_D#11H_D#12H_D#13H_D#14H_D#15

CPU_GTLREF0

H_D#16H_D#17H_D#18H_D#19H_D#20H_D#21H_D#22H_D#23H_D#24H_D#25H_D#26H_D#27H_D#28H_D#29H_D#30H_D#31

H_D#48H_D#49

H_D#51H_D#50

H_D#52H_D#53H_D#54H_D#55

H_D#57H_D#56

H_D#58H_D#59H_D#60H_D#61

H_D#63H_D#62

CPU_TEST5

H_D#[63..0]

H_DSTBN#[3..0]H_DSTBP#[3..0]

H_DINV#[3..0]+1.05V_VCCP

+1.05V_VCCP

+1.05V_VCCP

+1.05V_VCCP

H_RS#[2..0] 10

H_ADSTB#110

H_FERR#18H_IGNNE#18

H_A20M#18

H_LOCK# 10

H_INIT# 18

H_ADS# 10H_BNR# 10

H_DRDY# 10H_DBSY# 10

H_BREQ#0 10

H_BPRI# 10

H_DEFER# 10

H_STPCLK#18H_INTR18H_NMI18H_SMI#18

H_HIT# 10H_HITM# 10

H_TRDY# 10

H_ADSTB#010H_REQ#[4..0]10

H_A#[35..3]10

H_CPURST# 10,43

H_THRMTRIP# 11,18,26,30,54

CLK_CPU_BCLK 7CLK_CPU_BCLK# 7

CPU_PROCHOT# 34

ITP_BPM#0 43ITP_BPM#1 43ITP_BPM#2 43ITP_BPM#3 43ITP_BPM#4 43ITP_BPM#5 43ITP_TCK 43ITP_TDI 43

ITP_TDO 43ITP_TMS 43ITP_TRST# 43ITP_DBRESET# 20,43

H_DSTBN#2 10H_DSTBP#2 10H_DINV#2 10

H_DSTBN#3 10H_DSTBP#3 10H_DINV#3 10

H_DPRSTP# 11,18,34H_DPSLP# 18H_DPWR# 10H_PWRGOOD 18,30H_CPUSLP# 10

H_D#[63..0] 10

H_DINV#[3..0] 10H_DSTBN#[3..0] 10H_DSTBP#[3..0] 10

H_DSTBN#010H_DSTBP#010H_DINV#010

H_DSTBN#110H_DSTBP#110H_DINV#110

CPU_BSEL27

CPU_BSEL07CPU_BSEL17

PSI# 34

H_THERMDA 28H_THERMDC 28

Title


Date: Sheet of


Alba UMA -1CPU-FSB(1/2)

Custom


Alba UMA

Title


Date: Sheet of



Custom


Alba UMA

Title


Date: Sheet of



Custom


Alba UMA

TEST7

62.10040.221

SSID = CPU

Layout notes Z= 55 Ohm 0.5" MAX for CPU_GTLREF0 62.10040.221

Layout Note:Comp0, 2 connect with Zo=27.4 ohm, maketrace length shorter than 0.5".Comp1, 3 connect with Zo=55 ohm, maketrace length shorter than 0.5".

H_THRMTRIP# should connect toICH9 and MCH without T-ing.

X01-0112

TP801TP801

1 2R802 54D9R2F-L1-GPR802 54D9R2F-L1-GP

TP802TP802

1

2

R8141KR2F-3-GPR8141KR2F-3-GP




A3#J4A4#L5A5#L4A6#K5A7#M3A8#N2A9#J1A10#N3A11#P5A12#P2A13#L2A14#P4A15#P1A16#R1

A20M#A6

ADS# H1

ADSTB0#M1

REQ0#K3REQ1#H2REQ2#K2REQ3#J3REQ4#L1

A17#Y2A18#U5A19#R3A20#W6A21#U4A22#Y5

A30#U2

A24#R4A25#T5A26#T3

A32#W3

A28#W5A29#Y4A27#W2

A31#V4

A33#AA4A34#AB2A35#AA3

FERR#A5IGNNE#C4

RSVD#M4M4RSVD#N5N5RSVD#T2T2RSVD#V3V3RSVD#B2B2RSVD#C3C3

BNR# E2BPRI# G5

DEFER# H5

DBSY# E1DRDY# F21

BR0# F1

IERR# D20INIT# B3

LOCK# H4

RS0# F3RS1# F4RS2# G3

TRDY# G2

HIT# G6HITM# E4

BPM0# AD4BPM1# AD3BPM2# AD1BPM3# AC4PRDY# AC2PREQ# AC1

TCK AC5TDI AA6

TDO AB3TMS AB5

TRST# AB6DBR# C20

PROCHOT# D21THRMDA A24

THERMTRIP# C7

BCLK0 A22BCLK1 A21

RSVD#D2D2

RSVD#F6F6RSVD#D3D3RSVD#D22D22

STPCLK#D5LINT0C6LINT1B4SMI#A3

A23#U1

ADSTB1#V1

RESET# C1

KEY_NCB1

THRMDC B25

1 OF 4

R

E

S

E

R

V

E

D

HCLK

THERMAL

ADDR GROUP 1

X

D

P

/

I

T

P

S

I

G

N

A

L

S

C

O

N

T

R

O

L

ADDR GROUP 0

ICH

CPU1A

BGA479-SKT6-GPU7

1 OF 4

R

E

S

E

R

V

E

D

HCLK

THERMAL

ADDR GROUP 1

X

D

P

/

I

T

P

S

I

G

N

A

L

S

C

O

N

T

R

O

L

ADDR GROUP 0

ICH

CPU1A

BGA479-SKT6-GPU7

TP803TP803

1

2

C802SC1KP50V2KX-1GPC802SC1KP50V2KX-1GP


TP804TP804

1

2

R8132KR2F-3-GP

R8132KR2F-3-GP

TP807TP807TP808TP808

1 2R812 27D4R2F-L1-GPR812 27D4R2F-L1-GP

1 TP814TP814

1 2R806 56R2J-4-GPR806 56R2J-4-GP

1 2R811 54D9R2F-L1-GPR811 54D9R2F-L1-GP

TP806TP806


1 2R803 27D4R2F-L1-GPR803 27D4R2F-L1-GP

D16#N22D17#K25D18#P26D19#R23D20#L23D21#M24D22#L22D23#M23D24#P25D25#P23D26#P22D27#T24D28#R24D29#L25D30#T25D31#N25

DINV0#H25

DINV1#N24

DSTBN0#J26

DSTBN1#L26

DSTBP0#H26

DSTBP1#M26

D0#E22D1#F24D2#E26D3#G22D4#F23D5#G25D6#E25D7#E23D8#K24D9#G24D10#J24D11#J23D12#H22D13#F26D14#K22D15#H23

D53# AC26

D60# AC22

D63# AC23

GTLREFAD26

TEST2D25

BSEL0B22BSEL1B23BSEL2C21

DINV2# U22

D32# Y22D33# AB24D34# V24D35# V26D36# V23

D38# U25D39# U23D40# Y25D41# W22D42# Y23D43# W24D44# W25D45# AA23D46# AA24D47# AB25

DSTBP2# AA26DSTBN2# Y26

D48# AE24D49# AD24

D52# AB21

D54# AD20D55# AE22D56# AF23D57# AC25D58# AE21D59# AD21

D61# AD23

DINV3# AC20DSTBN3# AE25

D51# AB22D50# AA21

D62# AF22

COMP0 R26COMP1 U26

DPRSTP# E5DPSLP# B5DPWR# D24

PWRGOOD D6SLP# D7PSI# AE6

TEST1C23

TEST6A26

TEST3C24

TEST5AF1TEST4AF26

D37# T22

DSTBP3# AF24

COMP2 AA1COMP3 Y1

2 OF 4

DATA GRP0

DATA GRP1

D

A

T

A

G

R

P

2

D

A

T

A

G

R

P

3

MISC

CPU1B

BGA479-SKT6-GPU7

2 OF 4

DATA GRP0

DATA GRP1

D

A

T

A

G

R

P

2

D

A

T

A

G

R

P

3

MISC

CPU1B

BGA479-SKT6-GPU7

TP813TP813

1 2R804 56R2J-4-GPR804 56R2J-4-GP

TP805TP805

TP810TP810


TP809TP809

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CPU_VID6

CPU_VID0CPU_VID1CPU_VID2CPU_VID3CPU_VID4CPU_VID5

CPU_GND3CPU_GND2

CPU_GND4

CPU_GND1

VCC_SENSE_1

VSS_SENSE_1

+VCC_CORE

+1.5V_RUN+1.5V_VCCA

+1.05V_VCCP

+VCC_CORE

+VCC_CORE

+VCC_CORE

+VCC_CORE

+VCC_CORE

CPU_VID[6..0] 34

VCC_SENSE 34

VSS_SENSE 34

Title


Date: Sheet of


Alba UMA -1CPU-Power(2/2)

Custom


Alba UMA

Title


Date: Sheet of



Custom


Alba UMA

Title


Date: Sheet of



Custom


Alba UMA

layout note: "+1.5V_VCCA"as short as possible

VCC_SENSE and VSS_SENSE linesshould be of equal length.

Layout Note:Place as close as possibleto the CPU VCCA pin.

NCTFPIN

62.10040.221

62.10040.221

SSID = CPU

X01-0106

X01-0106

X01-0106

A00-0402

TP904TP9041

2

C

9

3

2

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

C

9

3

2

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

1

2

C

9

2

4

S

C

1

U

6

D

3

V

2

K

X

-

G

P

C

9

2

4

S

C

1

U

6

D

3

V

2

K

X

-

G

P

1 2PG902 Do Not StuffPG902 Do Not Stuff

1

2

C

9

1

3

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

C

9

1

3

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

1

2

C

9

3

1

D

o

N

o

t

S

t

u

f

f

DY C 93

1

D

o

N

o

t

S

t

u

f

f

DY

1

2

C914SC22U6D3V5MX-2GPC914SC22U6D3V5MX-2GP

1

2

C

9

2

5

S

C

1

U

1

0

V

2

K

X

-

1

G

P

C

9

2

5

S

C

1

U

1

0

V

2

K

X

-

1

G

P

1

2

C

9

3

3

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

C

9

3

3

S

C

2

2

U

6

D

3

V

5

M

X

-

2

G

P

1

2

C

9

0

3

D

o

N

o

t

S

t

u

f

f

DY C 90

3

D

o

N

o

t

S

t

u

f

f

DY

TP901TP901

VSSAF2

VSSA4VSSA8VSSA11VSSA14VSSA16VSSA19VSSA23

VSSB6VSSB8VSSB11VSSB13VSSB16VSSB19VSSB21VSSB24VSSC5VSSC8VSSC11VSSC14VSSC16VSSC19VSSC2VSSC22VSSC25VSSD1VSSD4VSSD8VSSD11VSSD13VSSD16VSSD19VSSD23VSSD26VSSE3VSSE6VSSE8VSSE11VSSE14VSSE16VSSE19VSSE21VSSE24VSSF5VSSF8VSSF11VSSF13VSSF16VSSF19VSSF2VSSF22VSSF25VSSG4VSSG1VSSG23VSSG26VSSH3VSSH6VSSH21VSSH24VSSJ2VSSJ5VSSJ22VSSJ25VSSK1VSSK4VSSK23VSSK26VSSL3VSSL6VSSL21VSSL24VSSM2VSSM5VSSM22VSSM25VSSN1VSSN4VSSN23VSSN26VSSP3

VSS P6VSS P21VSS P24VSS R2VSS R5VSS R22VSS R25VSS T1VSS T4VSS T23VSS T26VSS U3VSS U6VSS U21VSS U24VSS V2VSS V5VSS V22VSS V25VSS W1VSS W4VSS W23VSS W26VSS Y3VSS Y6VSS Y21VSS Y24VSS AA2VSS AA5VSS AA8VSS AA11VSS AA14VSS AA16VSS AA19VSS AA22VSS AA25VSS AB1VSS AB4VSS AB8VSS AB11VSS AB13VSS AB16VSS AB19VSS AB23VSS AB26VSS AC3VSS AC6VSS AC8VSS AC11VSS AC14VSS AC16VSS AC19VSS AC21VSS AC24VSS AD2VSS AD5VSS AD8VSS AD11VSS AD13VSS AD16VSS AD19VSS AD22VSS AD25VSS AE1VSS AE4VSS AE8VSS AE11VSS AE14VSS AE16VSS AE19VSS AE23VSS AE26VSS A2VSS AF6VSS AF8VSS AF11VSS AF13VSS AF16VSS AF19VSS AF21VSS A25VSS AF25

4 OF 4CPU1D

BGA479-SKT6-GPU7

4 OF 4CPU1D

BGA479-SKT6-GPU7

1

2

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9

3

7

S

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2

2

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7

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1 2R902

100R2F-L1-GP-U

R902

100R2F-L1-GP-U

1

2

C

9

1

1

S

C

2

2

U

6

D

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9

1

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0

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S

C

1

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1

0

V

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K

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-

1

G

P

C

9

0

5

S

C

1

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1

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-

1

G

P

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0

9

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1

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S

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DY C 91

2

D

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N

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t

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t

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f

f

DY

1 2R901

100R2F-L1-GP-U

R901

100R2F-L1-GP-U

1

2

C

9

0

4

S

C

1

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K

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9

2

9

D

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DY C 92

9

D

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N

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DY

1

2


1

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C

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3

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0

6

S

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1

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1

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K

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1

G

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C

9

0

6

S

C

1

U

1

0

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2

K

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-

1

G

P

1

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9

2

7

S

C

2

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1

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DY C 92

2

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DY

TP902TP9021

2

C

9

0

2

D

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N

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t

S

t

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f

f

DY C 90

2

D

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DY

1

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T

C

9

0

1

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DY

T

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0

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DY

1

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DY C 93

4

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DY

1

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0

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8

D

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1

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2

0

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DY C 92

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DY

1

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DY C 93

6

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DY

1

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C

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0

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DY C 90

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DY

TP903TP903

1

2

C

9

2

3

S

C

1

U

1

0

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K

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1

G

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C

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0

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DY

1

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9

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DY

1

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VCCA7VCCA9

VCCAC10

VCCA10VCCA12VCCA13VCCA15VCCA17VCCA18VCCA20VCCB7VCCB9VCCB10VCCB12VCCB14VCCB15VCCB17VCCB18VCCB20VCCC9VCCC10VCCC12VCCC13VCCC15VCCC17VCCC18VCCD9VCCD10VCCD12VCCD14VCCD15VCCD17VCCD18VCCE7VCCE9VCCE10VCCE12VCCE13VCCE15

VCCAA7VCCAA9VCCAA10VCCAA12VCCAA13VCCAA15VCCAA17VCCAA18VCCAA20VCCAB9

VCCAB12VCCAB14VCCAB15VCCAB17VCCAB18

VCCE17VCCE18VCCE20VCCF7VCCF9VCCF10VCCF12VCCF14VCCF15VCCF17VCCF18VCCF20

VCC AB20VCC AB7VCC AC7VCC AC9VCC AC12VCC AC13VCC AC15VCC AC17VCC AC18VCC AD7VCC AD9VCC AD10VCC AD12VCC AD14VCC AD15VCC AD17VCC AD18VCC AE9VCC AE10VCC AE12VCC AE13VCC AE15VCC AE17VCC AE18VCC AE20VCC AF9VCC AF10VCC AF12VCC AF14VCC AF15VCC AF17VCC AF18VCC AF20

VCCP G21

VCCP J6

VCCP J21VCCP K6

VCCP K21VCCP M6

VCCP M21

VCCP N6VCCP N21

VCCP R6VCCP R21

VCCP T6VCCP T21

VCCP V6

VCCP V21VCCP W21

VCCA B26VCCA C26

VID0 AD6

VID6 AE2VID4 AE3VID2 AE5

VID5 AF3VID3 AF4VID1 AF5

VSSSENSE AE7

VCCSENSE AF7VCCAB10

3 OF 4CPU1C

BGA479-SKT6-GPU7

3 OF 4CPU1C

BGA479-SKT6-GPU71 2PG901 Do Not StuffPG901 Do Not Stuff

1

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DY C 91

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C939SCD01U16V2KX-3GP


1 2

R903Do Not Stuff

R903Do Not Stuff

1

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55

4

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1

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D D

C C

B B

A A

H_D#[63..0]H_D#0H_D#1H_D#2H_D#3H_D#4H_D#5H_D#6H_D#7H_D#8H_D#9H_D#10H_D#11H_D#12H_D#13H_D#14H_D#15H_D#16H_D#17H_D#18H_D#19H_D#20H_D#21H_D#22H_D#23H_D#24H_D#25H_D#26H_D#27H_D#28H_D#29H_D#30H_D#31H_D#32H_D#33H_D#34H_D#35H_D#36H_D#37H_D#38H_D#39H_D#40H_D#41H_D#42H_D#43H_D#44H_D#45H_D#46H_D#47H_D#48H_D#49H_D#50H_D#51H_D#52H_D#53H_D#54H_D#55H_D#56H_D#57H_D#58H_D#59H_D#60H_D#61H_D#62H_D#63

H_AVREF

H_RCOMP

H_SWING

H_SWINGH_RCOMP

H_DINV#0

H_RS#1

H_DSTBN#0

H_REQ#2

H_DSTBP#0

H_REQ#4H_REQ#3

H_RS#0

H_DINV#3

H_DSTBN#3

H_DSTBP#3

H_REQ#1

H_DINV#2

H_DSTBN#2

H_DSTBP#2

H_REQ#0

H_DINV#1

H_RS#2

H_DSTBN#[3..0]

H_DSTBN#1

H_DSTBP#[3..0]

H_DSTBP#1

H_DINV#[3..0]

H_A#6

H_A#16

H_A#34

H_A#32

H_A#22

H_A#20

H_A#26

H_A#11

H_A#5

H_A#31

H_A#3

H_A#9

H_A#15

H_A#21

H_A#19

H_A#25

H_A#4

H_A#30H_A#29

H_A#8

H_A#14

H_A#18

H_A#24

H_A#28

H_A#7

H_A#13

H_A#17

H_A#12

H_A#35

H_A#33

H_A#23

H_A#27

H_A#10

H_A#[35..3]

H_REQ#[4..0]

H_RS#[2..0]

+1.05V_VCCP

+1.05V_VCCP

H_D#[63..0]8

H_CPURST#8,43H_CPUSLP#8

H_DINV#[3..0] 8

H_DSTBN#[3..0] 8

H_DSTBP#[3..0] 8

H_REQ#[4..0] 8

H_RS#[2..0] 8

H_BNR# 8

H_BREQ#0 8

H_ADS# 8H_ADSTB#0 8H_ADSTB#1 8

H_DBSY# 8

H_DRDY# 8H_HIT# 8H_HITM# 8H_LOCK# 8

H_BPRI# 8

H_DEFER# 8

H_DPWR# 8

H_TRDY# 8

H_A#[35..3] 8

CLK_MCH_BCLK 7CLK_MCH_BCLK# 7

Title


Date: Sheet of


Alba UMA -1Cantiga-HOST(1/6)

Custom


Alba UMA

Title


Date: Sheet of



Custom


Alba UMA

Title


Date: Sheet of



Custom


Alba UMA

Place R1001 near to the chip ( < 0.5")

H_RCOMP routing Trace width andSpacing use 10 / 20 mil

H_SWING routing Trace width andSpacing use 10 / 20 mil

H_SWING Resistors andCapacitors close MCH500 mil ( MAX )

SSID = MCH

1

2

R1003221R2F-2-GPR1003221R2F-2-GP

1

2

C1002Do Not StuffDY C1002Do Not StuffDY

1

2

C1001SCD1U10V2KX-4GPC1001SCD1U10V2KX-4GP

1

2

R1002100R2F-L1-GP-UR1002100R2F-L1-GP-U

1

2


H_A#_10 P16H_A#_11 R16H_A#_12 N17H_A#_13 M13H_A#_14 E17H_A#_15 P17H_A#_16 F17H_A#_17 G20H_A#_18 B19H_A#_19 J16H_A#_20 E20H_A#_21 H16H_A#_22 J20H_A#_23 L17H_A#_24 A17H_A#_25 B17H_A#_26 L16H_A#_27 C21H_A#_28 J17H_A#_29 H20

H_A#_3 A14

H_A#_30 B18H_A#_31 K17

H_A#_4 C15H_A#_5 F16H_A#_6 H13H_A#_7 C18H_A#_8 M16H_A#_9 J13

H_ADS# H12H_ADSTB#_0 B16H_ADSTB#_1 G17

H_BNR# A9H_BPRI# F11

H_BREQ# G12

HPLL_CLK# AH6

H_CPURST#C12

HPLL_CLK AH7

H_D#_0F2

H_REQ#_2 F13H_REQ#_3 B13

H_D#_1G8

H_D#_10M9

H_D#_20L6

H_D#_30N10

H_D#_40AA8

H_D#_50AA2

H_D#_60AE11

H_D#_8D4H_D#_9H3

H_DBSY# B10

H_D#_11M11H_D#_12J1H_D#_13J2H_D#_14N12H_D#_15J6H_D#_16P2H_D#_17L2H_D#_18R2H_D#_19N9

H_D#_2F8

H_D#_21M5H_D#_22J3H_D#_23N2H_D#_24R1H_D#_25N5H_D#_26N6H_D#_27P13H_D#_28N8H_D#_29L7

H_D#_3E6

H_D#_31M3H_D#_32Y3H_D#_33AD14H_D#_34Y6H_D#_35Y10H_D#_36Y12H_D#_37Y14H_D#_38Y7H_D#_39W2

H_D#_4G2

H_D#_41Y9H_D#_42AA13H_D#_43AA9H_D#_44AA11H_D#_45AD11H_D#_46AD10H_D#_47AD13H_D#_48AE12H_D#_49AE9

H_D#_5H6

H_D#_51AD8H_D#_52AA3H_D#_53AD3H_D#_54AD7H_D#_55AE14H_D#_56AF3H_D#_57AC1H_D#_58AE3H_D#_59AC3

H_D#_6H2

H_D#_61AE8H_D#_62AG2H_D#_63AD6

H_D#_7F6

H_DEFER# E9

H_DINV#_0 J8H_DINV#_1 L3H_DINV#_2 Y13H_DINV#_3 Y1

H_DPWR# J11H_DRDY# F9

H_DSTBN#_0 L10H_DSTBN#_1 M7H_DSTBN#_2 AA5H_DSTBN#_3 AE6

H_DSTBP#_0 L9H_DSTBP#_1 M8H_DSTBP#_2 AA6H_DSTBP#_3 AE5

H_AVREFA11H_DVREFB11

H_TRDY# C9

H_HIT# H9H_HITM# E12

H_LOCK# H11

H_REQ#_0 B15H_REQ#_1 K13

H_REQ#_4 B14

H_A#_32 B20H_A#_33 F21H_A#_34 K21H_A#_35 L20

H_SWINGC5

H_CPUSLP#E11

H_RCOMPE3

H_RS#_0 B6H_RS#_1 F12H_RS#_2 C8

H

O

S

T

1 OF 10U1001A

CANTIGA-GM-GP-U-NF

H

O

S

T

1 OF 10U1001A

CANTIGA-GM-GP-U-NF

1

2


1 2R1001 24D9R2F-L-GPR1001 24D9R2F-L-GP

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DMI_IRXN3_MTXN3

DMI_ITXN2_MRXN2DMI_ITXN1_MRXN1DMI_ITXN0_MRXN0

TSATN#

DMI_ITXN3_MRXN3

DMI_IRXP3_MTXP3DMI_IRXP2_MTXP2DMI_IRXP1_MTXP1DMI_IRXP0_MTXP0

DMI_ITXP2_MRXP2DMI_ITXP1_MRXP1DMI_ITXP0_MRXP0

DMI_IRXN2_MTXN2DMI_IRXN1_MTXN1DMI_IRXN0_MTXN0

SM_RCOMP_VOHSM_RCOMP_VOL

CFG5CFG6CFG7CFG8CFG9CFG10CFG11CFG12CFG13

CFG16

CFG18

CFG20CFG19

MCH_CLVREF

SM_REXT

RSTIN#PWROK_R

CFG13

CFG18

M_RCOMPPM_RCOMPN

CFG7

CFG9

CFG8

CFG5

CFG16

CFG11

CFG10

CFG12

CFG19

CFG6

PM_EXTTS#1PM_EXTTS#0

TSATN#_KBC

TSATN#

SM_RCOMP_VOH

SM_RCOMP_VOL

CLK_MCH_3GPLL#CLK_MCH_3GPLL

CANTIGA_SM_VREF

CLKREQ#_B

CFG3CFG4

CFG14CFG15

CFG17

CFG20

CLK_MCH_DREFCLK#CLK_MCH_DREFCLK

MCH_SSCDREFCLK#MCH_SSCDREFCLK

DMI_ITXP3_MRXP3

+1.05V_VCCP

+3.3V_RUN

+3.3V_RUN+1.05V_VCCP

+3.3V_RUN

+1.8V_SUS

+1.8V_SUS

+1.8V_SUS

+V_DDR_MCH_REF

DMI_IRXN0_MTXN0 19

DMI_ITXN0_MRXN0 19DMI_ITXN1_MRXN1 19DMI_ITXN2_MRXN2 19DMI_ITXN3_MRXN3 19

DMI_IRXN1_MTXN1 19DMI_IRXN2_MTXN2 19DMI_IRXN3_MTXN3 19

DMI_IRXP0_MTXP0 19

DMI_IRXP2_MTXP2 19DMI_IRXP3_MTXP3 19

DMI_IRXP1_MTXP1 19

MCH_CLKSEL17MCH_CLKSEL27

MCH_CLKSEL07

M_CLK_DDR#2 17M_CLK_DDR#3 17

M_CLK_DDR0 16M_CLK_DDR1 16

M_CKE0 16M_CKE1 16M_CKE2 17M_CKE3 17

M_CLK_DDR2 17M_CLK_DDR3 17

M_CS1# 16M_CS2# 17M_CS3# 17

M_CS0# 16

M_CLK_DDR#0 16M_CLK_DDR#1 16

M_ODT0 16M_ODT1 16M_ODT2 17M_ODT3 17

CL_CLK0 20CL_DATA0 20

H_DPRSTP#8,18,34PM_SYNC#20

PLT_RST#19,25,26,43,50

PM_PWROK20,26,28

DPRSLPVR20,34H_THRMTRIP#8,18,26,30,54

MCH_ICH_SYNC# 20

PM_EXTTS#016PM_EXTTS#117

TSATN#_KBC 26

M_PWROK 20CL_RST#0 20

CLK_MCH_3GPLL 7CLK_MCH_3GPLL# 7

CLKREQ#_B 7

CLK_MCH_DREFCLK 7CLK_MCH_DREFCLK# 7MCH_SSCDREFCLK 7MCH_SSCDREFCLK# 7

DMI_ITXP0_MRXP0 19DMI_ITXP1_MRXP1 19DMI_ITXP2_MRXP2 19DMI_ITXP3_MRXP3 19

Title


Date: Sheet of


Alba UMA -1Cantiga-DMI/CFG(2/6)

Custom


Alba UMA

Title


Date: Sheet of



Custom


Alba UMA

Title


Date: Sheet of



Custom


Alba UMA

FSB setting

MCH_CLVREF ~= 0.35V

SDVO/iHDMI/DP interface disabled

SDVO/iHDMI/DP interface enabled

DDPC_CTRLDATA

TLS cipher suite with confidentiality

CFG 16 FSB dynamic ODT disable

CFG Strap HighLowDMI X 2

CFG 9 PCIE GFX lane reversed

CFG 19DMI Lane Reserved

DMI X 4

Normal operation Reverse DMI lanes

ITPM enable

Only PCIE or SDVO is operational

ITPM disable

CFG 20SDVO concurrent with PCIE

PCIE and SDVO areoperatiing simultaneously via the PEG port

SDVO_CTRLDATA

CFG 5CFG 6

SDVO interface disable

CFG 7TLS cipher suite with no confidentiality

FSB Dynamic ODT enable

CFG 10 PCIE loopback enable PCIE loopback disableCFG 12 ALLZ mode enable ALLZ mode disableCFG 13 XOR mode enable XOR mode disable

PCIE GFX lanenumbered in oder

SDVO interface enableL_DDC_DATA LFP disable LFP card present

SSID = MCH

* is current setting

***

*

****

*

*

***

For UMA

A00-0402

TP1104TP1104

TP1103TP1103




1

2

R1116499R2F-2-GPR1116499R2F-2-GP

1

2



1

2

R1129Do Not StuffDYR1129Do Not StuffDY

1

2

R11093K01R2F-3-GPR11093K01R2F-3-GP


1 2R1117

10KR2J-3-GP

R1117

10KR2J-3-GP

1

2


TP1105TP1105

1 2R1101

100R2J-2-GP

R1101

100R2J-2-GP

1

2

C

1

1

0

6

S

C

D

1

U

1

0

V

2

K

X

-

4

G

P

C

1

1

0

6

S

C

D

1

U

1

0

V

2

K

X

-

4

G

P

1 2R1106 Do Not StuffDYR1106 Do Not StuffDY1 2R1102 Do Not StuffDYR1102 Do Not StuffDY



1

2



1

2




1 2

R1139Do Not Stuff

R1139Do Not Stuff


1

2

C1104SC2D2U10V3KX-1GP


1

2


1 2R1107 Do Not StuffDYR1107 Do Not StuffDY TP1101TP1101

1 TP1106TP1106

1

2

R112680D6R2F-L-GP

R112680D6R2F-L-GP

C

B

E

Q1101Do Not StuffDY Q1101Do Not StuffDY

1

2

C

1

1

4

4

D

o

N

o

t

S

t

u

f

f

DY

C

1

1

4

4

D

o

N

o

t

S

t

u

f

f

DY

1

2

R112156R2J-4-GPR112156R2J-4-GP


SA_CK_0 AP24SA_CK_1 AT21SB_CK_0 AV24

SA_CK#_0 AR24SA_CK#_1 AR21SB_CK#_0 AU24

SA_CKE_0 BC28SA_CKE_1 AY28SB_CKE_0 AY36SB_CKE_1 BB36

SA_CS#_0 BA17SA_CS#_1 AY16SB_CS#_0 AV16SB_CS#_1 AR13

SM_DRAMRST# BC36

SA_ODT_0 BD17SA_ODT_1 AY17SB_ODT_0 BF15SB_ODT_1 AY13

SM_RCOMP BG22SM_RCOMP# BH21

CFG_18P29CFG_19R28

CFG_2P25CFG_0T25CFG_1R25

CFG_20T28

CFG_3P20CFG_4P24CFG_5C25CFG_6N24CFG_7M24CFG_8E21CFG_9C23CFG_10C24CFG_11N21CFG_12P21CFG_13T21CFG_14R20CFG_15M20CFG_16L21CFG_17H21

PM_SYNC#R29

PM_EXT_TS#_0N33PM_EXT_TS#_1P32PWROKAT40RSTIN#AT11

DPLL_REF_CLK B38DPLL_REF_CLK# A38

DPLL_REF_SSCLK E41DPLL_REF_SSCLK# F41

DMI_RXN_0 AE41DMI_RXN_1 AE37DMI_RXN_2 AE47DMI_RXN_3 AH39

DMI_RXP_0 AE40DMI_RXP_1 AE38DMI_RXP_2 AE48DMI_RXP_3 AH40

DMI_TXN_0 AE35DMI_TXN_1 AE43DMI_TXN_2 AE46DMI_TXN_3 AH42

DMI_TXP_0 AD35DMI_TXP_1 AE44DMI_TXP_2 AF46DMI_TXP_3 AH43

RESERVED#AL34AL34

RESERVED#AN35AN35RESERVED#AK34AK34

RESERVED#AM35AM35

RESERVED#BG23BG23RESERVED#BF23BF23RESERVED#BH18BH18RESERVED#BF18BF18

PM_DPRSTP#B7

SB_CK_1 AU20

SB_CK#_1 AV20

RESERVED#AY21AY21

RESERVED#AH9AH9RESERVED#AH10AH10RESERVED#AH12AH12RESERVED#AH13AH13

RESERVED#M36M36RESERVED#N36N36RESERVED#R33R33RESERVED#T33T33

GFX_VID_0 B33GFX_VID_1 B32GFX_VID_2 G33GFX_VID_3 F33

GFX_VR_EN C34

SM_RCOMP_VOH BF28SM_RCOMP_VOL BH28

THERMTRIP#T20DPRSLPVRR32

RESERVED#K12K12

CL_CLK AH37CL_DATA AH36

CL_PWROK AN36CL_RST# AJ35CL_VREF AH34

NC#A47A47

NC#BG48BG48NC#BF48BF48NC#BD48BD48NC#BC48BC48NC#BH47BH47NC#BG47BG47NC#BE47BE47NC#BH46BH46NC#BF46BF46NC#BG45BG45NC#BH44BH44NC#BH43BH43NC#BH6BH6NC#BH5BH5NC#BG4BG4

SDVO_CTRLCLK G36SDVO_CTRLDATA E36

CLKREQ# K36

RESERVED#T24T24

ICH_SYNC# H36

TSATN# B12

PEG_CLK# E43PEG_CLK F43

NC#BH3BH3

GFX_VID_4 E33

RESERVED#B31B31

DDPC_CTRLCLK N28

NC#BF3BF3NC#BH2BH2NC#BG2BG2NC#BE2BE2NC#BG1BG1NC#BF1BF1NC#BD1BD1NC#BC1BC1NC#F1F1

SM_VREF AV42SM_PWROK AR36

SM_REXT BF17

RESERVED#M1M1

HDA_BCLK B28HDA_RST# B30

HDA_SDI B29HDA_SDO C29

HDA_SYNC A28

DDPC_CTRLDATA M28

RESERVED#B2B2

PM

M

I

S

C

NC

D

D

R

C

L

K

/

C

O

N

T

R

O

L

/

C

O

M

P

E

N

S

A

T

I

O

N

C

L

K

D

M

I

CFG

RSVD

G

R

A

P

H

I

C

S

V

I

D

M

E

H

D

A

2 OF 10U1001B

CANTIGA-GM-GP-U-NF

PM

M

I

S

C

NC

D

D

R

C

L

K

/

C

O

N

T

R

O

L

/

C

O

M

P

E

N

S

A

T

I

O

N

C

L

K

D

M

I

CFG

RSVD

G

R

A

P

H

I

C

S

V

I

D

M

E

H

D

A

2 OF 10U1001B

CANTIGA-GM-GP-U-NF

TP1102TP1102

1

2

R1122Do Not StuffDY R1122Do Not StuffDY

1

2

C

1

1

4

3

D

o

N

o

t

S

t

u

f

f

DY

C

1

1

4

3

D

o

N

o

t

S

t

u

f

f

DY

1

2

R112580D6R2F-L-GP

R112580D6R2F-L-GP

1 2R1118

0R2J-2-GP

R1118

0R2J-2-GP

1

2



123

4RN1101

SRN10KJ-5-GP

RN1101

SRN10KJ-5-GP

1 2R1123499R2F-2-GPR1123499R2F-2-GP

1

2

C1101Do Not Stuff DYC1101Do Not Stuff DY

1

2

R1119Do Not Stuff

DYR1119Do Not Stuff

DY

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

M_A_DQS#3

M_A_DQS#0

M_A_DQS#6

M_A_DQS#4

M_A_DQS#1M_A_DQS#2

M_A_DQS#5

M_A_DQS#7

M_A_A0

M_A_A6

M_A_A3

M_A_A5

M_A_A7

M_A_A1M_A_A2

M_A_A4

M_A_A10

M_A_A8

M_A_A13

M_A_A11

M_A_A9

M_A_A12

M_A_DQS#[7..0]

M_A_A[14..0]

M_A_DM[7..0]M_A_DM0M_A_DM1M_A_DM2M_A_DM3M_A_DM4M_A_DM5M_A_DM6M_A_DM7

M_A_DQS[7..0]

M_A_DQS5

M_A_DQS7

M_A_DQS2M_A_DQS3M_A_DQS4

M_A_DQS0M_A_DQS1

M_A_DQS6

M_B_DQ0M_B_DQ1M_B_DQ2M_B_DQ3M_B_DQ4M_B_DQ5M_B_DQ6M_B_DQ7M_B_DQ8M_B_DQ9M_B_DQ10M_B_DQ11

M_B_DQ15

M_B_DQ13M_B_DQ12

M_B_DQ14

M_B_DQ16M_B_DQ17M_B_DQ18M_B_DQ19

M_B_DQ23

M_B_DQ21M_B_DQ20

M_B_DQ22

M_B_DQ28

M_B_DQ26

M_B_DQ29

M_B_DQ25

M_B_DQ31

M_B_DQ24

M_B_DQ27

M_B_DQ30


M_B_DQ39

M_B_DQ37M_B_DQ36

M_B_DQ38

M_B_DQ44

M_B_DQ42

M_B_DQ45

M_B_DQ41

M_B_DQ47

M_B_DQ40

M_B_DQ43

M_B_DQ46


M_B_DQ55

M_B_DQ53M_B_DQ52

M_B_DQ54

M_B_DQ60

M_B_DQ58

M_B_DQ61

M_B_DQ57

M_B_DQ63

M_B_DQ56

M_B_DQ59

M_B_DQ62

M_B_DQ[63..0]

M_A_DQ44

M_A_DQ36

M_A_DQ47

M_A_DQ40M_A_DQ39

M_A_DQ37

M_A_DQ35M_A_DQ34

M_A_DQ59

M_A_DQ54M_A_DQ53

M_A_DQ63

M_A_DQ60M_A_DQ61

M_A_DQ58

M_A_DQ51

M_A_DQ48

M_A_DQ57

M_A_DQ55

M_A_DQ49M_A_DQ50

M_A_DQ62

M_A_DQ52

M_A_DQ56

M_A_DQ[63..0]M_A_DQ0M_A_DQ1M_A_DQ2M_A_DQ3

M_A_DQ7

M_A_DQ5M_A_DQ4

M_A_DQ6

M_A_DQ12

M_A_DQ10

M_A_DQ13

M_A_DQ9M_A_DQ8

M_A_DQ11

M_A_DQ15M_A_DQ14

M_A_DQ27

M_A_DQ25

M_A_DQ20M_A_DQ19

M_A_DQ30

M_A_DQ18

M_A_DQ16

M_A_DQ28

M_A_DQ17

M_A_DQ26

M_A_DQ31

M_A_DQ29

M_A_DQ22M_A_DQ23M_A_DQ24

M_A_DQ21

M_A_DQ46

M_A_DQ42

M_A_DQ38

M_A_DQ32

M_A_DQ45

M_A_DQ33

M_A_DQ43

M_A_DQ41

M_B_DQS#[7..0]M_B_DQS#0M_B_DQS#1M_B_DQS#2M_B_DQS#3M_B_DQS#4M_B_DQS#5M_B_DQS#6M_B_DQS#7

M_B_DQS[7..0]M_B_DQS0M_B_DQS1M_B_DQS2M_B_DQS3M_B_DQS4M_B_DQS5M_B_DQS6M_B_DQS7

M_B_A12

M_B_A9

M_B_A11

M_B_A13

M_B_A8

M_B_A10

M_B_A[14..0]M_B_A0M_B_A1M_B_A2M_B_A3M_B_A4M_B_A5M_B_A6M_B_A7

M_B_DM[7..0]M_B_DM0M_B_DM1M_B_DM2M_B_DM3M_B_DM4M_B_DM5M_B_DM6M_B_DM7

M_A_A14M_B_A14

M_A_DQS#[7..0] 16

M_A_DQS[7..0] 16

M_A_A[14..0] 16

M_A_DM[7..0] 16

M_B_BS#0 17M_B_BS#1 17M_B_BS#2 17

M_B_CAS# 17M_B_RAS# 17

M_A_BS#0 16M_A_BS#1 16M_A_BS#2 16

M_A_CAS# 16

M_B_DQ[63..0]17

M_A_RAS# 16

M_A_DQ[63..0]16

M_B_DQS#[7..0] 17

M_B_DQS[7..0] 17

M_B_A[14..0] 17

M_B_DM[7..0] 17

M_A_WE# 16M_B_WE# 17

Title


Date: Sheet of


Alba UMA -1Cantiga-DDR(3/6)

Custom


Alba UMA

Title


Date: Sheet of



Custom


Alba UMA

Title


Date: Sheet of



Custom


Alba UMA

SSID = MCH

SB_DQ_0AK47SB_DQ_1AH46

SB_DQ_10BA48SB_DQ_11AY48SB_DQ_12AT47SB_DQ_13AR47SB_DQ_14BA47SB_DQ_15BC47SB_DQ_16BC46SB_DQ_17BC44SB_DQ_18BG43SB_DQ_19BF43

SB_DQ_2AP47

SB_DQ_20BE45SB_DQ_21BC41SB_DQ_22BF40SB_DQ_23BF41SB_DQ_24BG38SB_DQ_25BF38SB_DQ_26BH35SB_DQ_27BG35SB_DQ_28BH40SB_DQ_29BG39

SB_DQ_3AP46

SB_DQ_30BG34SB_DQ_31BH34SB_DQ_32BH14SB_DQ_33BG12SB_DQ_34BH11SB_DQ_35BG8SB_DQ_36BH12SB_DQ_37BF11SB_DQ_38BF8SB_DQ_39BG7

SB_DQ_4AJ46

SB_DQ_40BC5SB_DQ_41BC6SB_DQ_42AY3SB_DQ_43AY1SB_DQ_44BF6SB_DQ_45BF5SB_DQ_46BA1SB_DQ_47BD3SB_DQ_48AV2SB_DQ_49AU3

SB_DQ_5AJ48

SB_DQ_50AR3SB_DQ_51AN2SB_DQ_52AY2SB_DQ_53AV1SB_DQ_54AP3SB_DQ_55AR1SB_DQ_56AL1SB_DQ_57AL2SB_DQ_58AJ1SB_DQ_59AH1

SB_DQ_6AM48

SB_DQ_60AM2SB_DQ_61AM3SB_DQ_62AH3SB_DQ_63AJ3

SB_DQ_7AP48SB_DQ_8AU47SB_DQ_9AU46

SB_BS_0 BC16SB_BS_1 BB17SB_BS_2 BB33

SB_CAS# BG16

SB_DM_0 AM47SB_DM_1 AY47SB_DM_2 BD40SB_DM_3 BF35SB_DM_4 BG11SB_DM_5 BA3SB_DM_6 AP1SB_DM_7 AK2

SB_DQS_0 AL47SB_DQS_1 AV48SB_DQS_2 BG41SB_DQS_3 BG37SB_DQS_4 BH9SB_DQS_5 BB2SB_DQS_6 AU1SB_DQS_7 AN6

SB_DQS#_0 AL46SB_DQS#_1 AV47SB_DQS#_2 BH41SB_DQS#_3 BH37SB_DQS#_4 BG9SB_DQS#_5 BC2SB_DQS#_6 AT2SB_DQS#_7 AN5

SB_MA_0 AV17SB_MA_1 BA25

SB_MA_10 BB16SB_MA_11 AW33SB_MA_12 AY33SB_MA_13 BH15

SB_MA_2 BC25SB_MA_3 AU25SB_MA_4 AW25SB_MA_5 BB28SB_MA_6 AU28SB_MA_7 AW28SB_MA_8 AT33SB_MA_9 BD33

SB_MA_14 AU33

SB_RAS# AU17

SB_WE# BF14

D

D

R

S

Y

S

T

E

M

M

E

M

O

R

Y

B

5 OF 10U1001E

CANTIGA-GM-GP-U-NF

D

D

R

S

Y

S

T

E

M

M

E

M

O

R

Y

B

5 OF 10U1001E

CANTIGA-GM-GP-U-NF

SA_DQ_0AJ38SA_DQ_1AJ41

SA_DQ_10AU40SA_DQ_11AT38SA_DQ_12AN41SA_DQ_13AN39SA_DQ_14AU44SA_DQ_15AU42SA_DQ_16AV39SA_DQ_17AY44SA_DQ_18BA40SA_DQ_19BD43

SA_DQ_2AN38

SA_DQ_20AV41SA_DQ_21AY43SA_DQ_22BB41SA_DQ_23BC40SA_DQ_24AY37SA_DQ_25BD38SA_DQ_26AV37SA_DQ_27AT36SA_DQ_28AY38SA_DQ_29BB38

SA_DQ_3AM38

SA_DQ_30AV36SA_DQ_31AW36SA_DQ_32BD13SA_DQ_33AU11SA_DQ_34BC11SA_DQ_35BA12SA_DQ_36AU13SA_DQ_37AV13SA_DQ_38BD12SA_DQ_39BC12

SA_DQ_4AJ36

SA_DQ_40BB9SA_DQ_41BA9SA_DQ_42AU10SA_DQ_43AV9SA_DQ_44BA11SA_DQ_45BD9SA_DQ_46AY8SA_DQ_47BA6SA_DQ_48AV5SA_DQ_49AV7

SA_DQ_5AJ40

SA_DQ_50AT9SA_DQ_51AN8SA_DQ_52AU5SA_DQ_53AU6SA_DQ_54AT5SA_DQ_55AN10SA_DQ_56AM11SA_DQ_57AM5SA_DQ_58AJ9SA_DQ_59AJ8

SA_DQ_6AM44

SA_DQ_60AN12SA_DQ_61AM13SA_DQ_62AJ11SA_DQ_63AJ12

SA_DQ_7AM42SA_DQ_8AN43SA_DQ_9AN44

SA_BS_0 BD21SA_BS_1 BG18SA_BS_2 AT25

SA_CAS# BD20

SA_DM_0 AM37SA_DM_1 AT41SA_DM_2 AY41SA_DM_3 AU39SA_DM_4 BB12SA_DM_5 AY6SA_DM_6 AT7

SA_DQS_0 AJ44SA_DQS_1 AT44SA_DQS_2 BA43SA_DQS_3 BC37SA_DQS_4 AW12SA_DQS_5 BC8SA_DQS_6 AU8SA_DQS_7 AM7

SA_DM_7 AJ5

SA_DQS#_0 AJ43SA_DQS#_1 AT43SA_DQS#_2 BA44SA_DQS#_3 BD37SA_DQS#_4 AY12SA_DQS#_5 BD8SA_DQS#_6 AU9SA_DQS#_7 AM8

SA_MA_0 BA21SA_MA_1 BC24

SA_MA_10 BC21SA_MA_11 BG26SA_MA_12 BH26SA_MA_13 BH17

SA_MA_2 BG24SA_MA_3 BH24SA_MA_4 BG25SA_MA_5 BA24SA_MA_6 BD24SA_MA_7 BG27SA_MA_8 BF25SA_MA_9 AW24

SA_RAS# BB20

SA_WE# AY20

SA_MA_14 AY25

D

D

R

S

Y

S

T

E

M

M

E

M

O

R

Y

A

4 OF 10U1001D

CANTIGA-GM-GP-U-NF

D

D

R

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S

T

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M

M

E

M

O

R

Y

A

4 OF 10U1001D

CANTIGA-GM-GP-U-NF

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

GMCH_GND4

GMCH_GND1GMCH_GND2GMCH_GND3

PEG_CMP

LIBGLVDS_VBG

LDDC_CLKLDDC_DATA

M_BLUE

M_GREEN

M_RED

TV_DACC

TV_DACATV_DACB

GMCH_DDCDATAGMCH_DDCCLK

GMCH_HS

GMCH_VS

CRT_IREF

GMCH_DDCDATA

GMCH_DDCCLKDDC_CLK_CON

DDC_DATA_CON

L_CTRL_CLKL_CTRL_DATA+3.3V_RUN

+3.3V_RUN

+3.3V_RUN

+3.3V_RUN

+1.05V_VCCP

LCDVDD_EN41

LDDC_DATA41

LBKLT_CTL41

LDDC_CLK41

GMCH_BL_ON26

VGA_TXAOUT0-41

VGA_TXAOUT1+41

VGA_TXAOUT2-41

VGA_TXAOUT0+41

VGA_TXAOUT1-41

VGA_TXAOUT2+41

VGA_TXACLK+41VGA_TXACLK-41

VGA_TXBOUT0-41

VGA_TXBCLK-41

VGA_TXBOUT1+41VGA_TXBOUT0+41

VGA_TXBOUT2-41

VGA_TXBCLK+41

VGA_TXBOUT1-41

VGA_TXBOUT2+41

M_BLUE42

M_RED42

M_GREEN42

GMCH_VSYNC42

GMCH_HSYNC42

DDC_CLK_CON46

DDC_DATA_CON 46

Title


Date: Sheet of


Alba UMA -1Cantiga-GND/LVDS/VGA(6/6)

C


Alba UMA

Title


Date: Sheet of



C


Alba UMA

Title


Date: Sheet of



C


Alba UMA

NCTFPIN

Place R1301close toMCH within500 mils.

SSID = MCH

NCTFPIN

UMA-SA

CRT_IREFrouting Tracewidth use 20 mil.

5V @ ext. CRT side

1 2R1305 75R2F-2-GPR1305 75R2F-2-GP

1 2R1303 2K4R2F-GPR1303 2K4R2F-GP

1 2R1308 150R2F-1-GPR1308 150R2F-1-GP

1 2R1312 33R2J-2-GPR1312 33R2J-2-GP

PEG_COMPI T37PEG_COMPO T36

PEG_RX#_0 H44PEG_RX#_1 J46PEG_RX#_2 L44PEG_RX#_3 L40PEG_RX#_4 N41PEG_RX#_5 P48PEG_RX#_6 N44PEG_RX#_7 T43PEG_RX#_8 U43PEG_RX#_9 Y43

PEG_RX#_10 Y48PEG_RX#_11 Y36PEG_RX#_12 AA43PEG_RX#_13 AD37PEG_RX#_14 AC47PEG_RX#_15 AD39

PEG_RX_0 H43PEG_RX_1 J44PEG_RX_2 L43PEG_RX_3 L41PEG_RX_4 N40PEG_RX_5 P47PEG_RX_6 N43PEG_RX_7 T42PEG_RX_8 U42PEG_RX_9 Y42

PEG_RX_10 W47PEG_RX_11 Y37PEG_RX_12 AA42PEG_RX_13 AD36PEG_RX_14 AC48PEG_RX_15 AD40

PEG_TX#_0 J41

PEG_TX#_10 Y40

PEG_TX#_3 M40PEG_TX#_4 M42PEG_TX#_5 R48PEG_TX#_6 N38PEG_TX#_7 T40PEG_TX#_8 U37PEG_TX#_9 U40

PEG_TX#_1 M46

PEG_TX#_11 AA46PEG_TX#_12 AA37PEG_TX#_13 AA40PEG_TX#_14 AD43PEG_TX#_15 AC46

PEG_TX#_2 M47

PEG_TX_0 J42PEG_TX_1 L46PEG_TX_2 M48PEG_TX_3 M39PEG_TX_4 M43PEG_TX_5 R47PEG_TX_6 N37PEG_TX_7 T39PEG_TX_8 U36PEG_TX_9 U39

PEG_TX_10 Y39PEG_TX_11 Y46PEG_TX_12 AA36PEG_TX_13 AA39PEG_TX_14 AD42PEG_TX_15 AD46

L_CTRL_CLKM32

L_CTRL_DATAM33L_DDC_CLKK33L_DDC_DATAJ33

L_VDD_ENM29LVDS_IBGC44LVDS_VBGB43LVDS_VREFHE37LVDS_VREFLE38LVDSA_CLK#C41LVDSA_CLKC40

LVDSA_DATA#_0H47LVDSA_DATA#_1E46LVDSA_DATA#_2G40

LVDSA_DATA_1D45LVDSA_DATA_2F40

LVDSB_CLK#B37LVDSB_CLKA37

LVDSB_DATA#_0A41LVDSB_DATA#_1H38LVDSB_DATA#_2G37

LVDSB_DATA_1G38LVDSB_DATA_2F37

L_BKLT_ENG32

TVA_DACF25TVB_DACH25TVC_DACK25

TV_RTNH24

CRT_BLUEE28

CRT_DDC_CLKH32CRT_DDC_DATAJ32

CRT_GREENG28

CRT_HSYNCJ29CRT_TVO_IREFE29

CRT_REDJ28

CRT_IRTNG29

CRT_VSYNCL29

LVDSA_DATA_0H48

LVDSB_DATA_0B42

L_BKLT_CTRLL32

TV_DCONSEL_0C31TV_DCONSEL_1E32

LVDSA_DATA#_3A40

LVDSA_DATA_3B40

LVDSB_DATA#_3J37

LVDSB_DATA_3K37

LVDS

P

C

I

-

E

X

P

R

E

S

S

G

R

A

P

H

I

C

S

TV

VGA

3 OF 10U1001C

CANTIGA-GM-GP-U-NF

LVDS

P

C

I

-

E

X

P

R

E

S

S

G

R

A

P

H

I

C

S

TV

VGA

3 OF 10U1001C

CANTIGA-GM-GP-U-NF

1

2

R130149D9R2F-GPR130149D9R2F-GP

1

2

34

5

6

Q1301

2N7002DW-7F-GP

Q1301

2N7002DW-7F-GP

1 2R1309 150R2F-1-GPR1309 150R2F-1-GP

TP1303TP1303TP1302TP1302

1TP225TP225

1 2R1306 75R2F-2-GPR1306 75R2F-2-GP

123

4RN1303

SRN10KJ-5-GP

RN1303

SRN10KJ-5-GP

TP1304TP1304TP1301TP1301

1 2R1311 1K02R2F-1-GPR1311 1K02R2F-1-GP

1 2R1307 150R2F-1-GPR1307 150R2F-1-GP

VSSAU48

VSS A23

VSSAR48VSSAL48VSSBB47VSSAW47VSSAN47VSSAJ47VSSAF47VSSAD47VSSAB47VSSY47VSST47VSSN47VSSL47VSSG47VSSBD46VSSBA46

VSSAV46VSSAR46VSSAM46VSSV46VSSR46VSSP46VSSH46VSSF46VSSBF44VSSAH44VSSAD44VSSAA44VSSY44VSSU44VSST44VSSM44VSSF44VSSBC43VSSAV43VSSAU43VSSAM43VSSJ43VSSC43VSSBG42VSSAY42VSSAT42VSSAN42VSSAJ42VSSAE42VSSN42VSSL42VSSBD41VSSAU41VSSAM41VSSAH41VSSAD41VSSAA41VSSY41VSSU41VSST41VSSM41VSSG41VSSB41VSSBG40VSSBB40VSSAV40VSSAN40VSSH40VSSE40VSSAT39VSSAM39VSSAJ39VSSAE39VSSN39VSSL39VSSB39VSSBH38VSSBC38VSSBA38VSSAU38VSSAH38VSSAD38VSSAA38VSSY38VSSU38VSST38VSSJ38VSSF38VSSC38

VSSBD36

VSS AM36VSS AE36VSS P36VSS L36VSS J36VSS F36VSS B36VSS AH35VSS AA35VSS Y35VSS U35VSS T35VSS BF34VSS AM34VSS AJ34VSS AF34VSS AE34VSS W34VSS B34VSS A34VSS BG33VSS BC33VSS BA33VSS AV33VSS AR33VSS AL33VSS AH33VSS AB33VSS P33VSS L33VSS H33VSS N32VSS K32VSS F32VSS C32VSS A31VSS AN29VSS T29VSS N29VSS K29VSS H29VSS F29VSS A29VSS BG28VSS BD28VSS BA28VSS AV28VSS AT28VSS AR28VSS AJ28VSS AG28VSS AE28VSS AB28VSS Y28VSS P28VSS K28VSS H28VSS F28VSS C28VSS BF26VSS AH26VSS AF26VSS AB26VSS AA26VSS C26VSS B26VSS BH25VSS BD25VSS BB25VSS AV25VSS AR25VSS AJ25VSS AC25VSS Y25VSS N25VSS L25VSS J25VSS G25VSS E25VSS BF24

VSSBF37VSSBB37VSSAW37VSSAT37VSSAN37VSSAJ37VSSH37VSSC37VSSBG36

VSSAU36

VSS AT24

VSS AH24

VSS AB24

VSS L24

VSSAY46

VSS G24

VSS E24

VSS AG23

VSS B23

VSS AY24

VSS AJ24

VSS AF24

VSS R24

VSS K24VSS J24

VSS F24

VSS BH23

VSS Y23VSSAK15

VSS AD12

VSS AJ6

VSS

9 OF 10U1001I

CANTIGA-GM-GP-U-NF

VSS

9 OF 10U1001I

CANTIGA-GM-GP-U-NF

12

3 4

RN1302SRN2K2J-1-GPRN1302SRN2K2J-1-GP

1 2R1310 33R2J-2-GPR1310 33R2J-2-GP

1 2R1304 75R2F-2-GPR1304 75R2F-2-GP

VSSBG21

VSSAW21VSSAU21VSSAP21VSSAN21VSSAH21VSSAF21VSSAB21VSSR21VSSM21VSSJ21VSSG21VSSBC20VSSBA20VSSAW20VSSAT20VSSAJ20VSSAG20VSSY20VSSN20VSSK20VSSF20VSSC20VSSA20VSSBG19VSSA18VSSBG17VSSBC17VSSAW17VSSAT17VSSR17VSSM17VSSH17VSSC17

VSSBA16

VSSAU16VSSAN16VSSN16VSSK16VSSG16VSSE16VSSBG15

VSSW15VSSA15VSSBG14VSSAA14VSSC14VSSBG13VSSBC13VSSBA13

VSSAN13VSSAJ13VSSAE13VSSN13VSSL13VSSG13VSSE13VSSBF12VSSAV12VSSAT12VSSAM12VSSAA12VSSJ12VSSA12VSSBD11VSSBB11VSSAY11VSSAN11VSSAH11

VSSY11VSSN11VSSG11VSSC11VSSBG10VSSAV10VSSAT10VSSAJ10VSSAE10VSSAA10

VSSBH8VSSB9VSSG9VSSAD9VSSAM9VSSAN9VSSBC9VSSM10VSSBF9

VSS AH8VSS Y8VSS L8VSS E8VSS B8VSS AY7VSS AU7VSS AN7VSS AJ7VSS AE7VSS AA7VSS N7VSS J7VSS BG6VSS BD6VSS AV6VSS AT6

VSSAC15

VSS AM6VSS M6VSS C6VSS BA5VSS AH5VSS AD5VSS Y5VSS L5VSS J5VSS H5VSS F5VSS BE4

VSS BC3VSS AV3VSS AL3

VSS_NCTF AF32VSS_NCTF AB32VSS_NCTF V32VSS_NCTF AJ30VSS_NCTF AM29VSS_NCTF AF29VSS_NCTF AB29VSS_NCTF U26VSS_NCTF U23VSS_NCTF AL20VSS_NCTF V20VSS_NCTF AC19VSS_NCTF AL17VSS_NCTF AJ17VSS_NCTF AA17VSS_NCTF U17

VSS_SCB BH48VSS_SCB BH1VSS_SCB A48VSS_SCB C1VSS_SCB A3

NC#E1 E1NC#D2 D2NC#C3 C3NC#B4 B4NC#A5 A5NC#A6 A6

NC#A43 A43NC#A44 A44NC#B45 B45NC#C46 C46NC#D47 D47NC#B47 B47NC#A46 A46NC#F48 F48NC#E48 E48NC#C48 C48NC#B48 B48

VSS R3VSS P3

VSS BA2

VSS AR2VSS AU2

VSS AP2

VSS F3

VSS AW2

VSS AE2VSS AF2VSS AH2VSS AJ2

VSS AD2VSS AC2VSS Y2VSS M2VSS K2VSS AM1VSS AA1VSS P1VSS H1

VSSBB8VSSAV8VSSAT8

VSS U24VSS U28VSS U25VSS U29

VSSL12

VSS

V

S

S

N

C

T

F

V

S

S

S

C

B

N

C

10 OF 10U1001J

CANTIGA-GM-GP-U-NF

VSS

V

S

S

N

C

T

F

V

S

S

S

C

B

N

C

10 OF 10U1001J

CANTIGA-GM-GP-U-NF

123

4

RN1301

SRN2K2J-1-GP

RN1301

SRN2K2J-1-GP

55

4

4

3

3

2

2

1

1

D D

C C

B B

A ASM_LF7_GMCHSM_LF6_GMCH

SM_LF3_GMCHSM_LF2_GMCHSM_LF1_GMCH

SM_LF5_GMCHSM_LF4_GMCH

VCC_AXG_SENSEVSS_AXG_SENSE

+1.05V_VCCP

+1.05V_VCCP

+1.8V_SUS

+1.05V_VCCP

+1.05V_VCCP

Title


Date: Sheet of


Alba UMA -1Cantiga-Power(4/6)

Custom


Alba UMA

Title


Date: Sheet of



Custom


Alba UMA

Title


Date: Sheet of



Custom


Alba UMA

8700mA

3060mA

3000mA

SSID = MCH

+1.05V_VCCP 50mAVCC_AXF+1.05V_VCCP

+1.05V_VCCP

+1.05V_VCCP+1.05V_VCCP+1.05V_VCCP

157.2mAVCCD_HPLL

VCCA_SM_CK 26mA

139.2mAVCCA_MPLLVCCA_HPLL 24mA

720mA+1.05V_VCCP+1.05V_VCCP

VCCA_SM

+1.05V_VCCP50mAVCCA_PEG_PLL

+1.8V_SUS+1.8V_SUS 124mA

Supply Signal Group 3060mAVCC+1.05V_VCCP

Imax

1782mAVCC_PEG852mAVTT

3000mAVCC_SM

456mAVCC_DMI

VCC_SM_CK

+1.05V_VCCP

+1.5V_RUN VCCD_TVDAC 35mA

+1.5V_RUN VCCA_PEG_BG 414uA

+1.05V_VCCP

+3.3V_RUN VCC_HV 105.3mA

321.35mAVCCD_PEG_PLL

For UMA

Close to (G)MCH

On the edge

For UMA

Coupling CAP

Coupling CAP For UMA

1

2

C

1

4

2

1

S

C

4

D

7

U

6

D

3

V

5

K

X

-

3

G

P

C

1

4

2

1

S

C

4

D

7

U

6

D

3

V

5

K

X

-

3

G

P

1

2

C

1

4

1

9

S

C

1

U

1

0

V

3

K

X

-

3

G

P

C

1

4

1

9

S

C

1

U

1

0

V

3

K

X

-

3

G

P

1

2

C

dell inspiron 1440 - wistron alba uma

Documents

coreoutputs v

sheet ofwistron corporation21f

taipei hsien

hsin tai wu

block diagramcustom2

vccpoutputsinputs pwr

ref pwr

sus pwr