delay in verilog

7/29/2019 Delay in Verilog

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Delays in Verilog

Delays in Verilog

Presented BY:Shashank MistrySubhash Pakki

Jitu Mistry


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Why delays and timing so

important ?

They allow a degree of realism to be incorporatedinto the modeling process.

The time taken for changes to propagate through amodule may lead to race conditions in other modules.

Some designs, such as high speed microprocessors,may have very tight timing requirements that must bemet.


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Types of Delays.

Depending on the design approach,

Gate-level ModelingDataflow ModelingBehavioral Modeling


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Gate level modelling

Propagation delay :through the gate, and the time taken for the output toactually change state, according to input.

Gate level modelling delay described below as:- Rise

Fall Min/Typ/Max values Turn-off


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The rise delay is associated with a gateoutput transition to a 1 from anothervalue(0,x,z).

Format: operation #( Rise_Val, fall_Val ) a1( out, i1,i2);

Ex: and #(1 , 0 ) a1(out ,i1,i2);//Rise=1, Fall=0, Turn-Off=0

Rise delay


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Fall delay

The fall delay is associated with a gate outputtransition to 0 from another state 1

Format: operation #( Rise_Val, fall_Val ) a1( out, i1,i2);

Ex:-> and #(0 , 1 ) a1(out ,i1,i2);// Rise=0 Fall=1 Turn-Off=0


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The turn-off delay is associated with a gate output transition tothe high impedance value(z) from another value(0,1,x).

If the value changes to x, the minimum of three delay isconsidered.

Rise Delay 0,x,z -> 1

Fall Delay 1,x,z -> 0

Turn-Off Delay 0,1,x -> z

Number Of Delays

Specified delays

1 Rise, fall and turn-off timesof equal length

2 Rise and fall times

3 Rise, fall and turn off

Turn-off delay


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For each type of delay, there are three values, min,typand max can be specified.Any one value can be chosen at the start of the

simulationBecause of IC fabrication process variations.

Ex:

And #( 2:3:4, 3:4:5, 4:5:6) a ( out, i1, i2 );

Min, typ or max values


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In Verilog delays can be introduced with#'num'as in the examples below, where # is a special

character to introduce delay, and 'num' is the numberof ticks simulator should delay current statementexecution.

#1 a = b // Delay by 1, i.e. execute after 1 tick unit

#'num'


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We can provide num value of different way byvariable or/and parameter

Parameter delata= 10;

#delta out = in1& in2

Note: # There is no way we could synthesize

delays, but of course we can add delay to particularsignals by adding buffers.

#'num'


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Dataflow Modelling

As dataflow modelling use the concept of signals orvalues

The delays are associated with the Net (e.g. a Wire)along which the value is transmitted

Delays values control the time between the change ina right hand side operand and when the new value isassigned to the left hand side.

a = b; means a b


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Dataflow Modelling

Since values can be assigned to a net in a number ofways, there are corresponding methods of specifyingthe appropriate delays.

1.Regular Assignment Delay2.Net Declaration Delay3.Implicit Continuous Assignment


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Regular Assignment Delay

To assign a delay in continuous assignment thedelay value is specified after the keyword assign.This is used to introduce a delay onto a net that

has already been declared.e.g. wire out;

assign #10 out = in1 & in2;


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Net Declaration Delay

The Delay to be attributed to a Net can beassociated when the Net is declared.e.g.

// net delayswire #10 out;assign out = in1 & in2;

// the same effect as the following, generally

preferablewire out;assign #10 out = in1 & in2;


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Implicit Continuous Assignment

Since a net can be implicitly assigned a value at itsdeclaration, it is possible to introduce a delay then,before that assignment takes place.

E.g.wire #10 out = in1 & in2;

// same as

wire out;assign #10 out = in1 & in2;


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DELAYS IN BEHAVIOURAL MODELLING

There are following method Delay-based timing control

Regular

Intra- assignmentZero delay


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REGULAR DELAY CONTROL

Regular delay control is used when a non zero delay is specified to the left of a proceduralassignment

This is sometimes also referred to as inter-assignment delay controlExample:#10 q = x+y;It simply waits for the appropriate number of

timesteps before executing the command.


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INTRA ASSIGNMENT DELAY

Instead of specifying delay control to the left oftha assignment, it is possible to assign a delayto the right of the assignment operator.

Example: q = #10 x+y;With this kind of delay ,the value of x+y isstored at the time that the assignment isexecuted, but this value is not assigned to q until

after the delay period.


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ZERO DELAY

Zero delay is a method to ensure that astatement is executed last,after all otherstatements in that simulation time are

execcuted.This is to to elminate race arround conditions.However if there are multiple zero delaystatements,the order between them is

nondeterministic.EX:#0 x=1


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SEQENTIAL BLOCKS

The keywords begin and end are used to groupstatements into seqential blocks.A statement is executed only after its

preceeding statement completes execution.


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PARALLEL BLOCKS

Parallel blocks, specified by keywords fork andjoin,provide intresting simulation features.Statements in a parallel block are executed

concurrently.Ordering of statements is controlled by delay orevent control assigned to each statement.


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Setup and Holdtime

Very important in sequential logic.

$setup(data_line, clk_line, limit);

$hold(clk_line, data_line, limit);


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Thank you

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delay in verilog

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