data sheet sc1810 - socionext...socionext europe gmbh iii sc1810 graphic competence center - gcc...

Data Sheet

SC1810

Rev1.10 | November 12, 2018Socionext Europe GmbH

Graphic Competence Center – GCC

Socionext Europe GmbH SC1810Graphic Competence Center - GCC GCC-0196-Eds-sc1810-rev1.10 Copyright 2018https://www.eu.socionext.com/

Socionext Europe GmbH ii SC1810Graphic Competence Center - GCC Data Sheetds-sc1810-rev1.10 Prefacehttps://www.eu.socionext.com/ Rev1.10 | November 12, 2018

Preface

Intention and Target Audience of this Document

This document describes and gives you detailed insight to the stated Socionext Europe GmbH product.The SC1810 devices belong to the SoC Family used for graphics applications.

The target audience of this document are engineers developing products that use the SC1810 devices.

Trademarks

ARM is a registered trademark of ARM Limited in UK, USA and Taiwan. ARM is a trademark of ARM Limited in Japan and Korea. ARM Powered logo is a registered trademark of ARM Limited in Japan, UK, USA, and Taiwan.

ARM Powered logo is a trademark of ARM Limited in Korea. PowerVR is a trademark of Imagination Technologies.OpenGL ES is a registered trademark of the Khronos Group.

System names and product names which appear in this document are the trademarks of the respective company ororganization.

Licenses

Under the conditions of Philips corporation I2C patent, the license is valid where the device is used in an I2C systemwhich conforms to the I2C standard specification by Philips Corporation.The purchase of Socionext I2C components conveys a license under the Philips I2C Patent Rights to use thesecomponents in an I2C system, provided that the system conforms to the I2C Standard Specification as defined byPhilips.

Please acquire the license of MediaLB from SMSC and request the following document: OS62420 MediaLB DeviceInterface Macro Advanced Product Data Sheet.

Contact Information

For more information on Socionext products or sales inquiries please contact our support team and sales associatesthrough our website www.eu.socionext.com.

Socionext Europe GmbH iii SC1810Graphic Competence Center - GCC Data Sheetds-sc1810-rev1.10 Historyhttps://www.eu.socionext.com/ Rev1.10 | November 12, 2018

History

Revision Date Description1.00 05.09.2018 First release online. Synced with HM Rev. 1.61.

1.10 12.11.2018

1. Overview: updated Table 1.1, “SC1810 Series Information”.3. Ball Assignment and Pinning: updated “3.2.1. System”.4. Electrical Characteristics: updated Table 4.14, “Recommended operating con-ditions”, added “4.5.8. USB I/O”.

Table of Contents

1. Overview .......................................................................................................................................... 1-11.1. Series Information ..................................................................................................................... 1-11.2. Features .................................................................................................................................... 1-11.3. Block Diagrams ......................................................................................................................... 1-5

1.3.1. Overview block diagram of the SC1810 ........................................................................... 1-51.4. About Device Handling ............................................................................................................. 1-6

1.4.1. Latch-up ............................................................................................................................ 1-61.4.2. Unused Pins ..................................................................................................................... 1-61.4.3. Power Supply Pins ............................................................................................................ 1-61.4.4. Oscillation Circuit .............................................................................................................. 1-61.4.5. Warning about PLL Clock Operation ................................................................................ 1-6

2. Package Dimensions ...................................................................................................................... 2-12.1. Package Dimensions ................................................................................................................ 2-12.2. Package Markings .................................................................................................................... 2-22.3. Recommended PCB Land Design ............................................................................................ 2-3

3. Ball Assignment and Pinning ........................................................................................................ 3-13.1. Ball Assignment (Top View) ...................................................................................................... 3-13.2. Pin Descriptions for each Interface ........................................................................................... 3-2

3.2.1. System .............................................................................................................................. 3-23.2.2. Power Supply .................................................................................................................... 3-23.2.3. ICE .................................................................................................................................... 3-33.2.4. USB HOST/FUNC Controller ............................................................................................ 3-33.2.5. I2C BUS Interface 0 .......................................................................................................... 3-33.2.6. I2C BUS Interface 1 .......................................................................................................... 3-33.2.7. Analog Digital Converter (ADC) ........................................................................................ 3-33.2.8. Temperature Sensor ......................................................................................................... 3-43.2.9. DDR Controller 0 .............................................................................................................. 3-43.2.10. DDR Controller 1 ............................................................................................................ 3-43.2.11. Ethernet Link Controller .................................................................................................. 3-53.2.12. SD Input/Output (SDIO) .................................................................................................. 3-53.2.13. FPD Link ......................................................................................................................... 3-63.2.14. MIPI CSI-2 ...................................................................................................................... 3-63.2.15. Display Clock .................................................................................................................. 3-73.2.16. Display 1 (RGB) .............................................................................................................. 3-73.2.17. Display 2 (RGB) .............................................................................................................. 3-73.2.18. SEERISTM-MCR 0 (YUV) .............................................................................................. 3-73.2.19. Display Controller 1 (YUV) .............................................................................................. 3-83.2.20. SEERISTM-MCR 2 (YUV) .............................................................................................. 3-83.2.21. TCON .............................................................................................................................. 3-83.2.22. Video Capture Unit (CAP) ............................................................................................... 3-83.2.23. External Interrupt Controller (EXIRC) ............................................................................. 3-93.2.24. SPI Interface ................................................................................................................... 3-93.2.25. Controller Area Network 0 (CAN) ................................................................................... 3-93.2.26. Controller Area Network 1 (CAN) ................................................................................... 3-93.2.27. Media LB ......................................................................................................................... 3-93.2.28. Audio Interface 0 (I2S) .................................................................................................. 3-103.2.29. Audio Interface 1 (I2S) .................................................................................................. 3-103.2.30. Audio Interface 2 (I2S) .................................................................................................. 3-103.2.31. Pulse Width Modulator (PWM) ..................................................................................... 3-103.2.32. UART/USART 0 ............................................................................................................ 3-103.2.33. UART/USART 1 ............................................................................................................ 3-113.2.34. UART/USART 2 ............................................................................................................ 3-11

Socionext Europe GmbH iv SC1810Graphic Competence Center - GCC Data Sheetds-sc1810-rev1.10 Table of Contentshttps://www.eu.socionext.com/ Rev1.10 | November 12, 2018

3.2.35. UART/USART 3 ............................................................................................................ 3-113.2.36. UART/USART 4 ............................................................................................................ 3-113.2.37. UART/USART 5 ............................................................................................................ 3-113.2.38. External DMA Interface (XDMAC) ................................................................................ 3-123.2.39. HOST Interface ............................................................................................................. 3-123.2.40. GPIO ............................................................................................................................. 3-123.2.41. High-speed Serial Parallel Interface 0 (HS-SPI) ........................................................... 3-123.2.42. High-speed Serial Parallel Interface 1 (HS-SPI) ........................................................... 3-123.2.43. External Bus Controller (EBC) ...................................................................................... 3-13

4. Electrical Characteristics ............................................................................................................... 4-14.1. Absolute Maximum Ratings ...................................................................................................... 4-14.2. Power Consumption .................................................................................................................. 4-24.3. Temperature Conditions ........................................................................................................... 4-24.4. Thermal Design ......................................................................................................................... 4-34.5. Recommended Operating Conditions ....................................................................................... 4-3

4.5.1. Standard CMOS I/O .......................................................................................................... 4-34.5.2. DDR I/O ............................................................................................................................ 4-44.5.3. SSCG/PLL ........................................................................................................................ 4-54.5.4. I2C I/O .............................................................................................................................. 4-54.5.5. FPD I/O ............................................................................................................................. 4-64.5.6. MIPI I/O ............................................................................................................................. 4-64.5.7. SD I/O ............................................................................................................................... 4-64.5.8. USB I/O ............................................................................................................................. 4-7

4.6. Power ON ................................................................................................................................. 4-74.6.1. Recommended Power ON/OFF Sequence ...................................................................... 4-74.6.2. Power ON Timing Chart .................................................................................................... 4-9

4.7. DC Characteristics .................................................................................................................. 4-104.7.1. Standard CMOS I/O ........................................................................................................ 4-104.7.2. DDR I/O .......................................................................................................................... 4-104.7.3. I2C I/O ............................................................................................................................ 4-11

4.7.3.1. I2C IO V-I Characteristic Chart ................................................................................ 4-124.7.4. FPD I/O ........................................................................................................................... 4-134.7.5. MIPI I/O ........................................................................................................................... 4-144.7.6. USB I/O ........................................................................................................................... 4-154.7.7. ADC I/O .......................................................................................................................... 4-16

4.7.7.1. Recommended Operating Conditions ..................................................................... 4-164.7.7.2. Electrical Characteristics ......................................................................................... 4-18

4.7.8. Temperature Sensor ....................................................................................................... 4-194.7.8.1. Recommended Operating Conditions ..................................................................... 4-194.7.8.2. Electrical Characteristics ......................................................................................... 4-19

4.8. AC Characteristics .................................................................................................................. 4-204.8.1. External Memory Bus Controller ..................................................................................... 4-204.8.2. DDR Controller ............................................................................................................... 4-244.8.3. Display Controller Unit .................................................................................................... 4-36

4.8.3.1. Clock........................................................................................................................ 4-364.8.3.2. Input Signal of Display Controller 1 (Only) .............................................................. 4-374.8.3.3. Output Signals ......................................................................................................... 4-384.8.3.4. TCON active Display Timing Interface .................................................................... 4-40

4.8.4. FPD Unit ......................................................................................................................... 4-424.8.4.1. Output Signal........................................................................................................... 4-42

4.8.5. Video Capture Unit ......................................................................................................... 4-434.8.5.1. Clock........................................................................................................................ 4-434.8.5.2. Input Signal.............................................................................................................. 4-43

4.8.6. MIPI D-PHY .................................................................................................................... 4-444.8.7. UART .............................................................................................................................. 4-47

Socionext Europe GmbH v SC1810Graphic Competence Center - GCC Data Sheetds-sc1810-rev1.10 Table of Contentshttps://www.eu.socionext.com/ Rev1.10 | November 12, 2018

4.8.8. USART ............................................................................................................................ 4-484.8.9. I2C Bus Interface ............................................................................................................ 4-504.8.10. HOST Interface ............................................................................................................. 4-534.8.11. USB HOST/FUNC Controller ........................................................................................ 4-544.8.12. High-Speed Serial Parallel Interface (HS-SPI) ............................................................. 4-554.8.13. SPI Interface (Ssp) ....................................................................................................... 4-574.8.14. Ethernet Controller ........................................................................................................ 4-59

4.8.14.1. RMII Interface ........................................................................................................ 4-594.8.14.2. GMII Interface........................................................................................................ 4-604.8.14.3. MII Interface........................................................................................................... 4-61

4.8.15. I2S ................................................................................................................................ 4-62

5. Appendix .......................................................................................................................................... 5-15.1. Verified External Memory List ................................................................................................... 5-1

Socionext Europe GmbH vi SC1810Graphic Competence Center - GCC Data Sheetds-sc1810-rev1.10 Table of Contentshttps://www.eu.socionext.com/ Rev1.10 | November 12, 2018

1. OverviewThe SC1810 System-on-Chip (SOC) series features state-of-the-art functions and performance for in-vehicle graphicdisplay applications such as digital clusters, central HMI and surround-view systems.

The SC1810 is a SOC solution for graphics applications which incorporates ARM Limited's CPU ARM Cortex A9(quad core), graphics engines and graphics display controllers. The SC1810’s LSI architecture includes manyperipheral I/O resources such as in-vehicle LAN in a single device, meaning that only one SC1810 is needed tocontrol a main graphics application system where normally at least two chips (CPU and GDC) would be required.This chapter describes the features, block diagram, and function of the SC1810.

1.1. Series Information

Table 1.1 shows the selectable difference points of the SC1810 series.

Note: This documentation describes the functionality of all the modules implemented in the SC1810 devices(regardless of their count or availability in the actual device implemented in your design).

1.2. Features

TechnologyCMOS 28nm

Power Supply VoltageIO: 3.3V, 1.8VCore: 0.9VDDR3: 1.5V / DDR3L: 1.35VFPD: 1.8VMIPI: 1.8V

Table 1.1. : SC1810 Series Information

Module SC1810AR3-154 SD supportSC1810AR3-134HD support

SC1810AR3-113Fully featured

SC1810AR3-103

CPU Dual Core Dual Core Quad Core Quad Core

Vision processor No DPA DPA + HWA DPA + HWA

Video Capture Unit 4 Channels (*) 4 Channels (*) 6 Channels 6 Channels

Display Controller 2 Channels (*) 2 Channels (*) 3 Channels 3 Channels

H.264 Encoder No No No Yes

(*) The following modules cannot be supported: Video Capture Unit 4-5, SEERIS-MCR2.Therefore, Display2 YUV output of Pimux #F model is not supported.

Socionext Europe GmbH 1 - 1 SC1810Graphic Competence Center - GCC Data Sheetds-sc1810-rev1.10 Overviewhttps://www.eu.socionext.com/ Rev1.10 | November 12, 2018

PackageFCBGA-102427mm x 27mm, 0.8mm Pitch

Memory InterfaceSDRAM Interfacex32-bit 2CH(independent) DDR3/3L memory interfaceDDR3-1866 /DDR3-1600/DDR3L-1600

System-on-Chip (SoC) Technical DetailsCentral processor coresARM Cortex A9, quad core 1 GHz32 KB instruction cache / 32 KB data cache, 1024 KB L2-cacheARM NEON™ SIMD EngineJTAG ICE interfaceJava acceleration (Jazelle technology)VFP instruction set (VFPv3)

Multi-layer AXI/AHB bus architectureExternal Bus InterfaceParallel NOR Flash (16bit)Parallel NAND Flash (8/16bit)

Vision Processing Unit (VPU)OpenVX engine

Motion-JPEG/H.264 Decoder (up to Full-HD 30fps) x 6H.264 Encoder (up to Full-HD 60fps ) x 2Graphics cores2D Graphics Engine: ‘Socionext SEERISTM-MBP’3D Graphics Engine: ’PowerVRTM-Series 8XE’OpenGL® ES 3.1

Display controller3 independent parallel display controllers:1x Graphic Display Controller (Display Controller 1)2x SEERISTM-MCR (SEERIS-MCR 0, SEERIS-MCR 2)

Gamma correction unit (color LUT)Dithering unit Display resolution up to Full-HDOutput formats/channels:Up to 2x single channel DRGB888/1x single and dual channel FPDUp to 3x YUV of progressive signals (ITU-R BT.656, ITU-R BT.601)

Support for Dual View display (Display Controller 1)Warping on-the-fly (SEERIS-MCR)


Video Capture6 independent channelsITU-R BT.656, SMPTE 293M-2003, SMPTE 296M-2001, SMPTE 274M-2005YCbCr 4:2:2 interlaced, YCbCr 4:2:2 progressiveRGB888 – 1 channelMIPI CSI2Virtual Channel support

Color conversionHistogram unit, Histogram Equalization

Peripherals and MoreADC - 1 x support (12bit 1MS/s, 4 input ports)SPI interfacequad support (HS-SPI) - 2 channelslegacy only (SSP) - 1 channel

Ethernet MAC10/100/1000 MbpsEthernet-AVB supportMII/RMII/GMII support

USB 2.0 host or function – 1 channelSDIO/MMC – 1 channeleMMC supportUHS-I support

UART – 6 channelsUSART – 6 channelsI2S – 3 channelsI2C – 2 channelsHost SPI interface – 1 channelPWM – 7 channelsGPIOTimer 16/32 bit - 2 channelsSignature Unit (signature and checksum calculation for display content, intended use: ASIL)Watchdog Timer x 2External Interrupt – 4 channelsDMAC – 16 channels x 3Power Management UnitTemperature Sensor

DebuggingJTAG


Automotive InterfacesCAN - 2 channelsMediaLB® 3-pin support

Software SupportBoard Support Package (BSP)Graphics Software Stack providing APIs forMultiple Capture and Display Units3D Graphics2D Pixel Graphics: SEERISTM functionality (incl. warping-on-the-fly)

ToolsSocionext Developer Suite for setup, debugging and application supportCGI Studio (2D & 3D)


1.3. Block Diagrams

1.3.1. Overview block diagram of the SC1810

Figure 1.1. : Overview block diagram of SC1810 Series

Connectivity

SC1810 SeriesMemory

SRAM128k

16chDMA

DDR3 1866; DDR3L 160016/32/64-bit

ARM® Neon

Main Processor

ARM®Cortex-A9

D-Cache 32kB

SEERIS® 2D Engine

ADC 12bit

Connectivity

SDIO/MMC

HS-SPISPI Master

USB 2.0

UART/USART

MediaLB

Watchdog

System

Timer

Pixel EngineSEERIS-MBP

Display EngineSEERIS-MCR

Fill, Copy, Blend, Rop2/3, Scale,

Rotate, FIR

1920x1080, 24Bitup to 8 layers

Warping, DitheringDualView, TCON, SigUnitDRGB888,YUV422

SocionextVision

Processor Unit

Vision and 3D Graphics Processor

I-Cache 32kB

CAN

Ethernet-AVB

JTAG

PWR Mgmt

VideoH264

De-/EncoderPowerVR S8XE 3D Shading Engine

OpenGL ES 3.1

ARM® Neon

ARM®Cortex-A9

ARM® Neon

ARM®Cortex-A9

ARM® Neon

ARM®Cortex-A9

L2-Cache 1024kB

Motion JPEGDecoder

D-Cache 32kBI-Cache 32kB



MIPI-CSI2, DRGB888, YCbCr,

ITU-R BT.656, SMPTE,

Capture

Capture

Capture Engine

Histogram

I2C I2SPWM

GPIO

DRGB888,YUV422

Capture

Capture

Capture

Capture

Display1 Engine1920x1080, 24Bit

up to 8 layers,External Synchronization

Dithering, DualView,TCON, SigUnit

DRGB888, YUV422,FPD-Link


1.4. About Device Handling

1.4.1. Latch-up

Applying a voltage higher than VDDE or lower than VSS to I/O pins of CMOS IC, or a voltage higher than the ratingsbetween VDDE and VSS may cause latch-up. The latch-up increases the supply current, resulting in thermaldestruction of elements. When handling the product, never exceed the maximum ratings.

VDDE: Power supply pin except core power (0.9V).

1.4.2. Unused Pins

If an input pin is not used, a pull-up or pull-down resistor should be connected, to avoid the permanent destruction ofthe device due to the latch-up, caused by high resistance.

1.4.3. Power Supply Pins

All power and ground pins should be connected to each power rail. Otherwise, the device will not work correctly, noteven in the guaranteed operating range.

1.4.4. Oscillation Circuit

Noise will effect the CLKX0 and CLKX1 external pins, leading to malfunction. Therefore, the oscillator and its bypasscapacitor should be placed near to the device's CLKX0/CLKX1 pins.The surroundings of these pins require carefullygrounding.

1.4.5. Warning about PLL Clock Operation

If the external clock stops, the device might continue to operate at the same frequency of the internal PLL oscillator.

Note: This operation is outside the guaranteed operation range!


2. Package Dimensions

2.1. Package Dimensions

Figure 2.1 shows the package dimensions of the SC1810 series.

Figure 2.1. : FCBGA-1024 Package Dimensions

Socionext Europe GmbH 2 - 1 SC1810Graphic Competence Center - GCC Data Sheetds-sc1810-rev1.10 Package Dimensionshttps://www.eu.socionext.com/ Rev1.10 | November 12, 2018

2.2. Package Markings

Figure 2.2 shows the package markings of the SC1810 series.

Figure 2.2. : SC1810 Package Markings

Table 2.1. : SC1810 Package MarkingsItem Marking Contents Letter Font Height (mm)Index pin (1) mark ● Figure 1.00Company name socionext Figure 1.80Part Number SC1810A Gothic 1.20Lot Number 1600 Gothic 1.20Series Number Z00 Gothic 1.20Part Number 2 XXX Gothic 1.20Trademark ARM Figure 1.20


2.3. Recommended PCB Land Design

Table 2.2. : Recommended PCB land design ruleSMD (solder-mask defined) NSMD (nonsolder-mask defined)

Solder-mask opening Pad pattern

0.80mm pitch Φ0.40mm Φ0.38 ~ Φ0.40mm

��NSMD��SMD

Pad pattern

Solder-maskopening

Solder-maskopening


3. Ball Assignment and Pinning

3.1. Ball Assignment (Top View)

Figure 3.1 shows the ball assignment of the SC1810 series.

Figure 3.1. : Ball Assignment (Top View)

A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM

32 NC1 VSSCAP3CLK

VSS SPI_DI VSSSPI_SC

KVSS EXP1 EXP3 EXP5 EXP7 EXP9 VSS

AD_VRL

AD_VIN0

AD_VIN2

VSSMEM_ED13

MEM_ED11

MEM_ED6

MEM_XCS0

MEM_ED4

VSSMEM_CLK

VSSMEM_EA7

MEM_EA12

MEM_EA15

MEM_EA21

VSS NC2 32

31 VSSCAP2VI_3

CAP2VI_1

CAP3VI_2

CAP3VI_0

GPIO_0

GPIO_4

VSS EXN1 EXN3 EXN5 EXN7 EXN9 VSSAD_VRH

AD_VIN1

AD_VIN3

VSSMEM_ED15

MEM_ED12

MEM_ED10

MEM_ED2

MEM_XWR0

MEM_ED0

MEM_XCS1

MEM_MNW

EX

MEM_EA4

MEM_EA16

MEM_EA19

MEM_EA25

I2C0_SCL

VSS 31

30CAP2CLK

CAP1VI_3

CAP3VI_7

CAP2VI_0

CAP3VI_3

GPIO_2

GPIO_1

VSS EXP0 EXP2 EXP4 EXP6 EXP8 VSSAD_V

RCVSS VSS VSS

MEM_ED14

MEM_ED5

MEM_ED1

MEM_XCS2

MEM_CLE

MEM_XWR1

MEM_EA1

MEM_EA6

MEM_EA8

MEM_EA17

MEM_EA20

I2C0_SDA

VPDOSDCLK0

30

29 VSSCAP2VI_2

CAP2VI_7

CAP3VI_4

CAP3VI_1

SPI_SSGPIO_

3VSS EXN0 EXN2 EXN4 EXN6 EXN8 VSS VSS VSS VSS VSS

MEM_ED9

MEM_ED8

MEM_ALE

MEM_RDY

MEM_MNRE

X

MEM_EA5

MEM_EA9

MEM_EA10

MEM_EA18

MEM_EA26

MEM_EA24

MPXMODE

1

MPXMODE

2VSS 29

28CAP1CLK

VSSCAP2VI_6

CAP3VI_5

CAP3VI_6

VSSSPI_D

OVSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

MEM_ED7

MEM_ED3

MEM_XRD

MEM_EA2

MEM_EA3

MEM_EA11

MEM_EA13

MEM_EA14

MEM_EA23

MEM_EA22

MPXMODE

0

JTAGSEL

ISD0CD

ISD0WP

28

27 VSSCAP0F

IDCAP1VI_2

CAP2VI_5

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSSSD_PWR_O

SD_PSEL

SD0DAT6

SD0DAT5

SD0DAT4

27

26CAP1VI_6

CAP1VI_5

CAP0VAL

CAP1VI_1

CAP2VI_4

VSS VSS VSS VSS VSS VSS VSS VSSTH_AV

DVSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SD0DAT7

SD0DAT2

SD0DAT1

SD0CMD

SD0DAT0

26

25CAP0

VSCAP1VI_4

CAP0HS

CAP1VI_7

CAP1VI_0

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDE18 VSS VSS VSS VSSSD0DAT3

TDO XTRST TMS TDI 25

24CAP0

B0CAP0

B5CAP0

B2CAP0

B7CAP0

B6VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDE33 VSS VDE33 VSS

SSCGVDD_CA

9VSS

SDVDE18

VSS VSS VSS TCK XSRST NCUSB_SYSINT

VSS 24

23CAP0

G6CAP0

G5CAP0

B1CAP0

B4CAP0

B3VSS VSS VSS VSS VSS VSS VSS

FVDE18

VSSAD_AVD

VSS VSS VSS VDE33 VSS VDE33 VSSSDVDE33

VSS VSS VSS VSS VSSUSB_PRTPW

R

USB_OC

VSSUSB_CRYCK4

823

22CAP0

R7CAP0

G3CAP0

G4CAP0

G1CAP0

G7VSS VSS VSS VSS VDE33 VSS

PLLVDD_FPD

VSSFVDE1

8VSS

AD_AVD

VSS VDE33 VSS VDE33 VSS VDE33 VSSPLLVDD_SD

VSS VSS VSS VSS VSS VSS VSS VSS 22

21CAP0

R2CAP0

R6CAP0

G0CAP0

G2VSS VSS VSS VSS VDE33 VSS VDE33 VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDE33 VSS

AVDDUS18

VSS VSS VSSUSB_RTERM

VSSUSB_D

PUSB_D

M21

20 VSSCAP0

R3CAP0

R4CAP0

R5VSS VSS VSS VSS VSS VDE33 VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDE33 VSS

AVDDUS18

VSSAVDDUS33

VSS VSS VSS VSS VSS VSS 20

19CAP0CLK

CAP0R0

CAP0R1

VSS VSS VSS VSS VSS VDE33 VSS VDE33 VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSSAVDDUS33

VSSMA11

_0MA14

_0MA13

_0MDTO

0_0MATO

_0MDTO

1_019

18 VSS VSS VSS VSS VSS VSS VSS VSS VSSPLLVDD_DIS

PVSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VSS VSS VSS

MA9_0

MA10_0

MXCAS_0

MA8_0

MXWE_0

MA12_0

18

17MIPI_D2P

MIPI_D2N

MIPI_D3P

MIPI_D3N

VSS VSS VSS VSS VSS VSS VSS VSS VDD VSS VDD VSS VDD VSS VDD VSSD0VDE15

VSSD0VDE15

VSSMVREF0_0

VSSMA2_

0MA4_

0MA3_

0MA6_

0MA5_

0MA7_

017

16MIPI_CLKP

MIPI_CLKN

VSS VSS VSS VSS VSSMIPI_EXT12K

VSSMIPI_VDD

VSSMIPI_VDD

VSS VDD VSS VDD VSS VDD VSS VDD VSSD0VDE15

VSS VSS VSSVAA_P

LL0MBA0

_0MXRA

S_0MODT

_0MBA1

_0MA0_

0MA1_

016

15MIPI_D1P

MIPI_D1N

MIPI_D0P

MIPI_D0N

VSS VSS VSS VSSMIPI_VDE

VSSMIPI_VDE

VSS VDD VSS VDD VSS VDD VSS VDD VSSD0VDE15

VSSD0VDE15

VSSMZQ_

0VSS

MXCS_0

MCKE_0

MBA2_0

MXRESET_0

VSS VSS 15

14 VSS VSS VSS VSS VSS VSS VSS VSS VSS VDE33 VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSSD0VDE15

VSS VSS VSSVAA_P

LL0MDQ4

_0MDQ0

_0MDQ1

_0VSS

MCK_0

MXCK_0

14

13GTX_C

LKMDC MDIO TXD7 TXD6 VSS VSS VSS VDE33 VSS VDE33 VSS VDD VSS VDD VSS VDD VSS VDD VSS

D0VDE15

VSSD0VDE15

VSS VSS VSSMDQ5

_0MDQ6

_0MDQ3

_0MDQ2

_0VSS VSS 13

12RX_CL

KTXD5 TXD2 TXD4 TXD3 VSS VSS VSS VSS VDE33 VSS VDD VSS

D1VDE15

VSSD1VDE15

VSSD1VDE15

VSSD1VDE15

VSSD0VDE15

VSS VSS VSSMVREF1_0

MDQ15_0

MDM0_0

MDQ7_0

VSSMDQS

0_0MXD

QS0_012

11 VSS TX_EN TXD1 TXD0 TX_ER VSS VSS VSS VDE33 VSS VDE33 VSS VDE33 VSSD1VDE15

VSSD1VDE15

VSSD1VDE15

VSS VSS VSSD0VDE15

VSSVAA_P

LL0VSS

MDQ12_0

MDQ13_0

MDQ14_0

MDM1_0

VSS VSS 11

10TX_CL

KRXD1

RX_DV

RX_ER RXD2 VSS VSS VSS VSS VDE33 VSS VDE33 VSSD1VDE15

VSSD1VDE15

VSSD1VDE15

VSSD1VDE15

VSS VSS VSS VSS VSS VSSMDQ1

7_0MDQ9

_0MDQ1

1_0VSS

MDQS1_0

MXDQS1_0

10

9OSC_CLK

RXD0 RXD5 RXD3 RXD6 VSS VSS VSS VDE33 VSS VDE33 VSS VDE33 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDE18 VSSMDQ2

1_0MDQ1

6_0MDQ8

_0MDQ1

0_0VSS VSS 9

8 VSS RXD7 RXD4 COLI2S1_S

DOVSS VSS VSS VSS VSS VSS VSS VSS

MZQ_1

VSSMVREF0_1

VSSVAA_P

LL1VSS

VAA_PLL1

VSSSSCG1VDD

VSS VSS VSS VSSMDM3_0

MDQ20_0

MDQ19_0

MDQ18_0

VSS VSS 8

7I2S1_E

CLKCRS

I2S1_SDI

DISP1B7

I2S1_WS

VSS VSS VSS VSS VSS VSS VSS VSS VSSVAA_P

LL1VSS

MVREF1_1

VSS VSS VSS VSS VSSSSCG0VDD

VSS VSS VSSMDQ2

8_0MDQ3

0_0MDQ2

3_0VSS

MDQS2_0

MXDQS2_0

7

6I2S1_S

CKDISP1

B3DISP1

B4DISP1

G6DISP1

G2VSS

DISP1R2

DISP1DE

PWM_O2

VSSMXRESET_1

MA14_1

MA7_1

MA4_1

MA1_1

MDTO0_1

MDQ5_1

MDQ1_1

MDQ9_1

MDQ15_1

MDQ21_1

MDQ16_1

MDQ28_1

MDM3_1

PLLBYPASS

VSSMDQ2

4_0MDQ2

9_0MDM2_0

MDQ22_0

VSS VSS 6

5 VSSDISP1

B6DISP1

G7DISP1

B0DISP1

G1DISP1

R4DISP1

GV

DISP1VSYN

C

USART2_SI

NVSS

MA13_1

MA10_1

MA8_1

MA3_1

MXRAS_1

MATO_1

MDQ6_1

MDQ2_1

MDQ10_1

MDQ14_1

MDQ22_1

MDQ17_1

MDQ25_1

MDQ29_1

SELFLTEST

MODEVSS

MDQ26_0

MDQ31_0

VSSMDQS

3_0MXD

QS3_05

4DISP1

B5DISP1

B2DISP1

G3VSS

DISP1R3

DISP1R1

DISP1CSYN

C

USART2_SO

UT

USART0_SC

KVSS

MXWE_1

MXCAS_1

MA2_1

MBA0_1

MDTO1_1

MXCS_1

MDQ7_1

MDQ3_1

MDQ0_1

MDQ12_1

MDQ23_1

MDQ18_1

MDQ26_1

MDQ27_1

MDQ30_1

XRSTVINIT

HIVSS VSS

MDQ27_0

VSS VSS 4

3DISP1

B1DISP1

G5VSS

DISP1R6

DISP1R5

GPIO_22

DISP1HSYN

C

USART1_SO

UT

USART0_SI

NVSS

MA12_1

MA9_1

MA0_1

MODT_1

VSSMDM0_1

VSSMDQ4

_1VSS

MDQ11_1

MDM1_1

MDQ19_1

MDQ24_1

VSSMDQ3

1_1VSS

CRIPM3

CRIPM2

VSS VSSMDQ2

5_0VSS 3

2 VSSDISP1

G4DISP1

R7DISP1

G0DISP1

R0PWM_

O0PWM_

O1

USART1_SI

N

USART0_SO

UTVSS

MA11_1

MA5_1

MCKE_1

VSSMCK_

1VSS

MDQS0_1

VSSMDQS

1_1VSS

MDQ13_1

MDQ20_1

VSSMDQS

2_1VSS

MDQS3_1

VSS CLKX1CRIPM1

VSS VSS VSS 2

1 NC0 VSSDISPC

LKIDISP1CLKO

VSSUSART2_SC

KVSS

USART1_SC

K

DISP1CLKI

VSSMA6_

1MBA1

_1MBA2

_1VSS

MXCK_1

VSSMXD

QS0_1VSS

MXDQS1_1

VSSMDQ8

_1MDM2_1

VSSMXD

QS2_1VSS

MXDQS3_1

VSS VSS CLKX0CRIPM0

VSS NC3 1

A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM

MIP

I

DDR-IF

LVDS ADC

US

B2

.0D

DR

-IF

Socionext Europe GmbH 3 - 1 SC1810Graphic Competence Center - GCC Data Sheetds-sc1810-rev1.10 Ball Assignment and Pinninghttps://www.eu.socionext.com/ Rev1.10 | November 12, 2018

3.2. Pin Descriptions for each Interface

The following describes the pins used for each function. Refer to the attached pinlist “SC1810_pinlist_1.2.xls” for correspondence with the ball name.

3.2.1. System

3.2.2. Power Supply

Pin name DescriptionCLKX0 Reference clock inputCLKX1 System ClockXRST System ResetCRIPM[3:0] Reserved (Connect to GND)VINITHI Reserved (Connect to GND)PLLBYPASS Reserved (Connect to GND)SELFL Boot device select (Refer to Table 6.1)TESTMODE Reserved (Connect to GND)

MPXMODE[1:0]Pin multiplex mode #A select (0:mode0, 1:mode1, 2:mode2, 3:mode3)

MPXMODE2 Pin multiplex mode #B select (0:mode0 or mode 2, 1:mode1)VPD Reserved (Connect to GND)

Pin name DescriptionSSCG0VDD SSCG power supply for function (0.9V)SSCG1VDD SSCG power supply for DDRC (0.9V)PLLVDD_FPD PLL power supply for FPD (0.9V)PLLVDD_DISP PLL power supply for Display (0.9V)PLLVDD_SD PLL power supply for SD and other functions (0.9V)SSCGVDD_CA9 SSCG power supply for CPU (0.9V)D0VDE15 IO power supply for DDRC ch0 (DDR3:1.5V/DDR3L:1.35V)D1VDE15 IO power supply for DDRC ch1 (DDR3:1.5V/DDR3L:1.35V)VAA_PLL0 PLL for DDRC ch0 power supply (1.8V)VAA_PLL1 PLL for DDRC ch1 power supply (1.8V)VDE33 IO power supply(3.3V)VDE18 IO power supply(1.8V)VDD Core power supply(0.9V)VSS GroundNC Not connectedNC0 Not connectedNC1 Not connectedNC2 Not connectedNC3 Not connected


3.2.3. ICE

3.2.4. USB HOST/FUNC Controller

3.2.5. I2C BUS Interface 0

3.2.6. I2C BUS Interface 1

3.2.7. Analog Digital Converter (ADC)

Pin name DescriptionJTAGSEL JTAG selection (0: Normal / 1: Boundary Scan Mode)TCK Test clockXTRST Test resetTMS Test modeTDI Test data inputTDO Test data outputXSRST Reset from debugger

Pin name DescriptionUSB_DP D+ pinUSB_DM D- pinUSB_RTERM Connect 3.6 kohm resistorAVDDUS33 USB power supply(3.3V)AVDDUS18 USB power supply(1.8V)USB_CRYCK48 48MHz OHCI clock. PHY reference clock USB_PRTPWR EHCI: turn on/off the power of the portUSB_OC EHCI: over currentUSB_SYSINT EHCI: system interrupt

Pin name DescriptionI2C0_SCL ClockI2C0_SDA Data

Pin name DescriptionI2C1_SCL ClockI2C1_SDA Data

Pin name DescriptionAD_AVD ADC power supply (1.8V)AD_VRH Reference voltage “H” input


3.2.8. Temperature Sensor

3.2.9. DDR Controller 0

3.2.10. DDR Controller 1

AD_VRL Reference voltage “L” inputAD_VRC Reference OutputAD_VIN[3:0] Analog input

Pin name DescriptionTH_AVD Temperature Sensor power supply (1.8V)TH_INT Temperature Sensor interrupt

Pin name DescriptionMDQ[31:0]_0 DataMDM[3:0]_0 Data MaskMDQS[3:0]_0 Data Strobe (Differential)MXDQS[3:0]_0 Data Strobe (Differential)MCK_0 Clock (Differential)MXCK_0 Clock (Differential)MA[14:0]_0 AddressMXCS_0 Chip selectMCKE_0 Clock enableMXCAS_0 Column address strobeMXRAS_0 Row address strobeMXWE_0 Write enableMBA[2:0]_0 Bank addressMODT_0 On-die termination signalMXRESET_0 ResetMZQ_0 ZQ bias (240 ohm ±1%)MVREF0_0 Reference voltageMVREF1_0 Reference voltageMATO_0 ReservedMDTO0_0 ReservedMDTO1_0 Reserved

Pin name DescriptionMDQ[31:0]_1 DataMDM[3:0]_1 Data MaskMDQS[3:0]_1 Data Strobe (Differential)MXDQS[3:0]_1 Data Strobe (Differential)MCK_1 Clock (Differential)MXCK_1 Clock (Differential)MA[14:0]_1 Address


3.2.11. Ethernet Link Controller

3.2.12. SD Input/Output (SDIO)

MXCS_1 Chip selectMCKE_1 Clock enableMXCAS_1 Column address strobeMXRAS_1 Row address strobeMXWE_1 Write enableMBA[2:0]_1 Bank addressMODT_1 On-die termination signalMXRESET_1 ResetMZQ_1 ZQ bias (240 ohm ±1%)MVREF0_1 Reference voltageMVREF1_1 Reference voltageMATO_1 ReservedMDTO0_1 ReservedMDTO1_1 Reserved

Pin name DescriptionGTX_CLK Transmit clockTX_CLK Transmission clockRX_CLK Reception clockOSC_CLK Transmission clockTXD[7:0] Transmission dataTX_EN Transmission enableTX_ER Transmission errorCRS Carrier detectionCOL CollisionRX_DV Reception data validRXD[7:0] Reception dataRX_ER Reception errorPHY_INTR PHY interruptMDC Management data clockMDIO Management data

Pin name DescriptionOSDCLK0 ClockSD0CMD CommandSD0DAT[7:0] DataISD0WP Write ProtectISD0CD Card DetectSD_PWR_O Bus Power (0:off/1:on)SD_PSEL Operating voltage selection (0:3.3V/1:1.8V)SDVDE18 IO power supply for SD/eMMC (1.8V) (*1)SDVDE33 IO power supply for SD/eMMC (3.3V) (*2)SD_PWRERR SD power supply error


3.2.13. FPD Link

3.2.14. MIPI CSI-2

SD_RSTN Reset control pin for eMMCSD_VCC_O VCC control pin for eMMCSD_VCCQ VCCQ control pin for eMMC(*1) Even for 3.3V signaling, it needs to connect to 1.8V power.(*2) For 1.8V signaling, it needs to change power from 3.3V to 1.8V during operation.

Pin name DescriptionFPDCLK PLL reference clock input for FPDEXP0 FPD ch1 Differential data0(P)EXN0 FPD ch1 Differential data0(N)EXP1 FPD ch1 Differential data1(P)EXN1 FPD ch1 Differential data1(N)EXP2 FPD ch1 Differential data2(P)EXN2 FPD ch1 Differential data2(N)EXP3 FPD ch1 Differential data3(P)EXN3 FPD ch1 Differential data3(N)EXP4 FPD ch1 Differential clock(P)EXN4 FPD ch1 Differential clock(N)EXP5 FPD ch0 Differential clock(P)EXN5 FPD ch0 Differential clock(N)EXP6 FPD ch0 Differential data3(P)EXN6 FPD ch0 Differential data3(N)EXP7 FPD ch0 Differential data2(P)EXN7 FPD ch0 Differential data2(N)EXP8 FPD ch0 Differential data1(P)EXN8 FPD ch0 Differential data1(N)EXP9 FPD ch0 Differential data0(P)EXN9 FPD ch0 Differential data0(N)FVDE18 IO power supply for FPD (1.8V)

Pin name DescriptionMIPI_CLKP Differential clock input (P)MIPI_CLKN Differential clock input (N)MIPI_D0N Differential data input for lane0 (N)MIPI_D0P Differential data input for lane0 (P)MIPI_D1N Differential data input for lane1 (N)MIPI_D1P Differential data input for lane1 (P)MIPI_D2N Differential data input for lane2 (N)MIPI_D2P Differential data input for lane2 (P)MIPI_D3N Differential data input for lane3 (N)MIPI_D3P Differential data input for lane3 (P)MIPI_EXT12K Connect to 12 kohm ±1% resistor


3.2.15. Display Clock

3.2.16. Display 1 (RGB)

3.2.17. Display 2 (RGB)

3.2.18. SEERISTM-MCR 0 (YUV)

MIPI_VDD IO power supply for MIPI D-PHY (0.9V)MIPI_VDE IO power supply for MIPI D-PHY (1.8V)

Pin name Description

DISPCLKIPLL reference clock input for Display /Dot clock input for DISP and SEERIS-MCR0

Pin name DescriptionDISP1CLKI Dot clock inputDISP1CLKO Dot clock outputDISP1HSYNC Horizontal SynchronizationDISP1VSYNC Vertical SynchronizationDISP1CSYNC Composite SynchronizationDISP1DE Display Valid PeriodDISP1GV Graphics/Video SwitchingDISP1R[7:0] Digital Video Output (Red)DISP1G[7:0] Digital Video Output (Green)DISP1B[7:0] Digital Video Output (Blue)

Pin name DescriptionDISP2CLKI Dot clock inputDISP2CLKO Dot clock outputDISP2HSYNC Horizontal SynchronizationDISP2VSYNC Vertical SynchronizationDISP2CSYNC Composite SynchronizationDISP2DE Display Valid PeriodDISP2GV Graphics/Video SwitchingDISP2R[7:0] Digital Video Output (Red)DISP2G[7:0] Digital Video Output (Green)DISP2B[7:0] Digital Video Output (Blue)

Pin name DescriptionYUV0CLKO Dot clock outputYUV0HSYNC Horizontal Synchronization


3.2.19. Display Controller 1 (YUV)

3.2.20. SEERISTM-MCR 2 (YUV)

3.2.21. TCON

3.2.22. Video Capture Unit (CAP)

YUV0VSYNC Vertical SynchronizationYUV0V[7:0] Digital Video Output

Pin name DescriptionYUV1CLKO Dot clock outputYUV1HSYNC Horizontal SynchronizationYUV1VSYNC Vertical SynchronizationYUV1V[7:0] Digital Video Output

Pin name DescriptionYUV2CLKO Dot clock outputYUV2HSYNC Horizontal SynchronizationYUV2VSYNC Vertical SynchronizationYUV2V[7:0] Digital Video Output

Pin name DescriptionTCON_CLKO Dot clock outputTCON_TSIG[11:0] Digital Video Control SignalTCON_R[7:0] Digital Video Output (Red)TCON_G[7:0] Digital Video Output (Green)TCON_B[7:0] Digital Video Output (Blue)

Pin name DescriptionCAP0CLK Refer to Chapter of Video CaptureCAP0VS Refer to Chapter of Video CaptureCAP0HS Refer to Chapter of Video CaptureCAP0FID Refer to Chapter of Video CaptureCAP0VAL Refer to Chapter of Video CaptureCAP0R[7:0] Refer to Chapter of Video CaptureCAP0G[7:0] Refer to Chapter of Video CaptureCAP0B[7:0] Refer to Chapter of Video CaptureCAP1CLK Refer to Chapter of Video CaptureCAP1VI_[7:0] Refer to Chapter of Video CaptureCAP2CLK Refer to Chapter of Video CaptureCAP2VI_[7:0] Refer to Chapter of Video Capture


3.2.23. External Interrupt Controller (EXIRC)

3.2.24. SPI Interface

3.2.25. Controller Area Network 0 (CAN)

3.2.26. Controller Area Network 1 (CAN)

3.2.27. Media LB

CAP3CLK Refer to Chapter of Video CaptureCAP3VI_[7:0] Refer to Chapter of Video CaptureCAP5CLK ClockCAP5HSYNC Horizontal SynchronizationCAP5VSYNC Vertical SynchronizationCAP5VI_[7:0] Video Data

Pin name DescriptionINT_A[3:0] External Interrupt Request

Pin name DescriptionSPI_DO Data outputSPI_DI Data inputSPI_SCK ClockSPI_SS Slave Select

Pin name DescriptionCAN0_TX TransmissionCAN0_RX Reception

Pin name DescriptionCAN1_TX TransmissionCAN1_RX Reception

Pin name DescriptionMLB_DATA DataMLB_SIG ControlMLB_CLK Clock


3.2.28. Audio Interface 0 (I2S)



3.2.31. Pulse Width Modulator (PWM)

3.2.32. UART/USART 0

Pin name DescriptionI2S0_SCK ClockI2S0_WS SyncI2S0_ECLK External ClockI2S0_SDO Output DataI2S0_SDI Input Data



Pin name DescriptionPWM_O[3:0] PWM outputPWM_O[7:5] PWM output

Pin name DescriptionUSART0_SIN Input dataUSART0_SOUT Output dataUSART0_SCK Serial ClockUART0_XCTS Clear to send









Pin name DescriptionUSART3_SIN Input dataUSART3_SOUT Output dataUSART3_SCK Serial Clock




3.2.38. External DMA Interface (XDMAC)

3.2.39. HOST Interface

3.2.40. GPIO

3.2.41. High-speed Serial Parallel Interface 0 (HS-SPI)

3.2.42. High-speed Serial Parallel Interface 1 (HS-SPI)

Pin name DescriptionDREQ External DMA request (to XDMAC)DACK External DMA acknowledge (from XDMAC)

Pin name DescriptionHOST_XCS Chip selectHOST_DO Data outputHOST_DI Data inputHOST_SCK Clock

Pin name DescriptionGPIO[4:0] General Purpose Input/OutputGPIO[22:18] General Purpose Input/OutputGPIO[65:54] General Purpose Input/OutputGPIO[127:69] General Purpose Input/Output

Pin name DescriptionHS0_SD[3:0] DataHS0_SCK ClockHS0_SSEL[3:0] Slave select

Pin name DescriptionHS1_SD[3:0] DataHS1_SCK ClockHS1_SSEL[3:0] Slave select


3.2.43. External Bus Controller (EBC)

Pin name DescriptionMEM_XCS[2:0] Chip selectMEM_XRD Read strobeMEM_XWR[1:0] Write StrobeMEM_RDY ReadyMEM_CLK ClockMEM_ALE Address latch enable (for NAND Flash)MEM_CLE Command latch enable (for NAND Flash)MEM_MNREX Read enable (for NAND Flash)MEM_MNWEX Write enable (for NAND Flash)MEM_EA[26:1] AddressMEM_ED[15:0] Data


4. Electrical Characteristics

4.1. Absolute Maximum Ratings

Table 4.1. : Absolute Maximum RatingsParameter Symbol Value Unit

Supply voltage

0.9V group *1

1.5V group *2

1.8V group *3

3.3V group *4

-0.5 to 1.04-0.5 to 1.98-0.5 to 2.5-0.5 to 4.6

V

Input voltage VI-0.5 to VDE18 + 0.5 (Max:2.5V)-0.5 to VDE33 + 0.5 (Max:4.6V)

V

Output voltage VO-0.5 to VDE18 + 0.5 (Max:2.5V)-0.5 to VDE33 + 0.5 (Max:4.6V)

V

ESD damage immunityHuman Body Model (HBM)Charge Device Model (CDM)

VESD+1500/-1500+500/-300

V

Supply current Id

0.9V group*5

AVM(Camera), Cluster, HUD: 5.00AVM(DEC), Cluster, HUD: 7.50Drive Recorder(ENC): 6.80DDRVDE (1.5V): 0.50

1.8V group *6: 0.15

3.3V group *7: 0.30VAA_PLL (1.8V): 0.015MIPI_VDD (0.9V): 0.040MIPI_VDE (1.8V): 0.007AVDDUS18 (1.8V): 0.045AVDDUS33 (3.3V): 0.045FVDE18 (1.8V): 0.086

A

Storage temperature Tst -55 to 125 C

*1 AVD, SSCGVDD, PLLVDD, MIPI_VDD (0.9V)

*2 DDRVDE (1.5V)

*3 VDE18, SDVDE18, AD_AVD, TH_AVD, VAA_PLL, MIPI_VDE, AVDDUS18, FVDE18 (1.8V)

*4 VDE33, SDVDE33, AVDDUS33

*5 VDD, SSCGVDD, PLLVDD

*6 VDE18, SDVDE18, AD_AVD, TH_AVD

*7 VDE33, SDVDE33

Socionext Europe GmbH 4 - 1 SC1810Graphic Competence Center - GCC Data Sheetds-sc1810-rev1.10 Electrical Characteristicshttps://www.eu.socionext.com/ Rev1.10 | November 12, 2018

Notes:Applying stress exceeding the maximum ratings (voltage, current, temperature, etc.) may cause damage

to semiconductor devices. Never exceed the ratings above.Never connect IC outputs or I/O pins directly, or connect them to VDD or VSS directly; otherwise thermal

destruction of elements will result, but which does not apply to pins designed to prevent signal collision.Provide ESD protection, such as grounding when handling the product; otherwise externally-charged

electric charge flows inside the IC and discharges, which may result in damage to the circuit.Applying voltage higher than VDD or lower than VSS to I/O pins of CMOS IC, or applying voltage higher

than the ratings between VDD and VSS may cause latch up. The latch up increases supply current, resulting in thermal destruction of elements. When handling the product, never exceed the maximum ratings.

4.2. Power Consumption

Note: The following values are measurement examples. The values are different depending on the measurementenvironment, the operation condition, and the sample. These values are for the thermal design. If each powersupply current is necessary, it can be estimated from the maximum ratings as the same ratio.

ConditionsFrequency: CA9 1066MHz, DDR 1866MHz(DDR3-1866 2ch), VPU 600MHz, GPU 400MHzVoltage: TYPApplication: The following application program is executed at the same time.

(a) Cluster 1920x720p60, Display 1ch(b) AVM 1280x720p60, Capture 4ch, Display 1ch(c) HUD 800x480p60, Display 1ch

4.3. Temperature Conditions

The temperature conditions are given in Table 4.3

Table 4.2. : Power Consumption

ItemValue

Unit25 deg. 85 deg.

AVM(Camera), Cluster, HUD 3.2 4.3 WAVM(DEC), Cluster, HUD 3.8 5.2 WDrive Recorder(ENC) 3.6 4.9 W

Table 4.3. : Temperature ConditionsParameter Symbol Value Unit

Operating case temperature TC -40 to 99.78 C

Junction temperature TJ -40 to 110 C


4.4. Thermal Design

Under the following conditions:PCB JEDEC / 114.3 x 101.6 x 1.6 mm / 8 layer

θJA and ψJT are the values of the reference under the JEDEC condition.

4.5. Recommended Operating Conditions

4.5.1. Standard CMOS I/O

Table 4.4. : Thermal DesignPackage θJA [K/W] ψJT [K/W] θJC [K/W] θJB [K/W]

FCBGA1024 11.11 1.09 1.46 4.84

Table 4.5. : 3.3V standard CMOS I/O recommended operating conditions

Parameter Symbol ConditionValue

UnitMin Typ Min

Power supply voltageVDDIO

VDE33 3.3V 3.135 3.3 3.465V

VDE18 1.8V 1.71 1.8 1.89

VDD 0.855 0.9 0.945 V

Input voltage(High level)

VIH3.3V 0.75*VDE33 - - V

1.8V 0.75*VDE18 - - V

Input voltage(Low level)

VIL3.3V - - 0.25*VDE33 V

1.8V - - 0.25*VDE18 V

Schmitt hysteresis voltage VH3.3V 0.2 - -

V1.8V 0.1 - -


4.5.2. DDR I/O

Table 4.6. : SSTL I/O Recommended Operating Conditions

Parameter SymbolValue

UnitMin Typ Max

PLL and SSTL receiver supply voltage VAA_PLL 1.62 1.8 1.98 V

SSTL output supply voltage (DDR3)

VDDQ

1.425 1.5 1.575 V

SSTL output supply voltage (DDR3L)

1.283 1.35 1.45 V

SSTL reference supply voltage VREF 0.49*VDDQ 0.5*VDDQ 0.51*VDDQ V

External termination voltage VTT VREF – 0.04 VREF VREF + 0.04 V

AC input logic threshold High for Command and Address

(DDR3-1866)VIH.CA(AC135) VREF + 0.135 - *1 V

AC input logic threshold Low for Command and Address

(DDR3-1866)VIL.CA(AC135) *1 - VREF – 0.135 V


(DDR3-1600)VIH.CA(AC175) VREF + 0.175 - *1 V


(DDR3-1600)VIL.CA(AC175) *1 - VREF – 0.175 V


(DDR3L-1600)VIH.CA(AC160) VREF + 0.160 - *1 V


(DDR3L-1600)VIL.CA(AC160) *1 - VREF – 0.160 V

AC input logic threshold High for DQ and DM (DDR3-1866)

VIH.DQ(AC135) VREF + 0.135 - *1 V

AC input logic threshold Low for DQ and DM (DDR3-1866)

VIL.DQ(AC135) *1 - VREF – 0.135 V

AC input logic threshold High for DQ and DM (DDR3-1600)

VIH.DQ(AC150) VREF + 0.150 - *1 V

AC input logic threshold Low for DQ and DM (DDR3-1600)

VIL.DQ(AC150) *1 - VREF – 0.150 V


4.5.3. SSCG/PLL

4.5.4. I2C I/O

AC input logic threshold High for DQ and DM (DDR3L-1600)

VIH.DQ(AC135) VREF + 0.135 - *1 V

AC input logic threshold Low for DQ and DM (DDR3L-1600)

VIL.DQ(AC135) *1 - VREF – 0.135 V

Standard SSTL recommended operating conditions (excerpt from JESD79-3F)*1: Overshoot / Undershoot rule of JESD79-3F.

Table 4.7. : SSCG/PLL Recommended Operation Conditions


UnitMin. Typ. Max.

Supply voltage SSCG*/PLL* 0.855 0.9 0.945 V

Table 4.8. : I2C Recommended Operation Conditions

Parameter SymbolStandard Mode Fast Mode(*1)

UnitMin Typ Max Min Typ Max

"L" level input voltage VIL -0.5 - 0.3*VDE18 -0.5 - 0.3*VDE18 V

"H" level input voltage VIH 0.7*VDE18 - 3.63 (*2) 0.7*VDE18 - 3.63 (*2) V

Schmitt trigger hysteresis Vhys - - - 0.05*VDE18 - - V

*1: This I2C Bus Fast Mode I/O buffer is downwards compatible with Standard Mode. *2: This I/O can be applied up to a maximum of 3.63V.

Table 4.6. : SSTL I/O Recommended Operating Conditions (Continued)


4.5.5. FPD I/O

4.5.6. MIPI I/O

4.5.7. SD I/O

Table 4.9. : FPD Recommended Operation Conditions


UnitMin. Typ. Max.

Supply voltage FVDE18 1.65 1.8 1.95 V

Table 4.10. : MIPI Recommended Operation Conditions


UnitMin. Typ. Max.

Supply voltageMIPI_VDE 1.7 1.8 1.95 V

MIPI_VDD 0.85 0.9 0.99 V

Table 4.11. : SDIO Recommended Operation Conditions


UnitMin Typ Max

Supply voltage

SDVDE33 (MSEL=0) 3.135 3.30 3.45

VSDVDE33 (MSEL=1) 1.71 1.80 1.89

SDVDE18 1.71 1.80 1.89

Input voltageSDVI (MSEL=0) SDVDE33*0.625 - SDVDE33+0.3 V

SDVI (MSEL=1) 1.27 - 2.00 V

Output voltageSDVO (MSEL=0) -0.3 - SDVDE33*0.25 V

SDVO (MSEL=1) -0.3 - 0.58 V


4.5.8. USB I/O

4.6. Power ON

4.6.1. Recommended Power ON/OFF Sequence

The order of power supply turning on/cutting recommends following.

[Power on]: PW0 group -> PW1 group -> PW2 group -> PW3 group -> PW4 group[Power off]: PW4 group -> PW3 group -> PW2 group -> PW1 group -> PW0 group

USB I/O Recommended Operation Conditions


UnitMin Typ Max

Supply voltageAVDDUS33 3.135 3.3 3.465

VAVDDUS18 1.71 1.8 1.89

Table 4.12. : Power On Sequence Spec.


UnitMin Typ Max

Power on diff time

t1diff 0 - - ms

t2diff 0.1 - 10 ms

t3diff 1 - 10 ms

Pamp up time

tspw0 100 - - us

tspw1 100 - - us

tspw2 100 - - us

tspw3 1 - - ms

tspw4 1 - - ms

Table 4.13. : Power GroupPower Group Symbol Description

PW0 VDD Internal core supply

PW1

MIPI_VDD MIPI D-PHY supply

PLLVDD PLL supply

SSCGVDD SSCG supply


Figure 4.1. : Power ON/OFF sequence

Supply power ON/OFF so that power for PW1 group does not exceed PW0 group.Turning part of power ON is prohibited.CMOS IC is unstable immediately after power ON. Perform a reset immediately.

The Power OFF sequence is opposite to Power ON sequence (reversed).

PW2 DVDE15 DDR I/O supply

PW3

VDE18 GPIO supply

SDVDE18 SD I/O supply

FVDE18 LVDS I/O supply

VAA_PLL PLL supply for PLL

TH_AVD Temperature sensor supply

AD_AVD A/D converter supply

AVDDUS18 USB 2.0 supply

MIPI_VDE MIPI D-PHY supply

PW4

VDE33 GPIO supply

SDVDE33 SD I/O supply

AVDDUS33 USB 2.0 PHY supply

Table 4.13. : Power Group (Continued)

PW0 Grp.

tspw0

PW1 Grp.

PW2 Grp.

PW3 Grp.

PW4 Grp.

tspw1

tspw2

tspw3t1diff

tspw4

t2diff

t3diff


4.6.2. Power ON Timing Chart

Figure 4.2. : Power on Timing Chart

Set the reset pins (XTRST, XRST) to Low when power ON.

Input the system clock immediately after power ON.The reset input (XTRST, XRST) has to be low for at least 2us after turning on PW4.

It requires at least 100 clocks of the system clock for the reset signal “L” applied to the XRST pin to be transmitted toall the internal circuits.Supply power ON/OFF so that power for VREF does not exceed PW2 group.


4.7. DC Characteristics

4.7.1. Standard CMOS I/O

Measurement condition: VDDIO (VDE33 or VDE18) = 3.3 ±0.165 V, VSS = 0 V, Tj = -40 to 110°C

4.7.2. DDR I/O

The following table provides input and output DC threshold values and On-Die-Termination (ODT) recommendedvalues. The conditions for the output threshold values are un-terminated outputs loaded with 1 pF capacitor load. TheODT values were measured after impedance calibration.

Table 4.14. : Recommended operating conditionsParameter Symbol Conditions Min. Typ. Max. Unit

System clock frequency Fref - 27 - 33.333333 MHz

Input clock rise time tr - - - 0.4 ns

Input clock fall time tf - - - 0.4 ns

Input clock pulse widthThigh High pulse 0.3 - - ns

Tlow Low pulse 0.3 - - ns

Table 4.15. : Standard CMOS I/O DC characteristics

ParameterSymbol

ConditionValue Uni

tMin. Typ. Max.

H level output voltage VOH When output current is equal to 2/4/8/16 mA 0.85*VDDIO - - V

L level output voltage VOL When output current is equal to 2/4/8/16 mA - - 0.15*VDDIO V

Input leakage current IL3.3V mode1.8V mode

- - 5.0 uA

Pull-up/pull-downresistance

Rp 25.8 33 42.6 kΩ

Table 4.16. : DDR3 Mode – DC Specifications


UnitMin. Typ. Max.

DC input voltage High VIH(DC) VREF + 0.1 - VDDQ V

DC input voltage Low VIL(DC) VSSQ – 0.3 - VREF – 0.1 V

DC output logic High VOH 0.8 * VDDQ - - V


4.7.3. I2C I/O

Note: *1: During the Fast Mode in this I/O cell is provided with a restriction of 10pF ~ 250pF for compliance tofstandard. Please be careful.

Note: *2: The I2C Bus Fast Mode I/O Buffer itself has no function to prevent a spike of 50 ns pulse width (max.).Therefore, provide an input filter to prevent a spike for both internal or external semiconductor device.

Note: In the I2C IO buffer the following pins are used: I2C0_SCL, I2C0_SDA.

DC output logic Low VOL - - 0.2 * VDDQ VInput termination resistance (ODT) to

VDDQ/2 RTT 54 60 66 ohm

Table 4.17. : DDR3L Mode – DC Specifications


UnitMin. Typ. Max.

DC input voltage High VIH(DC) VREF + 0.09 - VDDQ V

DC input voltage Low VIL(DC) VSSQ – 0.3 - VREF – 0.09 V

DC output logic High VOH 0.8 * VDDQ - - VDC output logic Low VOL - - 0.2 * VDDQ V

Input termination resistance (ODT) to VDDQ/2 RTT 54 60 66 ohm

Table 4.18. : I2C I/O direct current characteristic

Parameter SymbolStandard Mode Fast Mode(*2)

UnitMin Typ Max Min Typ Max

"L" level output voltageSink current 2[mA]

VDD ≤ 2[V]VOL2 - - - 0 - 0.2*VDE18 V

Output slew rate (Tfall)Bus capacitance 10[pF] ~

400[pF]VIH (min.) to VIL (max.) (*1)

tof - - 25020*

(VDD/5.5V)- 250 ns

Data line leakageInput voltage 0.1 ~ 0.9 VDE18

(max.)Ii -10 - 10 -10 - 10 mA

I/O pin capacitance Ci - - 10 - - 10 pF

Table 4.16. : DDR3 Mode – DC Specifications (Continued)


4.7.3.1. I2C IO V-I Characteristic Chart

Figure 4.3. : 2C V-I characteristic chart


4.7.4. FPD I/O

Figure 4.4. : Output signal levels

Figure 4.5. : Measurement circuit of output signal levels

Table 4.19. : FPD Direct Current Characteristics

Parameter Symbol ConditionValue

UnitMin Typ Max

Output offset voltage Vos Rload=100ohm 1.075 1.2 1.325 V

Output differential voltage |Vod|

Rload=100ohmNo-calibration

230 340 490 mV

Rload=100ohmwith

resistor- calibration280 340 400 mV

V(posi)

V(nega)

Vol_min

Single-ended

GND

Vod = V(posi)-V(nega)

Differential

Voh_max

Vos = [V(posi)+V(nega) ]/2

|Vod|_min

|Vod|_max

0V diff.

V(posi)

V(nega)

VRload


4.7.5. MIPI I/O

Table 4.20. : MIPI Characteristics


Unit NoteMin Typ Max

D-PHY(HS-Mode)

Input Common Mode Voltage VCM 0.025 -- 0.33 V -

Differential input high threshold VIDTH -- -- 0.07 V < 1.5Gbps

Differential input Low threshold VIDTL -0.07 -- -- V < 1.5Gbps

Single end input Voltage VRANGE -0.12 -- 0.49 V -

D-PHY LP-Mode

Logic 1 Input Voltage VIH_LP 0.74 -- -- V -

Logic 0 Input Voltage not in ULP state VIL_LP -- -- 0.55 V -

Logic 0 input voltage, ULP state VIL-ULPS -- -- 0.3 V -

Input hysteresis VHYST 0.025 -- -- V -

Single end input Voltage VRANGE -0.15 -- 1.45 V -

Resistance

External resistance EXT12K 11.88 12 12.12 Kohm -


4.7.6. USB I/O

Table 4.21. : Recommended Operating Conditions (High-speed)


UnitMin Typ Max

Input levels for high-speed:

high-speed squelch detection threshold (differential signal amplitude) VHSSQ 100 - 150 mV

High-speed disconnect detection threshold (differential signal amplitude) VHSDSC 525 - 625 mV

High-speed differential input signaling levels (this spec is based on "Template 6")

150(the absolute

value)- - mV

High-speed data signaling common mode voltage range (guideline for receiver) VHSCM -50 - 500 mV

Output levels for high-speed:

High-speed idle level VHSOI -10.0 - 10.0 mV

High-speed data signaling high VHSOH 360 - 440 mV

High-speed data signaling low VHSOL -10.0 - 10.0 mV

Chirp J level (differential voltage) VCHIRPJ 700 - 1100 mV

Chirp K level (differential voltage) VCHIRPK -900 - -500 mV

Terminations in high-speed:

Termination voltage in high-speed VHSTERM -10 - 10 mV

Table 4.22. : Recommended Operating Conditions (Full-speed/Low-speed)


UnitMin Typ Max

Input levels for full-speed/low-speed:

High (driving) VIH 2.0 - - V

High (floating) VIHZ 2.7 - 3.6 V

Low VIL - - 0.8 V

Differential input sensitivity VDI 0.2 - - V

Differential common mode range VCM 0.8 - 2.5 V

Output levels for full-speed/low-speed:

Low VOL 0.0 - 0.3 V

High (driven) VOH 2.8 - 3.6 V


4.7.7. ADC I/O

4.7.7.1. Recommended Operating Conditions

Note: *1 VLSB and Transition voltage of each code depends on by VAVD, So even if same voltage input to analoginput pin(VIN), output code varies by VAVD.

Note: *2 VSS is voltage at AVSH.

SE1 VOSE1 0.8 - - V

Output signal crossover voltage VCRS 1.3 - 2.0 V

Input capacitance for full-speed/low-speed:

Downstream facing port (being shared with upstream facing port at device mode, so the less value is selected

as the maximum spec)

CIND(CINUB)

- - 100 pF

Transceiver edge rate control capacitance CEDGE - - 75 pF

Terminations in full-speed/low-speed:

Bus pull-up resistor on upstream port (idle bus) (this is used only in the device mode (HOSTMODE = '0' set-

ting).)RPUI 0.9 - 1.575 kohm

Bus pull-up resistor on upstream port (upstream port receiving) (this is used only in the device mode (HOST-

MODE = '0' setting).)RPUA 1.425 - 3.090 kohm

Input impedance exclusive of pull-up/pull-down ZINP 300 - - kohm

Termination voltage on upstream port pull-up VTERM 3.0 - 3.6 V

Table 4.23. : Recommended Operating Conditions

Parameter Pin Name SymbolValue

UnitMin Typ Max

Power Supply Voltage AD_AVD VAVD 1.65 1.80 1.95 V

Reference Voltage(H) AD_VRH VRH AD_AVD (*1) V

Reference Voltage(L) AD_VRL VRL VSS (*2) V

Decoupling Capacitor AD_VRC CREF (*3) 0.1 - - uF

Analog Input Voltage AD_VIN0-3 VIN AD_VRL - AD_VRH V

Analog Input Frequency AD_VIN0-3 FVIN 0 - FS /2 Hz

Conversion Rate STC FS (*4) - - 2 MS/s

Clock Frequency CLK FC (*4) 5(*5) - 54 MHz

Table 4.22. : Recommended Operating Conditions (Full-speed/Low-speed) (Continued)


Note: *3 A/D outputs incorrect result at the instant following power on or at the resumption from power downmode. Resumption time is affected by the capacitance.

Note: *4 FC = FS x (NS + NC)The conversion rate is dependent on output impedance of source diving VIN.Choose the FC or NS to satisfy the expression [ Sampling time > t A ]Sampling starts soon after the second up of CLK after the up of STC.Sampling ends soon after the first up of CLK after the down of STC.Rimp is output impedance of the driver that drivers VIN.Cimp is the parastic capacitance connected to VIN(ex. the capacitance at PCB and output of driver)The relation between t A, Rimp and Cimp are shown in the following table.(On conditions that Cimp is charged to VIN before sampling starts)

t A (the time required to sample) [unit : ns]

(Analog Input Channels: 8ch)

Note: *5 Except convert period, these signals can be specified DC signal.

Rimp(Ω)Cimp(pF)

10 20 40

250 170 210 230

1000 220 250 340

10000 1460 2010 2980


4.7.7.2. Electrical Characteristics

*1 Input leak current is only internal switch of ADC. (Except Analog Switch I/O)*2 On condition that DC voltage are applied to analog voltage inputs (AD_VIN0-3).

Table 4.24. : Electrical Characteristics

Parameter Pin Name Symbol ConditionsValue

UnitsMin Typ Max

Resolution BIT - - 12 Bits

Supply Current(include reference current)

- IVD FS=2MS/s - 0.12 0.24 mA

VDD IAVD

AD_VRH=AD_AVD,

AD_VRL=VSSFS=2MS/s

- 0.94 2.00 mA

AD_AVD IDSD Power Down - 1.7 85 uA

VDD IDSA Power Down - 0.1 105 uA

Input Leak Current(*1) AD_AVD IVINON -0.4 - 0.4 uA

Reference Resistance AD_VIN0-3 RRbetween AD_VRH

and AD_VRL 1.08 2.16 3.60 kohm

Calibration

Zero Transition Voltage (*2)

- VZTbetween 0 and 1Rimp < 1k ohm

Typ-10 AD_AVD/4096 Typ+10 mV

Full Scale Transition Voltage(*2)

- VFSTbetween 4094 and

4095Rimp < 1k ohm

Typ-10 AD_AVD-AD_AVD/4096Typ+1

0 mV

Integral Non Linearity(*2)

- INLend point methodRimp < 1k ohm

-3.0 3.0 LSB

Differential Non Linearity(*2)

- DNL end point method -1.9 1.9 LSB

Without Calibration

Zero Transition Voltage (*2)

- VZTbetween 0 and 1Rimp < 1k ohm

Typ-20 AD_AVD/4096 Typ+20 mV

Full Scale Transition Voltage(*2)

- VFSTbetween 4094 and

4095Rimp < 1k ohm

Typ-20 AD_AVD-AD_AVD/4096Typ+2

0 mV

Integral Non Linearity(*2)

- INLend point methodRimp < 1k ohm

-8.0 8.0 LSB

Differential Non Linearity(*2)

- DNL end point method -6.0 6.0 LSB


4.7.8. Temperature Sensor

4.7.8.1. Recommended Operating Conditions

4.7.8.2. Electrical Characteristics

Table 4.25. : Recommended Operating Conditions


UnitMin Typ Max

Power supply voltage TH_AVD VAVD 1.65 1.80 1.95 V

Temperature sensor clock frequency -

fTSCLK 1.0 2.0 2.6 MHz

Table 4.26. : Electrical Characteristics

Parameter Symbol ConditionsValue

UnitMin Typ Max

Absolute accuracy TERRCT=2’b00 - - ±7 °C

CT=2’b01,2’b10,2’b11 - - ±5 °C


4.8. AC Characteristics

4.8.1. External Memory Bus Controller

Table 4.27. : Memory controller signal timing

Parameter Pin name SymbolValue

UnitMin Typ Max

Chip Select delay time MEM_XCS[2:0] TCSO 5 ns

Address delay time MEM_EA[26:1] TAO 5 ns

Data output delay time

MEM_ED[31:0]

TDO 5 ns

Data output HiZ time TDOZ 5 ns

SRAM/NOR Flash data setup time TDSR 7 ns

SRAM/NOR Flash data hold time TDHR 0 ns

NOR Flash page Read data setup time TDSP 7 ns

NOR Flash page Read data hold time TDHP 0 ns

RDY delay time MEM_RDY TDRI 0.5 ns

XRD delay time MEM_XRD TRDO 5 ns

XWR delay time MEM_XWR[3:0] TWRO 5 ns

Condition: CL= 10pF, IO Drive= 4mA, IO SR= Slow. The settings of the IO Drive and IO SR are in CCNT register.


Figure 4.6. : SRAM/NOR Flash Read

Figure 4.7. : SRAM/NOR Flash Write


Figure 4.8. : Low speed device Read

Figure 4.9. : Low speed device Write


Figure 4.10. : NOR Flash Page Read


4.8.2. DDR Controller

Table 4.28. : DDR Controller (DDR3-1866) signal timing by SSTL15 mode


UnitMin Typ Max

Command and Address setup timeMA*_0,

MBA*_0,MXCAS*_0,MXRAS*_0,MXWE*_0

tphy_IS_CA (2T timing)

- - 1410 ps

Command and Address hold timetphy_IH_CA (2T timing)

- - 378 ps




- - 1399 ps


- - 369 ps

Control setup time MCKE*_0,MODT*_0, MXCS*_0

tphy_IS_CTRL - - 329 ps

Control hold time tphy_IH_CTRL - - 415 ps




DQS output access time from CLK

MDQS0_0,MDQS1_0,

MXDQS0_0,MXDQS1_0

tphy_CKDQS_min -86 - - ps

DQS output access time from CLK tphy_CKDQS_-max - - 86 ps

Round Trip time from CLK out to Read DQS tphy_RT-T_Gate_min -619 - ps

Round Trip time from CLK out to Read DQS tphy_RTT_Gate_-max - 619 ps


MDQS2_0,MDQS3_0,

MXDQS2_0,MXDQS3_0



Round Trip time from CLK out to Read DQS tphy_RT-T_Gate_min -619 - - ps

Round Trip time from CLK out to Read DQS tphy_RTT_Gate_-max - - 619 ps


MDQS0_1,MDQS1_1,

MXDQS0_1,MXDQS1_1







MDQS2_1,MDQS3_1,

MXDQS2_1,MXDQS3_1





DQ and DM setup time for WriteMDQ[7:0]_0,MDQ[15:8]_0,

MDM0_0,MDM1_0

tphy_WDS - - 195 ps

DQ and DM hold time for Write tphy_WDH - - 195 ps

DQ setup time for Read tphy_RDS - - 179 ps

DQ hold time for Read tphy_RDH 356 - - ps


MDM2_0,MDM3_0

tphy_WDS - - 195 ps




DQ and DM setup time for WriteMDQ[7:0]_1, MDQ[15:8]_1,

MDM0_1,MDM1_1

tphy_WDS - - 187 ps





MDM2_1,MDM3_1

tphy_WDS - - 187 ps




Table 4.28. : DDR Controller (DDR3-1866) signal timing by SSTL15 mode (Continued)


Table 4.29. : DDR Controller(DDR3-1600) signal timing by SSTL15 mode


UnitMin Typ Max




- - 1678 ps


- - 466 ps




- - 1667 ps


- - 457 ps








MDQS0_0,MDQS1_0,

MXDQS0_0,MXDQS1_0


DQS output access time from CLK tphy_CKDQS_max - - 87 ps




MDQS2_0,MDQS3_0,

MXDQS2_0,MXDQS3_0






MDQS0_1,MDQS1_1,

MXDQS0_1,MXDQS1_1







MDQS2_1,MDQS3_1,

MXDQS2_1,MXDQS3_1





DQ and DM setup time for WriteMDQ[7:0]_0,

MDQ[15:8]_0, MDM0_0,MDM1_0

tphy_WDS - - 239 ps





MDM2_0,MDM3_0

tphy_WDS - - 239 ps




DQ and DM setup time for WriteMDQ[7:0]_1,

MDQ[15:8]_1,MDM0_1,MDM1_1

tphy_WDS - - 231 ps





MDM2_1,MDM3_1

tphy_WDS - - 231 ps




Table 4.29. : DDR Controller(DDR3-1600) signal timing by SSTL15 mode (Continued)


Table 4.30. : DDR Controller(DDR3L-1600) signal timing by SSTL135 mode


UnitMin Typ Max




- - 1656 ps


- - 453 ps




- - 1646 ps


- - 447 ps







DQS output access time from CLKMDQS0_0,MDQS1_0,

MXDQS0_0,MXDQS1_0



Round Trip time from CLK out to Read DQS tphy_RTT_Gate_min -734 - - ps


D

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