daq map of electronic components l. adeyemi, a. camsonne, e. fanchini, js. real, r. suleiman, e....
TRANSCRIPT
DAQ Map ofElectronic Components
L. Adeyemi, A. Camsonne, E. Fanchini, JS. Real, R. Suleiman, E. Voutier
May 24, 2012
VME COMMON CRATE NEW
VME 6100
Old TI
CAEN V538A
TI DB 1
Mott FADC
PEPPo (mode 1,2) FADC
DB 2
PEPPo (mode 3) FADC
S2 S1 40MHz clock
TDC CAEN V775
Discriminator Caen v985
JLab Discriminator
1234
1-> LNE Delayed From Mott NIM Delay 794 2-> Helicity From Mott NIM Lin Fan In/Out 7403-> PAT Sync From Mott NIM Lin Fan In/Out 740 4-> GATE From Mott NIM Lin Fan In/Out 740Mott DetTr from Mott NIM Crate
nT_Settle from 794 mod. Mott NIM Lin Fan In/Out 740
Control Channels
opsmdaq0
Lemo012
ECL0123
PEPPo DetTr from CH 4 PEPPo NIM Crate *
Lemo
3
ECL0
1
2
TRG IN
Common
CH 3 PEPPo NIM Crate *
OUT TRG(L1A)
IN TRG
TS#1
TS#2
TRG IN
1
Control Channels
Hel., T_Settle, Pat Sync, Pair Sync
PMTs from PEPPo Crate Lin Fan In/out PS 740 *Cosmic Det. From Patch PanelAnnihilation from PEPPo Crate Lin Fan In/out PS 740 *
CH1-CH32 from Mott Crate PS 794
TranslatorCH1-CH16 from PEPPo
Crate PS 794 Translator *
1 – 16 1 – 1617 BFM18 Mott DetTr19 PEPPo DetTr
MJL
7
Gate11
2
nT_Settle Mott LT3 Ch16
PEPPo NIM Crate
Translator PS 794
Lin Fan In/Out 740 * 4 3 2 1
Lin Fan In/Out 740 * 4 3 2 1
Lin Fan In/Out 740 * 4 3 2 1
Logic Fan In/Out 4 3 2 1LeCroy 429A
Gate Delayer 4 3 2 1PS 794 *
Pulse Generator
Divider Pulse Generator
LV Board
PMT Bases
+ 12V
Frequency FrequencyDivider
Synch
LED
A1
A3
P1
P2
P3
P4
P5
P6
P7
P8
P9
PMTs, A1 &A3 => PEPPo FADC mode 1,2 VME CratePMTs => PEPPo FADC mode 3 VME Crate
JLab Discrim VME Crate <= PMTs, A1 & A3
TTL
NIM 1
NIM 2
ECL
S2 Translator PS 794 Mott CratePEPPo FADC mode 1,2Translator PS 794 Mott Crate
S1Discrim. CAEN v895 PEPPo Crate
L1A from CAEN V538AMJL from CAEN Discrim
Translator PS 794 Mott Crate
DB1 VME Crate TRG IN (delayed by 2.0 µs )
Mott NIM Crate
BAD VtoF1 MHz0–10 V
LT1726
VtoF2 MHz
-7 – +7 V
LT2726
LT3726
LIN740
DISC708
QD794
FAN429A
VtoF1 MHz0–10 V
→ BPMCh1-16
← S1Ch17-32
→ BFM-140 mV ← Ch8 FADC
← DISC
→ BMF-145 MV← LT3 Ch7
→ nT_Settle
← 0.4 µs nT_Settle Trigger
→ Delayed Helicity
→ BCM 0L02 Output2
← VtoF LT3 Ch8
→ nT_Settle
← 0.2 µs S1 LNE
→ T_Settle
→ 4 MHzClock
← 121.2 kHz ClockLT1 Ch4
→ Pattern Sync
11 Battery
12 Coil2
→ Mott Trigger
← 0.3 µsLT3 Ch9
→ Pair Sync
13 Coil3
14 Coil4
15 MPA5D05
Mott NIM – LEVEL TRANSLATOR 726
LT1
NIM IN ECL OUT NIM OUT NIM OUT
1 VtoF
S1Ch1-16
2 Scintillator (TS1)/A1
3 Mott DetTr 50 Ω S2 Ch3
4 121.2 kHz Clock 50 Ω S2 Ch4
5 PEPPo DetTr 50 Ω S2 Ch5
6 LA1 50 Ω S2 Ch6
7 Battery
8 PMT1
9 PMT2
10 PMT3
11 PMT4
12 PMT5
13 PMT6
14 PMT7
15 PMT8
16 PMT9
Mott NIM – LEVEL TRANSLATOR 726
LT2
NIM/ECL IN ECL OUT NIM OUT NIM OUT
1 NIM Delayed Helicity 50 Ω FADC2 Ch10
2
3
4 ECL Battery LT1 Ch7 S2 Ch7
5 ECL Coil2 50 Ω S2 Ch17
6 ECL Coil3 50 Ω S2 Ch18
7 ECL Coil4 50 Ω S2 Ch19
8 ECL MPA5D05 50 Ω S2 Ch20
9 NIM PEPPo DetTr TDC Ch19
10
11
12
13
14
15
16
Mott NIM – LEVEL TRANSLATOR 726
LT3
NIM IN TTL/ECL OUT NIM OUT NIM OUT
1 Delayed Helicity LT2 Ch1 Mott FADC Ch12 PEPPo FADC Ch12
2
3 T_Settle Mott FADC Ch13 PEPPo FADC Ch13
4 Pattern Sync Mott FADC Ch14 PEPPo FADC Ch14
5 Pair Sync Mott FADC Ch15 S2 Ch6
6
7 BFM TDC Ch17
8 VtoF LT1 Ch1 S2 Ch1
9 Delayed Mott DetTr TDC Ch18
10 Mott DetTr CAEN V538A Ch1
11 Mott FADC Ch10
12
13 LT1 Ch3 QUAD DELAY CH3
14
15 nT_Settle S1 GATE – Ch4 PEPPo FADC TRG IN
16 nT_Settle QUAD DELAY CH1 QUAD DELAY CH2
Mott NIM – QUAD FAN IN/OUT 429A
QUAD FAN IN/OUT
Delayed Helicity – IN
S1 Control – Ch2 OUT2 – old Mott DAQ OUT1 – old Mott DAQ
S2– Ch13 LT3 – CH1
T_Settle – IN
S2– Ch14 LT3 – Ch15 FADC2 – Ch12
CAEN V538A – Ch6 LT3 – Ch16 LT3 – Ch3
Pattern Sync – IN
S1 Control – Ch3 S2 – Ch15 FADC2 – Ch13
LT3 – Ch4
Pair Sync – IN
S2 – Ch16 FADC2 – Ch14
LT3 – Ch5
CHANNEL ASSIGNMENT – CAEN V538A LEVEL TRANSLATOR
Chan IN LEMO
7
6
5
4
3
2 PEPPo DetTr
1 Mott DetTr
0 Delayed (0.4 µs) nT_Settle
Chan IN ECL
7
6
5
4
3 TID OUT TRG (L1A)
2
1
0
Chan OUT ECL
7
6
5
4
3
2 TID TS#2
1 TID TS#1
0 TID IN TRG
Chan OUT LEMO
7
6
5
4
3 LA1 (PEPPo NIM) LA1 (TDC COMM)
2
1
0
CHANNEL ASSIGNMENT – TRIGGER INTERFACE (TID)
TID Chan IN Signal
7
6
5
4
3
2 TS#2 (PEPPo DetTr)
1 TS#1 (Mott DetTr)
0 TRG (nT_Settle)
TID Chan OUT Signal
7
6
5
4
3
2
1 TRG (L1A)
0
CONTROL CHANNEL ASSIGNMENT – GATED SCALER S1
S1 CONTROL Chan
Signal
1 Load-Next-Event (LNE)
2 Delayed Helicity
3 Pattern Sync
4 GATE (nT_Settle)
nT_Settle
Delayed TID nT_Settle
Trigger(Scalers and PEPPo_Int)
nT_Settle Trigger Setup:I. nT_Settle Trigger is delayed by 0.4 µsII. LNE is delayed by 0.2 µs
nT_Settle
LNE
Beat Frequency Modulation (BFM)
BFM
BFM after-140 mV offset
BFM after-145 mV discrimination (TDC)
BFM in FADC
Name Included Modules Data Storage Trigger
Scalers Scaler S1 (helicity gated), S2 (ungated)
/data/mott/Scalers_%d.dat Delayed nT_Settle
Mott_Sample Mott FADC, S1, S2, TDC /data/mott/Mott_Sample_%d.dat Mott Detector
Mott_SemiInt Mott FADC, S1, S2, TDC /data/mott/Mott_SemiInt_%d.dat Mott Detector
Annih_Sample PEPPo FADC, S1, S2, TDC, CAEN VME Discriminator
/data/annihilation/Annihilation_Sample_%d.dat Annihilation Detector
PEPPo_Sample PEPPo FADC, S1, S2, TDC, 2 VME Discriminators
/data/compton/PEPPo_Sample_%d.dat Compton Detector
PEPPo_Semi PEPPo FADC, S1, S2, TDC, 2 VME Discriminators
/data/compton/PEPPo_SemiInt_%d.dat Compton Detector
PEPPo_Int PEPPo FADC, S1, S2 /data/compton/PEPPo_Int_%d.dat Delayed nT_Settle
Data Taking Modes
HARDWARE OWNERSHIP# Crate DAQ Component Ownership Users (Mott or
PEPPo)Comment
1 CAEN VME Crate Hall A M&P Rack IN02B23
1 VME MVME 6100 CIS M&P iocmdaq1
1 VME CAEN V538A Level Translator Hall A M&P
1 VME Trigger Interface Distribution Board (TID) CIS M&P
3 VME 12-bit ADC CIS 1M + 2P
2 VME FADC Distribution Board CIS M&P
2 VME SIS3801 Scaler CIS M&P
1 VME CAEN V895 Discriminator LPSC P
1 VME CAEN V775 TDC LPSC M&P
1 VME 40 MHz Clock Hall A M&P
1 VME JLab Discriminator Electronic Group P
1 NIM VtoF (10 V) Hall A M&P
1 NIM VtoF (+/-7 V) CIS M&P
1 NIM VtoF (single Chan) CIS M&P
1 NIM DISCRIMINATOR 708 CIS M
4 NIM LINEAR FAN IN/OUT 740 CIS +Hall C (3P) 1M + 3P
2 NIM QUAD DELAY 794 CIS 1M + 1P
4 NIM LEVEL TRANSLATOR 726 CIS 3M + 1P
2 NIM LOGIC FAN IN/OUT 429A CIS 1M & 1P
2 NIM Pulsar LPSC 2P
1 NIM Divider LPSC 1P
1 NIM LV Supply Board LPSC 1P
1 NIM Octal Login Unit 758 CIS 1P
Spare Boards
# Crate DAQ Component Ownership Comment1 VME Trigger Interface Distribution Board (TID) CIS Old TI
1 NIM Logic Fan In/Out 4282 LPSC
1 NIM Linear Fan In/Out 428F Hall A
1 NIM LeCroy Multichannel Analyzer CIS
2 NIM Octal Logic Unit 758 CIS