cvd deposited low k dielectrics for gap-fill applications....sunrivalled gap fill performance –...
TRANSCRIPT
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1CONFIDENTIAL
John Macneil
Trikon Technologies, Inc.
CVD deposited low k dielectrics for gap-fill applications.
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2 CONFIDENTIAL
Contents
Application requirements.Low k Flowfill deposition processFilm PropertiesApplications
PMDIMD
ExtendibilitySummary
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3 CONFIDENTIAL
Application requirements.
gap fill (8:1); temperature (~1000oC), capacitance (?)
Flowfill / Low k Flowfill
STI
gap fill (3-4:1); capacitance (k ~2.5-2.8), temperature ((<500oC);
Low k FlowfillIMD
gap fill (10:1); temperature (NiSi) (<400oC); capacitance (k~ 3-3.5)
Low k FlowfillPMD
DriversProcess
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4CONFIDENTIAL
Low K Flowfill® Process Overview
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5 CONFIDENTIAL
Low K Flowfill Chamber Schematic
Pumping
Wafer
Duplex Showerhead
SiH3(CH3)H2O2
Cooled Platen@ 0°C
Direct CVD – no plasma enhancement
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6 CONFIDENTIAL
M
OH
SiH
Low-k Flowfill® Chemistry Formation of “liquid” methyl doped-silicic acid
SiM
+ OO
H
HH
H
H
M
OH
SiH
H
O
Surface Reaction
H
M
OH
Si
H
OH
O
M = CH3
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7 CONFIDENTIAL
Low-k Flowfill® Chemistry Polymerisation via condensation reactions
M
OH
Si
H
OH
O
M
OSi
OH
O
M
OSi
HO
H
H
M-SiO -OH
-OH
-OH
-OH
-OH
HO-
HO-
HO-
HO-
HO
-
HO-
M-SiO -OH
-OH
-OH-O
H
-OH
HO-
HO-
HO-
HO-H
O-
HO-
M-SiO -OH
-OH
-OH
-OH
-OH
HO-
HO-
HO-
HO-
HO
-
HO-
M-SiO -OH
-OH
-OH
-OH
-OH
HO-
HO-
HO-
HO-
HO
-
HO-
M
OH
Si
H
OH
O
M
OH
Si
H
OH
O
HHO
HHO
HHO
HHO
HHO
HHO
HSi
MO
Si
HO
M
Si
SiH
H
H
O
O
O O O
M
M
M M
M
SiO
OSi
O OSiO
M
SiOH
OH
H
O
OH
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8 CONFIDENTIAL
Process Flow
Low K Flowfill®CVD Gap-fill
In-situ plasmaCure
Oxide BasePECVD
- Moisture barrier
Oxide CapPECVD – CMP stop
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9CONFIDENTIAL
Film Properties
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10 CONFIDENTIAL
1.0
2.0
3.0
4.0
5.0
0 5 10 15 20 25
Carbon Content (At.%)
Die
lect
ric C
onst
ant
Generic carbon-doped oxideIncorporation of methyl groups
Chemical composition & K Value
K value tuneable: 2.8<K<3.3
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11 CONFIDENTIAL
Thermal stability
Investigation of low-k carbon fraction prior to and post anneal in inert atmosphere (1000°C, 30 min, N2) using depth-profiled-AES.
**Klipp et al; Infineon Technologies, AMC 2004
Generically – carbon doped oxideSusceptible to damage during anneal in oxidising ambients
Carbon loss
However…….Stable to >1000°C in inert ambients
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12 CONFIDENTIAL
Moisture Resistance
Uncapped low k FlowfillMinimal moisture absorption –
1week 85% RH; 85 °C
FTIR spectra before & after moisture / temperature stress
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13 CONFIDENTIAL
Hardness and Elastic Modulus
H>3GPa
Hardness vs Displacement Into Surface
0
1
2
3
4
5
6
0 100 200 300 400 500 600 700
Displacement Into Surface (nm)
Har
dnes
s (G
Pa)
Modulus vs Displacement Into Surface
05
101520253035404550
0 100 200 300 400 500 600 700
Displacement Into Surface (nm)
Mod
ulus
(GPa
)
E>15GPa
Mechanically robust film eases integration
H&E vs indent depth for low k Flowfill (k~2.8)
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14 CONFIDENTIAL
Planarisation
Planarising capability reduces lessens CMP burden
Surface Tension ⇒ Planarisation
Gap-fill occurs from the bottom-up
Degree of Planarisation for the Intermetal Dielectric (IMD) using FlowfillCVD Oxide
0
10
20
30
40
50
60
70
80
90
100
0.00 1.00 2.00 3.00 4.00 5.00 6.00 7.00 8.00 9.00 10.00
Distance between Al lines [um]
Deg
ree
of P
lana
risat
ion
p[%
]
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15 CONFIDENTIAL
300mm Gap-fill & PlanarisationDRAM Interconnect Structure
Wafer Centre
SEMs decorated to show cap interface
PECVD Cap OxideLow-k Flowfill
Wafer Edge
0.25µm min line/space
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16CONFIDENTIAL
Pre-Metal Dielectric
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17 CONFIDENTIAL
Pre-metal dielectric
Traditional HDP / doped silica processes strugglingVoidingPlasma damage & high stressTemperature too high for NiSi and metal gates
PMD needsUniform fill of deep structures(DRAM, PMD AR 16:1 by 2005)Low-k to reduce capacitance(DRAM, Keff 2.7 to 3.1 by 2010)Temp <450°C to protect NiSiZero damage of gate dielectricsSilicide moving to Ni
STI
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18 CONFIDENTIAL
Pre-Metal Dielectric – Gap Fill
Flowfill and low k Flowfill both have the gap-filling capability needed for PMD.
(a) Space 0.02㎛, AR>10:1(vertical pattern) (b) Space 0.09㎛,AR 8.6:1(negative sloped pattern)
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19 CONFIDENTIAL
PMD - Low Temperature Compatibility
Flowfill® is deposited cold without a plasmaBase films may not be required reducing chances of plasma damage and poly clipping c.f HDP
Cure temperature ~400°CReduces thermal budgets at PMD
Compatible with new silicide materials e.g NiSiLow k Flowfill preferable to standard Flowfill
Duplex Showerhead
SiH4 or SiH3(CH3)H2O2
Cooled Platen@ 0°C
Wafer
SiH4 for std Flowfill or SiH3(CH3) for low-k Flowfill
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20 CONFIDENTIAL
PMD Electricals – standard Flowfill
GMmax(Maximum Transconductance).
Degradation of Gmmax in NMOS as a function of hot carrier stress time. (W/L=10/0.3um VG=1.38V, VD=3.25V)
Flowfill
Flowfill
Variation of threshold voltage in PMOS after BT stress (W/L=10/0.4um VG=-6.5V, 200OC, 10min)
Flowfill
Leakage current between bit line and top electrode
Transistor reliability and hot carrier hardness comparable to BPSG
Park et al, Hyundai Electronics, VMIC 98
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21CONFIDENTIAL
Inter-Metal Dielectric
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22 CONFIDENTIAL
Inter-Metal Dielectric (IMD)
Most DRAM manufacturers will continue to use Al interconnect in short/medium term
CostLess complex metal routing
Shorter lines, lower resistance
Dielectrics with gap fill capability needed for IMDLow K beneficial in high performance devices
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23 CONFIDENTIAL
Integration at 0.18µmk~3.0
W
Al/Cu
Low k Flowfill
CVD
Sacrificialoxide
Hsia et al ICAMP 99
κ=2.8 κ=3.3 HDPκ=4.2 20 - 36% Inter-line
Capacitance Improvement
Via Chain Resistance vs Std k HDP
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24 CONFIDENTIAL
Integration at 130nm
Embedded SOD low-k sensitive to plasma damage during etch / strip
Absorb moisture Out-gass during W dep giving poisoned via / W void
Low k Flowfill® compatible with zero-overlay designsNo poisoned via even for 30% off-set at 130nm
Low-k Flowfill® (k=2.8)
Compatible with Zero Overlay
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25 CONFIDENTIAL
Electrical Performance – DRAM
Low-k Flowfill - 29% Capacitance Reduction c.f HDP
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26CONFIDENTIAL
Extendibility
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27 CONFIDENTIAL
Developmental gap fill process
Objectives:K value reduction c.f. low k Flowfill
k ≤2.5DRAM IMDPMD
Reduction of µ-porosity in high aspect ratio featuresEasier integration
PMDSTI
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28 CONFIDENTIAL
Trench Material – TEM of Standard Flowfill
Behaviour similar for low k FlowfillEvidence of porosity in narrow trenchNarrow trench will have higher wet etch rate
K value is reduced in small features due to low density region.
Base/Liner
Flowfill
PECVD CAP
Lowest Density region in Flowfill
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29 CONFIDENTIAL
Wet etch rate within trenches
10:1 HF etching after sample cleave (30 secs)Flowfill shows clear evidence of low density fill in metal & Si trenchesDevelopmental process shows no evidence of low density in gaps
Flowfill
New Process
Metal trench Metal trench Si trench
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30 CONFIDENTIAL
Current Density vs Electric Field
Tested using Al dot MIS capacitance on low resistivity Si wafer.Film thickness: ~500nmMaximum supply voltage: 200VTrikon unable to determine true Vbd due to film thickness and max voltage limitation
Can only say that Vbd > 4MVcm-1
1.00E-12
1.00E-10
1.00E-08
1.00E-06
1.00E-04
1.00E-02
1.00E+000 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Electric field (MVcm-1)
Cur
rent
den
sity
(Acm
-2)
J1J2J3
Max electric field available ~4MVcm-1
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31 CONFIDENTIAL
Developmental gap fill process - film properties
Film Property Low k Flowfill new low k gap fill MethodDielectric Constant ~2.9 ~2.5 Al dot MIS capacitorNon-uniformity (200mm wafer 1σ) 4.50% 3.04% OptiprobeDeposition Rate (nm/min) 340 600 OptiprobeRefractive Index 1.415 1.342 OptiprobeStress (MPa) <50 <20 wafer bowWet Etch Rate in 10:1 BHF (nm/min) 580 679 wafer pieceHardness GPa (20% indent depth) 3.1 0.57 Nano-indentation Modulus GPa (20% indent depth) 22.1 3.92 Nano-indentation SiC:SiO ratio 0.005 0.0199 FTIRSiH:SiO ratio 0.011 0.0195 FTIRCH:SiO ratio 0.009 0.0324 FTIRSi at% 23.2 20.5 RBSO at% 38.3 31 RBSC at% 11.5 14.5 NRAH at% 27 34 ERDAVBD (MVcm-1) >8 >4 Al dot MIS capacitorLeakage (Acm-2 @ 1MVcm-1) ~1E-10 ~1E-9 Al dot MIS capacitor
RBS: Rutherford Back-Scattering; NRA: Nuclear Reaction Analysis; ERDA: Elastic Recoil Detection Analysis
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32 CONFIDENTIAL
New Flowable oxides
Scope to reduce porosity/low density regions in HAR features by modifying chemistry before it reaches wafer surface.As-deposited viscosity is low enough to provide fill.K values to <2.5 are possible.
Thermal stability (<650oC)is likely to be only sufficient to be of use for IMD/PMD applications.
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33 CONFIDENTIAL
Summary
Low k Flowfill CVD technology Unrivalled gap fill performance – PMD & IMDLow k – PMD & IMDLow temperature – PMD & IMD
Compatible with NiSi
There is a continuing need for low k materials with gap fill capabilityPMD and DRAM IMD applications will drive this need for several technology generations to come
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34 CONFIDENTIAL
Selected References
PMD / IMD1. Integration of high gapfill, standard and low k, contact level dielectric
materials for the 90nm mode and beyond. Spencer et al; FreescaleSemiconductor, AMC 2004
2. New integration fields for gap filling low k dielectrics in DRAM – The way from BEOL to MOL to FEOL. Klipp et al; Infineon Technologies, AMC 2004
3. Pre-Metal Dielectric Applications of Low Temperature SPO(Self-Planarization Oxide) By Using SiH4+H2O2 CVD For 0.13㎛Technology and Beyond. Park et al; Hyundai Electronics (Hynix), VMIC 1998
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35 CONFIDENTIAL
PMD Electricals – standard Flowfill
Flowfill
Flowfill
Capacitance of Ta2O5 capacitors for HDP and Flowfill Leakage current of Ta2O5 capacitors for HDP and Flowfill
Superior leakage current and data distribution variance of Ta2O5 capacitor c.f HDP.
Attributed to absence of plasma in Flowfill process
1Gbit DRAM Ta2O5 capacitor
Park et al, Hyundai Electronics, VMIC 98