cse140: components and design techniques for digital · pdf filecse140: components and design...

Sources: TSR, Katz, Boriello & Vahid

1

CSE140: Components and Design Techniques

for Digital Systems

Tajana Simunic Rosing


2

Where we are now…

• What we covered thus far: – Number representations

– Logic gates

– Boolean algebra

– Introduction to CMOS

• HW#2 due, HW#3 assigned

• Where we are going: – Logic representations

– SOP and POS

– K-maps

– Algorithm for simplification


3

Combinational Circuit Introduction

Combinational

digital circuit

1 a

b

1 F 0

1 a

b

? F 0

• We’ll start with a simple form of circuit:

– Combinational circuit

• A digital circuit whose outputs depend solely on

the present combination of the circuit inputs’

values

• Built out of simple components: switches and

gates

Digital circuit

Sequential

digital circuit


4

Combinational Logic Design Process

Step Description

Step 1 Capture the

function

Create a truth table or equations to describe the

desired behavior of the combinational logic.

Step 2 Convert to

equations

This step is only necessary if you captured the

function using a truth table instead of equations.

Simplify the equations if desired.

Step 3 Implement

as a gate-

based

circuit

For each output, create a circuit corresponding

to the output’s equation.

2.7


5

Example: Three 1s Detector

• Problem: Detect 3 consecutive

1s in 8-bit input: abcdefgh • 00011101

• 01111000

• 10101011

– Step 1: Capture the function

• Truth table or equation?

– Step 2: Convert to equation

– Step 3: Implement with gates

bcd

def

fgh

abc

cde

efg

y

a b c

d

e

f

g

h

a


6

Example: Seat Belt Warning Light System

• Design circuit for warning light

• Sensors

– s=1: seat belt fastened

– k=1: key inserted

– p=1: person in seat

• Capture logic equation

– What are conditions for warning light to go on?

• Convert equation to circuit


7

Example: Number of 1s Count

• Problem: Output in binary on

two outputs yz the number of 1s

on three inputs • 010

• 101

• 000

– Step 1: Capture the function

• Truth table or equation?

– Step 2: Convert to equation

– Step 3: Implement as gates

a b c

a b c

a b c

a b c

z

a b c

a b c

a

b

y


8

Design example: 1-bit binary adder

• Inputs: A, B, Carry-in

• Outputs: Sum, Carry-out

A

B

Cin Cout

S A B Cin Cout S 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1

A A A A A

B B B B B

S S S S S

Cin Cout


9


for Digital Systems

Representation of logic functions



10

Canonical Form -- Sum of Minterms

• Truth tables are too big for numerous inputs

• Use standard form of equation instead

– Known as canonical form

– Regular algebra: group terms of polynomial by power

• ax2 + bx + c (3x2 + 4x + 2x2 + 3 + 1 --> 5x2 + 4x + 4)

– Boolean algebra: create a sum of minterms

• Minterm: product term with every literal (e.g. a or a’) appearing

exactly once

Determine if F(a,b)=ab+a’ is same function as F(a,b)=a’b’+a’b+ab, by

converting the first equation to the canonical form


11

A B C F F’ 0 0 0 0 1 0 0 1 1 0 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 0

F =

F’ = A’B’C’ + A’BC’ + AB’C’

Sum-of-products canonical forms

• Also known as disjunctive normal form

• Minterm expansion:

F = 001 011 101 110 111

+ A’BC + AB’C + ABC’ + ABC A’B’C


12

short-hand notation for

minterms of 3 variables

A B C minterms

0 0 0 A’B’C’ m0

0 0 1 A’B’C m1

0 1 0 A’BC’ m2

0 1 1 A’BC m3

1 0 0 AB’C’ m4

1 0 1 AB’C m5

1 1 0 ABC’ m6

1 1 1 ABC m7

F in canonical form:

F(A, B, C) = m(1,3,5,6,7)

= m1 + m3 + m5 + m6 + m7

= A’B’C + A’BC + AB’C + ABC’ + ABC

canonical form minimal form

F(A, B, C) = A’B’C + A’BC + AB’C + ABC + ABC’

= (A’B’ + A’B + AB’ + AB)C + ABC’

= ((A’ + A)(B’ + B))C + ABC’

= C + ABC’

= ABC’ + C

= AB + C

Sum-of-products canonical form (cont’d)

• Product minterm

– ANDed product of literals – input combination for which output is 1

– each variable appears exactly once, true or inverted (but not both)


13

A B C F F’ 0 0 0 0 1 0 0 1 1 0 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 0

F = 000 010 100

F =

F’ = (A + B + C’) (A + B’ + C’) (A’ + B + C’) (A’ + B’ + C) (A’ + B’ + C’)

Product-of-sums canonical form

• Also known as conjunctive normal form

• Also known as maxterm expansion

• Implements “zeros” of a function

(A + B + C) (A + B’ + C) (A’ + B + C)


14

A B C maxterms

0 0 0 A+B+C M0

0 0 1 A+B+C’ M1

0 1 0 A+B’+C M2

0 1 1 A+B’+C’ M3

1 0 0 A’+B+C M4

1 0 1 A’+B+C’ M5

1 1 0 A’+B’+C M6

1 1 1 A’+B’+C’ M7

short-hand notation for

maxterms of 3 variables

F in canonical form:

F(A, B, C) = M(0,2,4)

= M0 • M2 • M4

= (A + B + C) (A + B’ + C) (A’ + B + C)

canonical form minimal form

F(A, B, C) = (A + B + C) (A + B’ + C) (A’ + B + C)

= (A + B + C) (A + B’ + C)

(A + B + C) (A’ + B + C)

= (A + C) (B + C)

Product-of-sums canonical form (cont’d)

• Sum term (or maxterm)

– ORed sum of literals – input combination for which output is false

– each variable appears exactly once, true or inverted (but not both)


15

Mapping between canonical forms

• Minterm to maxterm conversion

– use maxterms whose indices do not appear in minterm expansion

– e.g., F(A,B,C) = m(1,3,5,6,7)

• Maxterm to minterm conversion

– use minterms whose indices do not appear in maxterm expansion

– e.g., F(A,B,C) = M(0,2,4)

• Minterm expansion of F to minterm expansion of F’

– use minterms whose indices do not appear

– e.g., F(A,B,C) = m(1,3,5,6,7) F’(A,B,C) =

• Maxterm expansion of F to maxterm expansion of F’

– use maxterms whose indices do not appear

– e.g., F(A,B,C) = M(0,2,4) F’(A,B,C) =

• Minterm to maxterm conversion

– use maxterms whose indices do not appear in minterm expansion

– e.g., F(A,B,C) = m(1,3,5,6,7) = M(0,2,4)

• Maxterm to minterm conversion

– use minterms whose indices do not appear in maxterm expansion

– e.g., F(A,B,C) = M(0,2,4) = m(1,3,5,6,7)

• Minterm expansion of F to minterm expansion of F’

– use minterms whose indices do not appear

– e.g., F(A,B,C) = m(1,3,5,6,7) F’(A,B,C) = m(0,2,4)

• Maxterm expansion of F to maxterm expansion of F’

– use maxterms whose indices do not appear

– e.g., F(A,B,C) = M(0,2,4) F’(A,B,C) = M(1,3,5,6,7)


16

A B C D W X Y Z 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 0 1 1 0 0 1 1 0 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 1 1 1 0 1 1 1 1 0 0 0 1 0 0 0 1 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 X X X X 1 0 1 1 X X X X 1 1 0 0 X X X X 1 1 0 1 X X X X 1 1 1 0 X X X X 1 1 1 1 X X X X

off-set of W

these inputs patterns should never be encountered in practice – "don’t care" about associated output values, can be exploited in minimization

Incompletely specified functions

• Example: binary coded decimal increment by 1

– BCD digits encode the decimal digits 0 – 9

don’t care (DC) set of W

on-set of W

• Don’t cares and canonical forms

– so far, only represented on-set

– also represent don’t-care-set

– need two of the three sets (on-set, off-set, dc-set)


17

canonical sum-of-products

minimized sum-of-products

canonical product-of-sums

minimized product-of-sums

F1

F2

F3

B

A

C

F4

Alternative two-level implementations of

F = AB + C


18


for Digital Systems

Logic simplification


Sources: Katz, Boriello & Vahid


19

A B F

0 0 1

0 1 0

1 0 1

1 1 0

B has the same value in both on-set rows

– B remains

A has a different value in the two rows

– A is eliminated

F = A’B’+AB’ = (A’+A)B’ = B’

Key to simplification: the uniting theorem

• Uniting theorem: A (B’ + B) = A

• Essence of simplification of two-level logic

– find two element subsets of the ON-set where only one variable

changes its value – this single varying variable can be eliminated

and a single product term used to represent both elements


20

1-cube X

0 1

Boolean cubes

• Visual technique for applying the uniting theorem

• n input variables = n-dimensional "cube"

2-cube

X

Y

11

00

01

10

3-cube

X

Y Z

000

111

101 4-cube

W

X

Y Z

0000

1111

1000

0111


21

A B F

0 0 1

0 1 0

1 0 1

1 1 0

ON-set = solid nodes

OFF-set = empty nodes

DC-set = 'd nodes

two faces of size 0 (nodes)

combine into a face of size 1(line)

A varies within face, B does not

this face represents the literal B'

Mapping truth tables onto Boolean cubes

• Uniting theorem combines two “faces" of a cube

into a larger “face"

• Example:

A

B

11

00

01

10

F


22

A B Cin Cout 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 1

(A'+A)BCin

AB(Cin'+Cin)

A(B+B')Cin

Cout = BCin+AB+ACin

the on-set is completely covered by the combination (OR) of the subcubes of lower dimensionality - note that “111” is covered three times

Three variable example

• Binary full-adder carry-out logic

A

B C

000

111

101


23

F(A,B,C) = m(4,5,6,7)

on-set forms a square - a cube of dimension 2

This subcube represents the literal A

Higher dimensional cubes

• Sub-cubes of higher dimension than 2

A

B C

000

111

101

100

001

010

011

110

• In a 3-cube (three variables):

– a 0-cube, i.e., a single node, yields a term in 3 literals

– a 1-cube, i.e., a line of two nodes, yields a term in 2 literals

– a 2-cube, i.e., a plane of four nodes, yields a term in 1 literal

– a 3-cube, i.e., a cube of eight nodes, yields a constant term "1"

• In general,

– an m-subcube within an n-cube (m < n) yields a term with n – m literals


24

A B F

0 0 1

0 1 0

1 0 1

1 1 0

Karnaugh maps

• Flat map of Boolean cube

– wrap–around at edges

– hard to draw and visualize for more than 4 dimensions

– virtually impossible for more than 6 dimensions

• Alternative to truth-tables to help visualize adjacencies

– guide to applying the uniting theorem

– on-set elements with only one variable changing value are

adjacent unlike the situation in a linear truth-table

0 2

1 3

0 1 A

B

0

1

1

0 0

1


25

Karnaugh maps (cont’d)

• Numbering scheme based on Gray–code

– e.g., 00, 01, 11, 10

– only a single bit changes in code for adjacent map cells

0 2

1 3

00 01 AB

C

0

1

6 4

7 5

11 10

C

B

A

0 2

1 3

6 4

7 5 C

B

A

0 4

1 5

12 8

13 9 D

A

3 7

2 6

15 11

14 10 C

B A

B C

000

111

101

100

001

010

011

110


26

Karnaugh map examples

• F =

• Cout =

• f(A,B,C) = m(0,4,5,7)

0 0

0 1

1 0

1 1 Cin

B

A

1 1

0 0 B

A

1 0

0 0

0 1

1 1 C

B

A

0 2

1 3

00 01 AB

C

0

1

6 4

7 5

11 10

C

B

A


27


for Digital Systems

Logic simplification cont.


Sources: Katz, Boriello & Vahid


• Total students enrolled : 151

• # Solutions received : 137

• Max score : 100.00

• Min score (w/o 0s) : 30.00

• Mean score : 86.03

• Median score : 89.00

CSE140a HW2 Stats buckets # students students (%)

0 ~ 5 14 9.27%

5 ~ 10 0 0.00%

10 ~ 15 0 0.00%

15 ~ 20 0 0.00%

20 ~ 25 0 0.00%

25 ~ 30 1 0.66%

30 ~ 35 0 0.00%

35 ~ 40 0 0.00%

40 ~ 45 0 0.00%

45 ~ 50 1 0.66%

50 ~ 55 3 1.99%

55 ~ 60 0 0.00%

60 ~ 65 4 2.65%

65 ~ 70 6 3.97%

70 ~ 75 11 7.28%

75 ~ 80 18 11.92%

80 ~ 85 11 7.28%

85 ~ 90 29 19.21%

90 ~ 95 11 7.28%

95 ~ 100 42 27.81%

0.0%

10.0%

20.0%

30.0%0

~ 5

5 ~

10

10 ~

15

15 ~

20

20 ~

25

25 ~

30

30 ~

35

35 ~

40

40 ~

45

45 ~

50

50 ~

55

55 ~

60

60 ~

65

65 ~

70

70 ~

75

75 ~

80

80 ~

85

85 ~

90

90 ~

95

95 ~

100

Stu

de

nts

(%

)

Bucket of Points

HW2 Grade Distribution


29

Where we are now…

• What we covered thus far: – Chap 1

– Logic representations

– SOP and POS

– K-maps

• HW#3 due, HW#4 assigned

• Midterm #1 next week on Th

• Where we are going: – K-maps – more examples

– Mux and Demux


30

find the smallest number of the largest possible subcubes to cover the ON-set

(fewer terms with fewer inputs per term)

Karnaugh map: 4-variable example

• F(A,B,C,D) = m(0,2,3,5,6,7,8,10,11,14,15)

F =

D

A

B

A

B

C D

0000

1111

1000

0111 1 0

0 1

0 1

0 0

1 1

1 1

1 1

1 1

C


31

Karnaugh maps: don’t cares

• f(A,B,C,D) = m(1,3,5,7,9) + d(6,12,13) without don't cares with don’t cares

f = f =

0 0

1 1

X 0

X 1 D

A

1 1

0 X

0 0

0 0

B

C

0 0

1 1

X 0

X 1 D

A

1 1

0 X

0 0

0 0

B

C

don't cares can be treated as 1s or 0s

depending on which is more advantageous


32

Another Example

• F = m(0, 2, 7, 8, 14, 15) + d(3, 6, 9, 12, 13)

1 0

0 0

X 1

X X

X 1

1 X

1 0

1 0

D

A

B

C


33

we'll need a 4-variable Karnaugh map for each of the 3 output functions

Design example: two-bit comparator

block diagram

LT

EQ

GT

A B < C D

A B = C D

A B > C D

A B

C D

N1

N2

A B C D LT EQ GT 0 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 0 0 1 0 0 0 0 1 0 1 0 1 0 1 0 1 0 0 1 1 1 0 0 1 0 0 0 0 0 1 0 1 0 0 1 1 0 0 1 0 1 1 1 0 0 1 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0

and truth table


34

A' B' D + A' C + B' C D

B C' D' + A C' + A B D'

LT =

EQ =

GT =

K-map for EQ K-map for LT K-map for GT

Design example: two-bit comparator (cont’d)

0 0

1 0

0 0

0 0 D

A

1 1

1 1

0 1

0 0

B

C

1 0

0 1

0 0

0 0 D

A

0 0

0 0

1 0

0 1

B

C

0 1

0 0

1 1

1 1 D

A

0 0

0 0

0 0

1 0

B

C

= (A xnor C) • (B xnor D)

LT and GT are similar (flip A/C and B/D)

A' B' C' D' + A' B C' D + A B C D + A B' C D’


35

block diagram and

truth table

4-variable K-map for each of the 4 output functions

A2 A1 B2 B1 P8 P4 P2 P1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 1 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 0 1 1 0 0 0 0 0 0 0 1 0 0 1 1 1 0 0 1 1 0 1 1 1 0 0 1

Design example: 2x2-bit multiplier

P1

P2

P4

P8

A1

A2

B1

B2


36

K-map for P8 K-map for P4

K-map for P2 K-map for P1

Design example: 2x2-bit multiplier (cont’d)

0 0

0 0

0 0

0 0 B1

A2

0 0

0 0

0 1

1 1

A1

B2

0 0

0 1

0 0

1 0 B1

A2

0 1

0 0

1 0

0 0

A1

B2

0 0

0 0

0 0

1 1 B1

A2

0 1

0 1

0 1

1 0

A1

B2

0 0

0 0

0 0

0 0 B1

A2

0 0

0 0

1 0

0 0

A1

B2


37

I8 I4 I2 I1 O8 O4 O2 O1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 0 1 1 0 0 1 1 0 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 1 1 1 0 1 1 1 1 0 0 0 1 0 0 0 1 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 X X X X 1 0 1 1 X X X X 1 1 0 0 X X X X 1 1 0 1 X X X X 1 1 1 0 X X X X 1 1 1 1 X X X X

block diagram and

truth table

4-variable K-map for each of the 4 output functions

O1

O2

O4

O8

I1

I2

I4

I8

Design example: BCD + 1


38

O8 O4

O2 O1

Design example: BCD + 1 (cont’d)

0 0

0 0

X 1

X 0 I1

I8

0 1

0 0

X X

X X

I4

I2

0 0

1 1

X 0

X 0 I1

I8

0 0

1 1

X X

X X

I4

I2

0 1

0 1

X 0

X 0 I1

I8

1 0

0 1

X X

X X

I4

I2

1 1

0 0

X 1

X 0 I1

I8

0 0

1 1

X X

X X

I4

I2


39


for Digital Systems

Muxes and demuxes



Contention: X

A = 1

Y = X

B = 0

• Contention: circuit tries to drive output to 1 and 0 – Actual value somewhere in between

– Could be 0, 1, or in forbidden zone

– Might change with voltage, temperature, time, noise

– Often causes excessive power dissipation

• Warnings: – Contention usually indicates a bug.

– X is used for “don’t care” and contention - look at the context to tell them apart


Transmission Gate:

Mux/Tristate building block

A B

EN

EN

• nMOS pass 1’s poorly

• pMOS pass 0’s poorly

• Transmission gate is a better switch

– passes both 0 and 1 well

• When EN = 1, the switch is ON:

– EN = 0 and A is connected to B

• When EN = 0, the switch is OFF:

– A is not connected to B


Floating: Z

E A Y0 0 Z

0 1 Z

1 0 0

1 1 1

A

E

Y

• Floating, high impedance, open, high Z

• Floating output might be 0, 1, or somewhere in

between

– A voltmeter won’t indicate whether a node is

floating

Tristate Buffer


Tristate Busses

en1

to bus

from bus

en2

to bus

from bus

en3

to bus

from bus

en4

to bus

from bus

sh

are

d b

us

processor

video

Ethernet

memory

• Floating nodes are used in tristate busses

– many different drivers, but only one is active at once


2:1 Multiplexer or Mux

• Selects between one of N inputs to connect to output

• log2N-bit select input – control input

• Example: 2:1 Mux

Y

0 0

0 1

1 0

1 1

0

1

0

1

0

0

0

0

0 0

0 1

1 0

1 1

1

1

1

1

0

0

1

1

0

1

S

D0

YD

1

D1

D0

S Y

0

1 D1

D0

S

D1

Y

D0

S

S00 01

0

1

Y

11 10

D0

D1

0

0

0

1

1

1

1

0

Y = D0S + D

1S

Y

D0

S

D1

Logic gates Tristates Pass gates


45

2 -1 I0 I1 I2 I3 I4 I5 I6 I7

A B C

8:1 mux

Z

I0 I1 I2 I3

A B

4:1 mux

Z I0 I1

A

2:1 mux

Z

k=0

n

Multiplexers

• 2:1 mux: Z = A'I0 + AI1

• 4:1 mux: Z = A'B'I0 + A'BI1 + AB'I2 + ABI3

• 8:1 mux: Z = A'B'C'I0 + A'B'CI1 + A'BC'I2 + A'BCI3 +

AB'C'I4 + AB'CI5 + ABC'I6 + ABCI7

• In general: Z = (mkIk)

– in minterm shorthand form for a 2n:1 Mux


A B Y0 0 0

0 1 0

1 0 0

1 1 1

Y = AB

00

Y01

10

11

A B

• Using the mux as a lookup table

Logic using Multiplexers


A B Y0 0 0

0 1 0

1 0 0

1 1 1

Y = AB

A Y

0

1

0 0

1

A

BY

B

• Reducing the size of the mux

Logic using Multiplexers


48

C0 C1 C2 Function Comments

0 0 0 1 always 1

0 0 1 A + B logical OR

0 1 0 (A • B)' logical NAND

0 1 1 A xor B logical xor

1 0 0 A xnor B logical xnor

1 0 1 A • B logical AND

1 1 0 (A + B)' logical NOR

1 1 1 0 always 0

Mux example: Logical function unit

C2 C0 C1

0

1

2

3

4

5

6

7 S2

8:1 MUX

S1 S0

F


49

Mux as general-purpose logic

• A 2n-1:1 multiplexer can implement any function of n variables

– with n-1 variables used as control inputs and

– the data inputs tied to the last variable or its complement

• Example: F(A,B,C) = AC + BC' + A'B‘C


2:4

Decoder

A1

A0

Y3

Y2

Y1

Y0

00011011

0 0

0 1

1 0

1 1

0

0

0

1

Y3

Y2

Y1

Y0

A0

A1

0

0

1

0

0

1

0

0

1

0

0

0

• N inputs, 2N outputs

• One-hot outputs: only one output HIGH at once

Demux or Decoder


51

1:2 Decoder: O0 = G S’ O1 = G S

2:4 Decoder: O0 = G S1’ S0’ O1 = G S1’ S0 O2 = G S1 S0’ O3 = G S1 S0

3:8 Decoder: O0 = G S2’ S1’ S0’ O1 = G S2’ S1’ S0 O2 = G S2’ S1 S0’ O3 = G S2’ S1 S0 O4 = G S2 S1’ S0’ O5 = G S2 S1’ S0 O6 = G S2 S1 S0’ O7 = G S2 S1 S0

Decoder: logic equations

• Decoders/demultiplexers

– control inputs (called “selects” (S)) represent binary index of

output to which the input is connected

– data input usually called “enable” (G)


Y3

Y2

Y1

Y0

A0A1

Decoder Implementation


2:4

Decoder

A

B00011011

Y = AB + AB

Y

ABABABAB

Minterm

= A B

• OR minterms

Logic Using Decoders

A'B'C' A'B'C A'BC' A'BC AB'C' AB'C ABC' ABC

C A B

0 1 2 3 4 5 6 7

S2

3:8 DEC

S1 S0

“1”


54

Example of demux as general-purpose logic

F1 = A'BC'D + A'B'CD + ABCD

F2 = ABC'D' + ABC

F3 = (A' + B' + C' + D')

A B

0 A'B'C'D' 1 A'B'C'D 2 A'B'CD' 3 A'B'CD 4 A'BC'D' 5 A'BC'D 6 A'BCD' 7 A'BCD 8 AB'C'D' 9 AB'C'D 10 AB'CD' 11 AB'CD 12 ABC'D' 13 ABC'D 14 ABCD' 15 ABCD

4:16 DEC Enable

C D


55

Another example

• F(A,B,C) = M(0,2,4)


56


for Digital Systems

Timing and hazards



A

Y

Time

delay

A Y

• Delay between input change and output changing

• How to build fast circuits?

Timing


A

Y

Time

A Y

tpd

tcd

• Propagation delay: tpd = max delay from input to output

• Contamination delay: tcd = min delay from input to output

Propagation & Contamination Delay


• Delay is caused by

– Capacitance and resistance in a circuit

– Speed of light limitation

• Reasons why tpd and tcd may be different:

– Different rising and falling delays

– Multiple inputs and outputs, some of which are faster

than others

– Circuits slow down when hot and speed up when cold

Propagation & Contamination Delay


AB

C

D Y

Critical Path

Short Path

n1

n2

Critical (Long) Path: tpd = 2tpd_AND + tpd_OR

Short Path: tcd = tcd_AND

Critical (Long) & Short Paths


AB

C

Y

00 01

1

Y

11 10AB

1

1

0

1

0

1

0

0

C

0

Y = AB + BC

• Glitch occurs when an input change causes multiple output changes;

circuit with a potential for a glitch has a hazard

• There are 3 types of hazards:

• Static-0 : output should be 0 but has a 1 glitch

• Static-1 : output should be 1 but has a 0 glitch

• Dynamic: transition 0->1 or 1->0 with a glitch

• Example:

Glitches or Hazards

A = 0B = 1 0

C = 1

Y = 1 0 1

Short Path

Critical Path

B

Y

Time

1 0

0 1

glitch

n1

n2

n2

n1

What happens if

A = 0, C = 1, &

B falls?


00 01

1

Y

11 10AB

1

1

0

1

0

1

0

0

C

0

Y = AB + BC + ACAC

B = 1 0Y = 1

A = 0

C = 1

Fixing a hazard


63

Another example

• F(A,B,C,D)=m(1,3,5,7,8,9,12,13)

• Test two single bit input transitions:

– 1100 -> 1101

– 1100 -> 0101

A C’

D

Z

D

0 0

1 1

1 1

1 1

A

1 1

0 0

0 0

0 0

B

C


64


for Digital Systems

Two and Multilevel logic implementation



A0

A1

PRIORITY

CiIRCUIT

A2

A3

Y0

Y1

Y2

Y3

• Output asserted corresponds to the most significant TRUE input

Multiple-Output Circuits: Priority Circuit

A1

A0

0 00 11 01 1

0000

Y3Y2

Y1

Y0

0000

0011

0100

A3

A2

0 00 00 00 0

0 0 0 1 0 00 10 11 01 10 0

0 10 10 11 0

0 11 01 01 10 00 1

1 01 01 11 1

1 01 11 11 1

0001

1110

0000

0000

1 0 0 01111

0000

0000

0000

1 0 0 01 0 0 0

A1

A0

0 00 11 XX X

0000

Y3Y2

Y1

Y0

0001

0010

0100

A3

A2

0 00 00 00 1

X X 1 0 0 01 X

A3A

2A

1A

0

Y3

Y2

Y1

Y0


66

Multiple-Output Circuits

• Many circuits have more than one output

• Can give each a separate circuit, or can share gates

• Ex: F = ab + c’, G = ab + bc

Option 1: Separate circuits Option 2: Shared gates


A B C D E F G

X

Multi-level logic

• x = A D F + A E F + B D F + B E F + C D F + C E F + G

– reduced sum-of-products form – already simplified

– 6 x 3-input AND gates + 1 x 7-input OR gate (that may not even exist!)

– 25 wires (19 literals plus 6 internal wires)

• x = (A + B + C) (D + E) F + G

– factored form – not written as two-level S-o-P

– 1 x 3-input OR gate, 2 x 2-input OR gates, 1 x 3-input AND gate

– 10 wires (7 literals plus 3 internal wires)


68

Multiple-Output Example: BCD to 7-Segment Converter

a = w’x’y’z’ + w’x’yz’ + w’x’yz + w’xy’z +

w’xyz’ + w’xyz + wx’y’z’ + wx’y’z

abcdefg = 1111110 0110000 1101101

af

b

d

ge

c

(b)(a)

b = w’x’y’z’ + w’x’y’z + w’x’yz’ + w’x’yz +

w’xy’z’ + w’xyz + wx’y’z’ + wx’y’z

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