cs 61c: great ideas in computer architecture introduction to …cs61c/sp18/lec/05/lec05.pdf ·...
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CS61C:GreatIdeasinComputerArchitecture
IntroductiontoAssemblyLanguageandRISC-VInstructionSetArchitecture
Instructors:NickWeaver&JohnWawrzynek
http://inst.eecs.Berkeley.edu/~cs61c
1/30/18 Spring2018-Lecture#5 1
Outline• AssemblyLanguage• RISC-VArchitecture• Registersvs.Variables• RISC-VInstructions• C-to-RISC-VPatterns• AndinConclusion…
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Outline• AssemblyLanguage• RISC-VArchitecture• Registersvs.Variables• RISC-VInstructions• C-to-RISC-VPatterns• AndinConclusion…
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LevelsofRepresentation/Interpretation
lw $t0,0($2)lw $t1,4($2)sw $t1,0($2)sw $t0,4($2)
HighLevelLanguageProgram(e.g.,C)
AssemblyLanguageProgram(e.g.,RISC-V)
MachineLanguageProgram(RISC-V)
HardwareArchitectureDescription(e.g.,blockdiagrams)
Compiler
Assembler
MachineInterpretation
temp=v[k];v[k]=v[k+1];v[k+1]=temp;
0000 1001 1100 0110 1010 1111 0101 1000 1010 1111 0101 1000 0000 1001 1100 0110 1100 0110 1010 1111 0101 1000 0000 1001 0101 1000 0000 1001 1100 0110 1010 1111
ArchitectureImplementation
Anythingcanberepresented asanumber,
i.e.,dataorinstructions
LogicCircuitDescription(CircuitSchematicDiagrams) 4
InstructionSetArchitecture(ISA)• JobofaCPU(CentralProcessingUnit,akaCore):executeinstructions• Instructions:CPU’sprimitivesoperations
– Instructionsperformedoneafteranotherinsequence– Eachinstructiondoesasmallamountofwork(atinypartofalargerprogram).– Eachinstructionhasanoperationappliedtooperands,– andmightbeusedchangethesequenceofinstruction.
• CPUsbelongto“families,”eachimplementingitsownsetofinstructions
• CPU’sparticularsetofinstructionsimplementsanInstructionSetArchitecture(ISA)– Examples:ARM,Intelx86,MIPS,RISC-V,IBM/MotorolaPowerPC(oldMac),
IntelIA64,...5
InstructionSetArchitectures• Earlytrend:addmoreinstructionstonewCPUsforelaborateoperations– Madeassemblylanguageprogrammingeasier.– VAXarchitecturehadaninstructiontocomputepolynomials!
result = C[0]+x**0 + x*(C[1] + x*(C[2] + ... x*C[d])) • RISCphilosophy(CockeIBM,PattersonUCB,HennessyStanford,1980s)–ReducedInstructionSetComputing– Keeptheinstructionsetsmallandsimple,inordertobuildfasthardware
– Letcompilergeneratesoftwaredocomplicatedoperationsbycomposingsimplerones
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AssemblyLanguageProgramming• EachassemblylanguageistiedtoaparticularISA(itsjustahumanreadableversionofmachinelanguage).
• Whyprograminassemblylanguageversusahigh-levellanguage?• Backintheday,whenISAswherecomplexandcompilerswhereimmature….handoptimizedassemblycodecouldbeatwhatthecompilercouldgenerate.
• ThesedaysISAsaresimpleandcompilersbeathumans• AssemblylanguagestillusedinsmallpartsoftheOSkerneltoaccessspecialhardwareresources
• Forus…learntoprograminassemblylanguage1. Bestwaytounderstandwhatcompilersdotogenerate
machinecode2. BestwaytounderstandwhattheCPUhardwaredoes3. Plusitsgreatfun!
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x86
ARM
RISC-V GreenCard (intextbook)
81/26/18http://inst.eecs.berkeley.edu/~cs61c/resources/RISCV_Green_Sheet.pdf
InspiredbytheIBM360“GreenCard”
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Outline• AssemblyLanguage• RISC-VArchitecture• Registersvs.Variables• RISC-VInstructions• C-to-RISC-VPatterns• AndinConclusion…
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WhatisRISC-V?• FifthgenerationofRISCdesignfromUCBerkeley• Ahigh-quality,license-free,royalty-freeRISCISAspecification• Experiencingrapiduptakeinbothindustryandacademia• Supportedbygrowingsharedsoftwareecosystem• Appropriateforalllevelsofcomputingsystem,frommicro-
controllerstosupercomputers– 32-bit,64-bit,and128-bitvariants(we’reusing32-bitinclass,textbookuses
64-bit)• Standardmaintainedbynon-profitRISC-VFoundation
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FoundationMembers(60+)
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Rumble Development
Platinum:
Gold,Silver,Auditors:
Outline• AssemblyLanguage• RISC-VArchitecture• Registersvs.Variables• RISC-VInstructions• C-to-RISC-VPatterns• AndinConclusion…
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AssemblyVariables:Registers• UnlikeHLLlikeCorJava,assemblydoesnothavevariablesas
youknowandlovethem– Moreprimitive,whatsimpleCPUhardwarecandirectlysupport
• Assemblylanguageoperandsareobjectscalledregisters– Limitednumberofspecialplacestoholdvalues,builtdirectlyintothehardware
– Operationscanonlybeperformedonthese!• Benefit:Sinceregistersaredirectlyinhardware,theyarevery
fasttoaccess(fasterthan1ns-lighttravels1footin1ns!!!)
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Processor
Control
Datapath
RegistersliveinsidetheProcessor
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PC
RegistersArithmetic&LogicUnit
(ALU)
Memory Input
Output
Bytes
Enable?Read/Write
Address
WriteData
ReadData
Processor-MemoryInterface I/O-MemoryInterfaces
Program
Data
SpeedofRegistersvs.Memory• Giventhat
– Registers:32words(128Bytes)– Memory(DRAM):Billionsofbytes(2GBto8GBonlaptop)
• andphysicsdictates…– Smallerisfaster
• HowmuchfasterareregistersthanDRAM??• About100-500timesfaster!
– intermsoflatencyofoneaccess
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NumberofRISC-VRegisters• Drawback:Registersareinhardware.Tokeepthemreallyfast,
theirnumberislimited:– Solution:RISC-Vcodemustbecarefullywrittentouseregisters
efficiently• 32registersinRISC-V,referredtobynumberx0–x31
– Registersarealsogivensymbolicnames,describedlater– Why32?Smallerisfaster,buttoosmallisbad.Goldilocksprinciple(“This
porridgeistoohot;Thisporridgeistoocold;thisporridgeisjustright”)• EachRISC-Vregisteris32bitswide(RV32variantofRISC-VISA)
– Groupsof32bitscalledawordinRISC-VISA– P&HCoDtextbookusesthe64-bitvariantRV64(explaindifferences
later)• x0 isspecial,alwaysholdsvaluezero
– Soreallyonly31registersabletoholdvariablevalues17
C,JavaVariablesvs.Registers• InC(andmostHLLs):
– Variablesdeclaredandgivenatype• Example: int fahr, celsius;
char a, b, c, d, e;
– EachvariablecanONLYrepresentavalueofthetypeitwasdeclared(e.g.,cannotmixandmatchintandcharvariables)
• InAssemblyLanguage:– Registershavenotype;– Operationdetermineshowregistercontentsareinterpreted
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Outline• AssemblyLanguage• RISC-VArchitecture• Registersvs.Variables• RISC-VInstructions• C-to-RISC-VPatterns• AndinConclusion…
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RISC-VInstructionAssemblySyntax•InstructionshaveanopcodeandoperandsE.g.,add x1, x2, x3 # x1 = x2 + x3
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Operationcode(opcode)Destinationregister Secondoperandregister
Firstoperandregister
#isassemblycommentsyntax
AdditionandSubtractionofIntegers•AdditioninAssembly
–Example: add x1,x2,x3 (inRISC-V)–Equivalentto: a=b+c (inC)whereCvariables⇔RISC-Vregistersare:
a⇔x1,b⇔x2,c⇔x3
•SubtractioninAssembly–Example: sub x3,x4,x5 (inRISC-V)–Equivalentto: d=e-f (inC)whereCvariables⇔RISC-Vregistersare:d⇔x3,e⇔x4,f⇔x5
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AdditionandSubtractionofIntegersExample1• HowtodothefollowingCstatement? a=b+c+d-e;• Breakintomultipleinstructions
add x10, x1, x2 # temp = b + cadd x10, x10, x3 # temp = temp + dsub x10, x10, x4 # a = temp - e
• AsinglelineofCmayturnintoseveralRISC-Vinstructions
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add x3,x4,x0 (inRISC-V)samef=g (inC)
Immediates• Immediatesareusedtoprovidenumericalconstants• Constantsappearoftenincode,sotherearespecial
instructionsforthem:• Ex:AddImmediate:
addi x3,x4,-10 (inRISC-V) f=g-10 (inC)whereRISC-Vregistersx3,x4 areassociatedwithCvariablesf,g
• Syntaxsimilartoaddinstruction,exceptthatlastargumentisanumberinsteadofaregister
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addi x3,x4,0 (inRISC-V)sameasf=g (inC)
Processor
Control
Datapath
DataTransfer:LoadfromandStoretomemory
PC
RegistersArithmetic&LogicUnit
(ALU)
Memory Input
Output
Bytes
Enable?Read/Write
AddressWriteData=StoretomemoryReadData=Loadfrommemory
Processor-MemoryInterface I/O-MemoryInterfaces
Program
Data
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MuchlargerplaceToholdvalues,but
slowerthanregisters!
FastbutlimitedplaceToholdvalues
MemoryAddressesareinBytes• Datatypicallysmallerthan32bits,butrarelysmallerthan8bits(e.g.,
chartype)–worksfineifeverythingisamultipleof8bits• Remember,8bitchunkiscalledabyte
(1word=4bytes)• Memoryaddressesarereally
inbytes,notwords• Wordaddressesare4bytes
apart– Wordaddressissameasaddressof
rightmostbyte–least-significantbyte(i.e.Little-endianconvention)
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04812
15913
261014
371115
3124 2316 158 70
Least-significantbyteinword
Least-significantbytegetsthesmallestaddress
Wordsinmemorymuststartatbyteaddressesthatareevenmultiplesof4,i.e.,wordsmustbealigned.Note:alignedwordshavethelow2bitsoftheiraddress=0.
TransferfromMemorytoRegister• Ccode int A[100]; g = h + A[3];
• UsingLoadWord(lw)inRISC-V: lw x10,12(x13) #Regx10getsA[3] add x11,x12,x10 #g=h+A[3]
Assume: x13–baseregister(pointertoA[0])Note: 12–offsetinbytesOffsetmustbeaconstantknownatassemblytime
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TransferfromRegistertoMemory• Ccode int A[100]; A[10] = h + A[3];
• UsingStoreWord(sw)inRISC-V: lw x10,12(x13) #Tempregx10getsA[3] add x10,x12,x10 #Tempregx10getsh+A[3] sw x10,40(x13) #A[10]=h+A[3]
Assume: x13–baseregister(pointer)Note: 12,40–offsetsinbytes
x13+12andx13+40mustbemultiplesof4
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Loading and Storing Bytes• Inadditiontoworddatatransfers
(lw,sw),RISC-Vhasbytedatatransfers:–loadbyte:lb–storebyte:sb
• Sameformataslw,sw• E.g.,lb x10,3(x11)
– contentsofmemorylocationwithaddress=sumof“3”+contentsofregisterx11iscopiedtothelowbytepositionofregisterx10.
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byteloaded
zzz zzzzx
…is copied to “sign-extend”This bit
xxxx xxxx xxxx xxxx xxxx xxxxx10:
RISC-Valsohas“un
signedbyte”
loads(lbu)which
zeroextend
tofillregister.Whynouns
igned
storebytesbu?
Yourturn-clickers
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Answer x12
A 0x5
B 0xf
C 0x3
D 0xffffffff
addi x11,x0,0x3f5sw x11,0(x5)lb x12,1(x5)
What’sthevalueinx12?
Yourturn-clickers
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Answer x12
A 0x5
B 0xf
C 0x3
D 0xffffffff
addi x11,x0,0x3f5sw x11,0(x5)lb x12,1(x5)
What’sthevalueinx12?
Administrivia• TheProject1deadlineextendedtoThursday,11:59pm!• SendDSPletterstoPejie<[email protected]>.• TherewillbeaguerrillasectionThursday7-9PM.• TwoweekstoMidterm#1!• Project2-1releaselaterthisweekorearlynext,due2/16.• Project2-2releaserightaftermidtermanddue2/23.
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RISC-VLogicalInstructions
Logical operationsC
operatorsJava
operatorsRISC-V
instructionsBit-by-bit AND & & andBit-by-bit OR | | orBit-by-bit XOR ^ ^ xorShift left logical << << sllShift right logical >> >> srl
•Usefultooperateonfieldsofbitswithinaword−e.g.,characterswithinaword(8bits)
•Operationstopack/unpackbitsintowords•Calledlogicaloperations
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Logical Shifting•ShiftLeftLogical:slli x11,x12,2#x11=x12<<2
– Storeinx11thevaluefromx12shifted2bitstotheleft(theyfalloffend),inserting0’sonright;<<inC
Before:00000002hex 00000000000000000000000000000010two
After: 00000008hex 00000000000000000000000000001000twoWhatarithmeticeffectdoesshiftlefthave?
•ShiftRightLogical:srliisoppositeshift;>>–Zerobitsinsertedatleftofword,rightbitsshiftedoffend
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ArithmeticShifting• Shiftrightarithmetic(srai)movesnbitstotheright(inserthigh-ordersignbitintoemptybits)
• Forexample,ifregisterx10contained11111111111111111111111111100111two=-25ten
• Ifexecutesrax10,x10,4,resultis: 11111111111111111111111111111110two=-2ten• Unfortunately,thisisNOTsameasdividingby2n
− Failsforoddnegativenumbers− Carithmeticsemanticsisthatdivisionshouldroundtowards0
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ComputerDecisionMaking• Basedoncomputation,dosomethingdifferent• NormaloperationonCPUistoexecuteinstructionsinsequence• Needspecialinstructionsforprogramminglanguages:if-statement
• RISC-V:if-statementinstructionis beq register1,register2,L1 means:gotoinstructionlabeledL1
if(valueinregister1)==(valueinregister2) ….otherwise,gotonextinstruction• beqstandsforbranchifequal • Otherinstruction:bneforbranchifnotequal
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TypesofBranches• Branch–changeofcontrolflow
• ConditionalBranch–changecontrolflowdependingonoutcomeofcomparison– branchifequal(beq)orbranchifnotequal(bne)– Alsobranchiflessthan(blt)andbranchifgreaterthanorequal(bge)
• UnconditionalBranch–alwaysbranch– aRISC-Vinstructionforthis:jump(j)
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Outline• AssemblyLanguage• RISC-VArchitecture• Registersvs.Variables• RISC-VInstructions• C-to-RISC-VPatterns• AndinConclusion…
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ExampleifStatement• Assumingassignmentsbelow,compileifblock f→x10 g→x11 h→x12 i→x13 j→x14
if (i == j) bne x13,x14,skip f = g + h; add x10,x11,x12 . skip: .
. .
. .
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Exampleif-elseStatement• Assumingassignmentsbelow,compile f→x10 g→x11 h→x12 i→x13 j→x14
if (i == j) bne x13,x14,else f = g + h; add x10,x11,x12 else j done f = g – h; else: sub x10,x11,x12 done:
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Magnitude Compares in RISC-V• Untilnow,we’veonlytestedequalities(==and!=inC);
Generalprogramsneedtotest<and>aswell.• RISC-Vmagnitude-comparebranches: “BranchonLessThan” Syntax:blt reg1,reg2, label Meaning: if(reg1<reg2)//treatregistersassignedintegers gotolabel;• “BranchonLessThanUnsigned” Syntax:bltu reg1,reg2, label Meaning: if(reg1<reg2)//treatregistersasunsignedintegers gotolabel;
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“BranchonGreaterThanorEqual”(andit’sunsignedversion)alsoexists.
CLoopMappedtoRISC-VAssembly
int A[20];int sum = 0;for (int i=0; i<20; i++) sum += A[i];
# Assume x8 holds pointer to A# Assign x9=A, x10=sum, x11=iadd x9, x8, x0 # x9=&A[0]add x10, x0, x0 # sum=0add x11, x0, x0 # i=0addi x13,x0,20 # x13=20Loop:lw x12, 0(x9) # x12=A[i]add x10,x10,x12 # sum+=addi x9,x9,4 # &A[i++]addi x11,x11,1 # i++blt x11,x13,Loop
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Outline• AssemblyLanguage• RISC-VArchitecture• Registersvs.Variables• RISC-VInstructions• C-to-RISC-VPatterns• AndinConclusion…
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InConclusion,…• Instructionsetarchitecture(ISA)specifiesthesetof
commands(instructions)acomputercanexecute• Hardwareregistersprovideafewveryfastvariablesfor
instructionstooperateon• RISC-VISArequiressoftwaretobreakcomplexoperationsinto
astringofsimpleinstructions,butenablesfaster,simplehardware
• Assemblycodeishuman-readableversionofcomputer’snativemachinecode,convertedtobinarybyanassembler
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