cs 423 – operating systems design lecture 9 –context switches, coordination roy campbell fall...

CS 423 – Operating Systems Design

Lecture 9 –Context Switches, Coordination

Roy CampbellFall 2010

Context Switch

• PCBs move from queue to queue as they change state– Red circles indicate where context switches can

occur

Context SwitchSwitch between one program control

flow and another• Context – Machine level:

– integer/floating pt/stack/heap/PCB registers

– status registers: overflow, branch– memory status: tlb, L1, L2, L3, cache,

virtual memory status, addressing faults, memory ops

– pipeline/hyperthread status– interrupts: status, pending

Instruction Seq for switch

• Hardware:– IA86 – heavy weight CALL, TSS context

switch instructions change registers and stacks.

• Software:– Light weight, do it yourself register

changes.

– must change context prior to restore

Instruction Seq for switch

• Hybrid:– Hardware: change program

counter/registers via interrupt or operation basic primitive – software must add any additional changed context after switch.

– Restoring program counter using hardware primitive – must change context prior to restore

Simple software Context Switch)

Switch(tCur,tNew) { /* Unload old thread */ TCB[tCur].regs.r7 = CPU.r7;

… TCB[tCur].regs.r0 = CPU.r0;

TCB[tCur].regs.sp = CPU.sp; TCB[tCur].regs.retpc = CPU.retpc; /*return addr*/

/* Load and execute new thread */ CPU.r7 = TCB[tNew].regs.r7;

… CPU.r0 = TCB[tNew].regs.r0; CPU.sp = TCB[tNew].regs.sp; CPU.retpc = TCB[tNew].regs.retpc; return; /* Return to CPU.retpc */}

Additional Context Switch Overhead

• Application State – stack, heap, sockets…

• Virtual Machine State – i/o and network support and VM mappings

• Virtual Memory State - vmtable, tlb cache,

• User Process, Thread State – thread/process stack, heap, ready queue, exception handling

• Kernel Process, Thread State – kernel thread/process stack, heap, interrupt vectors

Optimizing Context Switch

• Lazy context switching – wait until dispatch knows what is running next and then change minimized context.

• When switching between different protection domains, check parameters.

• Minimize protection checking – Light Remote Procedure Call – don’t check parameters if remain in same protection domain

Switch Details• How many registers need to be saved/restored?

– MIPS 4k: 32 Int(32b), 32 Float(32b)– Pentium: 14 Int(32b), 8 Float(80b), 8 SSE(128b),…– Sparc(v7): 8 Regs(32b), 16 Int regs (32b) * 8 windows =

136 (32b)+32 Float (32b)– Itanium: 128 Int (64b), 128 Float (82b), 19 Other(64b)

• retpc is where a return should jump to.– In reality, this is implemented as a jump

• Software switch is often implemented as assembly!

Intel Task Switching Instructions

• JMP, Call to a Task Segment S in a GDT (Global Descriptor Table)

• JMP, Call to a task-gate descriptor (contains a TSS) in the GDT, or current LDT

• Implicit call to an interrupt-handler task

• Implicit call to an exception-handler task

• A return (IRET) when the NT flag (Nested Task) is set. Used to return from interrupts.

Intel CALL InstructionThis instruction can be used to execute four types of calls:• Near Call — A call to a procedure in the current code segment (the

segmentcurrently pointed to by the CS register), sometimes referred to as an

intrasegmentcall.• Far Call — A call to a procedure located in a different segment than

the currentcode segment, sometimes referred to as an inter-segment call.• Inter-privilege-level far call — A far call to a procedure in a segment

at adifferent privilege level than that of the currently executing program orprocedure.• Task switch — A call to a procedure located in a different task.• See Chapter 7, “Task Management,” in the Intel® 64 and IA-32

Architectures Software Developer’s Manual, Volume 3A, for information on performing task switches with the CALL

©Gabriel Kliot, Technion 12

Context switch in Linux


Memory layout – general picture

Stack

Process Y user memory

TSS of CPU i

tss->esp0

Stack

Process X user memory

Stack

Process Z user memory

Kernel memory

Stack

Process Z kernel stack and task_struct

task_struct

Stack

Process X kernel stack and task_struct

task_struct

Stack

Process Y kernel stack and task_struct

task_struct


TSS

tss->esp0

#1 – kernel stack after any system call, before context switch

ss

esp

eflags

cs

eip

orig_eax

es

ds

eax

ebp

edi

esi

edx

ecx

ebx

prev

esp

…

Schedule() function frame

…

…

User Stack

User Code

Saved on the kernel stack during a transition to kernel mode by a jump to interrupt and by SAVE_ALL macro

task_struct

thread.esp0


prev

TSS

tss->esp0

esp

#2 – stack of prev before switch_to macro in schedule() func

task_struct

thread.eip

thread.esp

thread.esp0

Schedule() saved EAX, ECX, EDX

Old (schedule’s()) EBP

Arguments to contex_switch()

Return address to schedule()

…

…


TSS

tss->esp0

#3 – switch_to: save esi, edi, ebp on the stack of prev

task_struct

thread.eip

thread.esp

thread.esp0

prev

esp





EDI

ESI

EBP

…

…


TSS

tss->esp0

#4 – switch_to: save esp in prev->thread.esp

esp





EDI

ESI

EBP

…

task_struct

thread.eip

thread.esp

thread.esp0

prev…


next

TSS

tss->esp0

#5 – switch_to: load next->thread.esp into espprev





EDI

ESI

EBP

…

task_struct

thread.eip

thread.esp

thread.esp0





EDI

ESI

EBP

…

esp

$1fthread.eip

thread.esp

thread.esp0

task_struct

… …


next

TSS

tss->esp0

prev





EDI

ESI

EBP

…

task_struct

thread.eip

thread.esp

thread.esp0





EDI

ESI

EBP

…

esp

$1fthread.eip

thread.esp

thread.esp0

task_struct

…

#6 – switch_to: save return address in the prev->thread.eip

$1f

…


next

TSS

tss->esp0

prev





EDI

ESI

EBP

…

task_struct

thread.eip

thread.esp

thread.esp0





EDI

ESI

EBP

…

esp

$1fthread.eip

thread.esp

thread.esp0

task_struct

…

$1f

#7 – switch_to: save return address on the stack of next

$1f

…


nextprev





EDI

ESI

EBP

…

task_struct

thread.eip

thread.esp

thread.esp0





EDI

ESI

EBP

…

esp

$1fthread.eip

thread.esp

thread.esp0

task_struct

…

$1f

$1f

#8 – __switch_to func: save the base of next’s stack in TSS

TSS

tss->esp0

…


nextprev





EDI

ESI

EBP

…

task_struct

thread.eip

thread.esp

thread.esp0





EDI

ESI

EBP

…

esp

$1fthread.eip

thread.esp

thread.esp0

task_struct

…

$1f

#9 – back in switch_to: eip points to $1f instruction label

eip

1:

TSS

tss->esp0

…


next

TSS

tss->esp0

prev





EDI

ESI

EBP

…

task_struct

thread.eip

thread.esp

thread.esp0





…esp

$1fthread.eip

thread.esp

thread.esp0

task_struct

…

$1f

#10 – switch_to: restore esi, edi, ebp from the stack of next

…

Where to look for more info

• The key function for context switching is __switch_to() in http://lxr.linux.no/linux+v2.6.35/arch/x86/kernel/process_32.c.

• The difficulties of optimizing context switching on i7:

http://software.intel.com/sites/billboard/archive/goal-posts.php• Intel processor manuals can be found here:http://www.intel.com/products/processor/manuals/• See Page 120 for CALL instruction

http://www.intel.com/Assets/PDF/manual/253666.pdf

http://lxr.linux.no/linux+v2.6.35/arch/x86/kernel/process_32.c


http://software.intel.com/sites/billboard/archive/goal-posts.php

http://software.intel.com/sites/billboard/archive/goal-posts.php

http://www.intel.com/products/processor/manuals/



Where to look for more info

• The key function for context switching is __switch_to() in http://lxr.linux.no/linux+v2.6.35/arch/x86/kernel/process_32.c.

• Reason given for software switching – difficult to recover from errors using hardware switch (particularly segment issues.)



Cost of Context Switch

http://wiki.osdev.org/Context_Switching • 2.8 GHZ Pentium P4, approx 811 ns HW for

interrupt, 184 ms address space switch, 67 ns to store/restore registers.

• As CPUs got faster, switches got faster but took relatively more time as clocks got faster.

• BUT, software switching vs hardware switching is used because can recover from errors.

• NOTE: context switching involves invalidating caches - cost varies and can be very large.

• http://www.cs.rochester.edu/u/cli/research/switch.pdf

http://wiki.osdev.org/Context_Switching

http://www.cs.rochester.edu/u/cli/research/switch.pdf

http://www.cs.rochester.edu/u/cli/research/switch.pdf

Arm Context switching

• “Context Switch Overheads for Linux on ARM Platforms” Francis M. David [email protected] Jeffrey C. Carlyle [email protected] Roy H. Campbell [email protected]

mailto:[email protected]



Coordination

• Mutual Exclusion• Signals

– Buffering– Gang scheduling– Simultaneity – multiple processes

waiting for two or more shared events• Priorities• State machine and other solutions

– Atomicity and computation

Mutual Exclusion

• Turtles all the way down

Buffering

Consuming Waiting Producing

Processes Consuming

Processes Producing

Gang Scheduling

Parallel Processes

Rendezvous

Simultaneity

Which transition fires? How to program?

Priorities

• Many Readers or Single Writer• Writer Preference is many

writer/readers waiting

State Machine

• Can always build a state machine representation of the synchrnoization condition?

• When can you do that using semaphores only?

CS 423 - Fall 2007

Summary

• Context Switch• Coordination

cs 423 – operating systems design lecture 9 –context switches, coordination roy campbell fall...

Documents

stack of prev task

technion12 context switch

context switch pcbs

esp0 slide

switch hardware

different task

switch hybrid

switch details