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Impact of Interconnect

Parasitics• Reduce Robustness 

• Affect Performance • Increase delay

• Increase power dissipation

Classes of Parasitics 

• Capacitive 

• Resistive 

• Inductive 

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INTERCONNECT

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Capacitive Cross Talk

 X 

Y V  X 

C  XY 

C Y 

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Capacitive Cross Talk

Dynamic Node

3 x 1 mm overlap: 0.19 V disturbance

C  Y

C   XY

V  DD

PDN 

CLK 

CLK 

In 1 In 2 In 3 

Y

 X  2.5 V 

0 V 

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Capacitive Cross Talk

Driven Node

tXY = R Y(CXY+C Y)

Keep time-constant smaller than rise time

V (Volt) 

0 

0.5 

0.45 

0.4 

0.35 

0.3 

0.25 

0.2 

0.15 

0.1 

0.05 

0  1 0.8 0.6 

t (nsec) 

0.4 0.2 

 X  

Y  V   X  

 R Y  

C   XY  

C  Y  

tr ↑ 

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Dealing with Capacitive Cross

Talk

•  Avoid floating nodes

• Protect sensitive nodes

• Make rise and fall times as large as possible• Differential signaling

• Do not run wires together for a long distance

• Use shielding wires

• Use shielding layers

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Shielding

GND

GND

Shielding wire 

Substrate ( GND ) 

Shielding layer  

V  DD 

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Impact of Cross Talk on Delay

r is ratio between capacitance to GND and to neighbor

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Structured Predictable

Interconnect

S

S SV   V S

G

S

S V

G

V

S

S SV   V S

G

S

S V

G

V

Example: Dense Wire Fabric ([Sunil Kathri])Trade-off:• Cross-coupling capacitance 40x lower, 2% delay variation

• Increase in area and overall capacitance

 Also: FPGAs, VPGAs

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Interconnect Projections

Low-k dielectrics• Both delay and power are reduced  by dropping interconnect

capacitance

• Types of low-k materials include: inorganic (SiO2), organic

(Polyimides) and aerogels (ultra low-k)

• The numbers below are on the

conservative side of the NRTS roadmap

Generation 0.25mm

0.18mm

0.13mm

0.1mm

0.07mm

0.05mm

Dielectric

Constant

3.3 2.7 2.3 2.0 1.8 1.5

 

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Encoding Data Avoids Worst-Case

Conditions

Encoder  

Decoder  

Bus 

In

Out

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Driving Large Capacitances

V  in V  out

C  L

V  DD

• Transistor Sizing• Cascaded Buffers

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Using Cascaded Buffers

C L = 20 pF  

In Out

1 2 N

0.25 m process 

Cin = 2.5 fFtp0 = 30 ps

 F  = CL/Cin = 8000

 fopt  = 3.6  N  = 7tp = 0.76 ns

(See Chapter 5)

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Output Driver Design

Trade off Performance for Area and Energy

Given t  pmax  find N  and f  

•  Area

• Energy

  m inm inm in

12

1

1

1

1...1   A

 f  

 F  A

 f  

 f   A f   f   f   A

 N  N 

driver 

 

  2221211

1...1  DD

 L DDi DDi

 N 

driver    V  f  

C V C 

 f  

 F V C  f   f   f   E