CoreFFT

User’s Guide

Actel Corporation, Mountain View, CA 94043

© 2007 Actel Corporation. All rights reserved.

Printed in the United States of America

Part Number: 50200054-3

Release: May 2007

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Table of Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1 Running CoreFFT . . . . . . . . . . . . . . . . . . . . . . . . . . 7Installing CoreFFT Evaluation Version in Libero IDE . . . . . . . . . . . . . . 7

Installing CoreFFT Full Version in Libero IDE . . . . . . . . . . . . . . . . . . 8

Pre-Synthesis Simulation in Libero IDE . . . . . . . . . . . . . . . . . . . . . . 10

Synthesis in Libero IDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Post-Synthesis Simulation in Libero IDE . . . . . . . . . . . . . . . . . . . . . 14

Place–and–Route in Libero IDE . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Testbench Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

A Product Support . . . . . . . . . . . . . . . . . . . . . . . . . . 19Customer Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Actel Customer Technical Support Center . . . . . . . . . . . . . . . . . . . . . 19

Actel Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Website . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Contacting the Customer Technical Support Center . . . . . . . . . . . . . . . 20

CoreFFT User’s Guide 3

CoreFFT User’s Guide 5

Introduction

This manual describes CoreFFT design flows and provides implementation hints as well as operation details not provided in the datasheet.

CoreFFT is a Microsoft® Windows® command line program that generates an FFT engine based on the user’s request. The generated FFT module is optimized for Actel FPGA devices. This guide provides information on running CoreFFT generator, generating a module and testbench RTL code, and implementing the design flow using the Actel Libero® Integrated Design Environment (IDE). The design flow description contains procedures for macro simulation and synthesis and procedures for performing place–and–route (layout) utilizing the macro. For complete information on macro use, refer to this guide in conjunction with the CoreFFT datasheet. CoreFFT is available as a full version or as a demo (evaluation) version. Two flavors of the evaluation version are provided: demoFFT_verilog that generates Verilog RTL, and demoFFT_ vhdl that generates VHDL RTL.

• The full version of CoreFFT generates RTL code for the user-defined FFT engine and test harness. The model is fully supported in the Actel Libero IDE.

• The evaluation version supports the FFT engine and test harness generation with limited parameters:

– 32-point forward FFT with automatic scaling

– Axcelerator® FPGA family

This guide describes use cases for Libero IDE on the PC.

1Running CoreFFT

The majority of the design flows are common to both the Full and Evaluation versions of CoreFFT. The differences are outlined below.

Installing CoreFFT Evaluation Version in Libero IDE You can skip this step if you are running the full version.

To install CoreFFT evaluation version:

1. Start Libero IDE and create a new project named demoFFT, for example. You must select the Axcelerator device family.

2. Unzip the file evalFFT.zip to extract files evalFFT.exe and evalFFT_conf.txt.

3. Copy both extracted files in the top-level directory created by Libero IDE (D:\Actelprj\FFTdemo).

4. Run CoreFFT by typing an appropriate command at the DOS prompt:

D:\Actelprj\FFTdemo>evalFFT evalFFT_conf.txt

A message appears on the DOS screen, warning that the Evaluation version is being used.

5. Type the following command to run the fft.bat file that appears in the D:\Actelprj\ FFT demo directory:

D:\Actelprj\ FFTdemo > fft.bat

CoreFFT User’s Guide 7

Running CoreFFT

Installing CoreFFT Full Version in Libero IDE You can skip this step if you are running the Evaluation version.

To install CoreFFT full version:

1. Unzip the file coreFFT.zip to extract the coreFFT.exe file and an example of a configuration file named configFFT.txt.

2. Create a CoreFFT configuration file in *.txt format. To create it from scratch, follow the configuration file description given in the FFT datasheet, or modify an attached configFFT.txt file using a text editor. Assume the FFT configuration file is assigned a name of configFFT.txt.

3. Copy the coreFFT.exe file and the FFT configuration file (configFFT.txt) in the top-level directory created by Libero IDE (D:\Actelprj\FFTdemo).

4. Type the following command at the Command prompt to run CoreFFT:

D:\Actelprj\FFTdemo > coreFFT configFFT.txt

5. Type the following command to run the fft.bat file that appears in the D:\Actelprj\ FFTdemo directory:

D:\Actelprj\ FFTdemo > fft.bat

8 CoreFFT User’s Guide

Installing CoreFFT Full Version in Libero IDE

Figure 1-1 · Libero IDE Demo Project Settings

CoreFFT User’s Guide 9

Running CoreFFT

Pre-Synthesis Simulation in Libero IDEThe pre-synthesis simulation verifies correctness of the RTL code generated. Use the following procedure to run pre-synthesis simulation in the Libero IDE. The same procedure applies to both Evaluation and Full versions.

To run pre-synthesis simulation:

1. Set ModelSim.do script.

• In Libero IDE Graphical User Interface (GUI), go to Options > Project Settings and choose the Simulation tab.

• Clear the Use Automatic Do file option.

• Enter the path and name of the pre-synthesis run_presynth.do file generated by coreFFT, D:/Actelprj/FFTdemo/simulation/run_presynth.do. Click OK.

2. Run simulation.

• Click the Simulation – ModelSim button in the Libero IDE GUI to start pre-synthesis simulation.

• When prompted, set up stimulus.

• Choose Associate with Stimulus.

• Click OK.

• Select fft_tb.v.

• Click Add.

• Click OK.

• Simulation will run automatically.

Successful simulation runs four tests and results in a screen similar to the one shown in Figure 1-2 on page 11.

3. Quit ModelSim.

10 CoreFFT User’s Guide

Pre-Synthesis Simulation in Libero IDE

Figure 1-2 · Pre-Synthesis Simulation Result (ModelSim screenshot)

CoreFFT User’s Guide 11

Running CoreFFT

Synthesis in Libero IDEUse the following procedure to run synthesis in the Libero IDE. The same procedure applies to both Evaluation and Full versions.

To run synthesis:

1. Click the Synthesis – Synplify button in the Libero IDE GUI.

2. Make sure the Synplify project has all the necessary source files and libraries, then ensure that the files are arranged in the following order:

• axcelerator.v

• actram.v

• actar.v

• fftHeader.v

• twiddle.v

• fftSm.v

• fftDp.v

• fftTop.v

Figure 1-3 on page 13 depicts an example of the Synplify GUI.

3. In the Synplify GUI, verify the correct FPGA family and device are selected (for example, Axcelerator and AX1000).

4. Go to Synplify Project > Implementation Options, select the Verilog tab, check the Use Verilog 2001 option, and click OK.

5. Click the Run button in the Synplify GUI.

12 CoreFFT User’s Guide

Synthesis in Libero IDE

Figure 1-3 · Synplify Synthesis Tool Demo Project Settings

CoreFFT User’s Guide 13

Running CoreFFT

Post-Synthesis Simulation in Libero IDEThe post-synthesis simulation verifies the synthesized model. Use the following procedure to run post-synthesis simulation in the Libero IDE. The same procedure applies to both evaluation and full versions.

To run post-synthesis simulation:

1. Set ModelSim.do script.

• In the Libero IDE GUI, go to Options > Project Settings menu and choose the Simulation tab.

• Enter the post-synthesis file name (D:/Actelprj/FFTdemo/simulation/run_postsynth.do) in the user-defined Do File window.

• Click OK.

2. Click the Simulation – ModelSim button in the Libero IDE GUI to run post-synthesis simulation.

Successful simulation runs four tests and results in a screen similar to the one shown in Figure 1-4 on page 15. The simulation results are also stored in the file \simulation\fftResult.txt. If the simulation fails both the actual result and the golden output, the test vector shows up in the \simulation\fftResult.txt file.

3. Quit ModelSim.

14 CoreFFT User’s Guide

Post-Synthesis Simulation in Libero IDE

Figure 1-4 · Post-Synthesis Demo Simulation Result (ModelSim screenshot)

CoreFFT User’s Guide 15

Running CoreFFT

Place–and–Route in Libero IDEUse the following procedure to run place-and-route in the Libero IDE. The same procedure applies to both evaluation and full version.

To run place-and-route:

1. Click the Designer button in the Libero IDE to start place-and-route.

2. Using the Designer GUI, choose the targeted Actel FPGA family, device, speed grade, and operation conditions.

3. Set timing constraints.

• In the Designer GUI, go to File > Import Auxiliary Files.

• When prompted, select the fftTop.sdc constraint file.

• Click Import.

• Click OK.

• Accept the default settings in the Compile Options window. The designer tool automatically starts compilation.

4. When the compilation is over, proceed with layout.

Testbench DescriptionCoreFFT automatically generates a testbench that is used for pre-synthesis and post-synthesis simulations. It also generates two input test vectors and two golden output test vectors. One of the test vectors presents a complex harmonic, the other one presents a complex pseudo-random signal. Figure 1-5 on page 17 depicts a functional block diagram of the FFT testbench.

The testbench fft_tb makes the FFT engine run four times—switching between the test vectors at every run. After every run, the fft_tb compares the actual results obtained from the FFT engine against the golden output vectors and reports the comparison result: “FFT test passed” or “FFT test failed”. Normally the simulation ends up with four messages: “FFT test passed”.

16 CoreFFT User’s Guide

Testbench Description

Figure 1-5 · Testbench Functional Block Diagram

FFT FFT ResultsCompare Report

FFTresult.txt

TestVector 1(file IdData1)

TestVector 2(file IdData2)

GoldenVector 1(file golden1)

GoldenVector 2(file golden2)

CoreFFT User’s Guide 17

AProduct Support

Actel backs its products with various support services including Customer Service, a Customer Technical Support Center, a web site, an FTP site, electronic mail, and worldwide sales offices. This appendix contains information about contacting Actel and using these support services.

Customer ServiceContact Customer Service for non-technical product support, such as product pricing, product upgrades, update information, order status, and authorization.

From Northeast and North Central U.S.A., call 650.318.4480From Southeast and Southwest U.S.A., call 650. 318.4480From South Central U.S.A., call 650.318.4434From Northwest U.S.A., call 650.318.4434From Canada, call 650.318.4480From Europe, call 650.318.4252 or +44 (0) 1276 401 500From Japan, call 650.318.4743From the rest of the world, call 650.318.4743Fax, from anywhere in the world 650.318.8044

Actel Customer Technical Support CenterActel staffs its Customer Technical Support Center with highly skilled engineers who can help answer your hardware, software, and design questions. The Customer Technical Support Center spends a great deal of time creating application notes and answers to FAQs. So, before you contact us, please visit our online resources. It is very likely we have already answered your questions.

Actel Technical SupportVisit the Actel Customer Support website (www.actel.com/custsup/search.html) for more information and support. Many answers available on the searchable web resource include diagrams, illustrations, and links to other resources on the Actel web site.

WebsiteYou can browse a variety of technical and non-technical information on Actel’s home page, at www.actel.com.

CoreFFT User’s Guide 19

Product Support

Contacting the Customer Technical Support CenterHighly skilled engineers staff the Technical Support Center from 7:00 A.M. to 6:00 P.M., Pacific Time, Monday through Friday. Several ways of contacting the Center follow:

EmailYou can communicate your technical questions to our email address and receive answers back by email, fax, or phone. Also, if you have design problems, you can email your design files to receive assistance. We constantly monitor the email account throughout the day. When sending your request to us, please be sure to include your full name, company name, and your contact information for efficient processing of your request.

The technical support email address is tech@actel.com.

PhoneOur Technical Support Center answers all calls. The center retrieves information, such as your name, company name, phone number and your question, and then issues a case number. The Center then forwards the information to a queue where the first available application engineer receives the data and returns your call. The phone hours are from 7:00 A.M. to 6:00 P.M., Pacific Time, Monday through Friday. The Technical Support numbers are:

650.318.4460800.262.1060Customers needing assistance outside the US time zones can either contact technical support via email (tech@actel.com) or contact a local sales office. Sales office listings can be found at www.actel.com/contact/offices/index.html.

20 CoreFFT User’s Guide

For more information about Actel’s products, visit our website at http://www.actel.comActel Corporation • 2061 Stierlin Court • Mountain View, CA 94043 USACustomer Service: 650.318.1010 • Customer Applications Center: 800.262.1060

Actel Europe Ltd. • River Court, Meadows Business Park • Station Approach, Blackwater • Camberley Surrey GU17 9AB United Kingdom • Phone +44 (0) 1276 609 300 • Fax +44 (0) 1276 607 540

Actel Japan • EXOS Ebisu Bldg. 4F • 1-24-14 Ebisu Shibuya-ku • Tokyo 150 • JapanPhone +81.03.3445.7671 Fax +81.03.3445.7668 • www.jp.actel.com

Actel Hong Kong • Suite 2114, Two Pacific Place • 88 Queensway, Admiralty Hong Kong

Phone +852 2185 6460 Fax +852 2185 6488 • www.actel.com.cn

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