copyright by muhammad mustafa hussain 2005
TRANSCRIPT
Copyright
by
Muhammad Mustafa Hussain
2005
The Dissertation Committee for Muhammad Mustafa Hussain certifies that this is
the approved version of the following dissertation:
ADVANCED FABRICATION PROCESSES FOR SUB-50 nm CMOS
Committee:
Baxter F. Womack, Supervisor
Dean P. Neikirk
Gary A. Hallock
Leonard F. Register
Naim Moumen
ADVANCED FABRICATION PROCESSES FOR SUB-50 nm CMOS
by
Muhammad Mustafa Hussain, BS, MS, MSEE
Dissertation
Presented to the Faculty of the Graduate School of
the University of Texas at Austin
in Partial Fulfillment
of the Requirements
for the Degree of
Doctor of Philosophy
The University of Texas at Austin
December 2005
In the loving memory
of
my beloved cat, “Bagha”
this dissertation
is dedicated
to
my inspiring, loving and supportive
parents, wife and brother
v
ACKNOWLEDGEMENTS
All the praise is due to Allah – the most beneficial, the most gracious.
I would like to express my deepest gratitude towards my supervising Professor
Baxter F. Womack, for his constant supervision, guidance and support. Since, I joined
UT in January 2003, he has kindly supported me by giving me the opportunity to work
with him as a teaching assistant and then as a PhD student.
Then, I would like to give appreciation to Professor Dean P Neikirk, Professor
Frank Register and Professor Gary Hallock for their kindness to spare their valuable time
to serve in my dissertation committee. Professor Neikirk has shown me how to look at a
research idea from a realistic viewpoint. Professor Hallock’s benevolent consideration for
Victor L. Hand Graduate Fellowship has helped me to continue my graduate study.
Professor Register’s calming gesture has given me confidence to pursue my goal.
I also humbly remember by undergraduate advisor Professor AHM Zhirul Alam
for his perpetual trust on me. I respectfully thank Professor Aluzio Prata, Miss Ramona
Gordon of the University of Southern California, Professor Gary May of Georgia
Institute of Technology, Professor Lih Lin of the University of Washington, Seattle, Miss
Melanie Gullick of the University of Texas at Austin and Miss Mahmooda Sultana of
Massachusetts Institute of Technology for their sympathetic understanding and timely
support during my graduate study.
vi
I will always remember Professor Alan Willner of the University of Southern
California and Professor Dean P Neikirk for their incredible teaching and presentation
style.
Dr. Naim Moumen of IBM opened up the door of my cherished dream to pursue
my PhD. Without his and SEMATECH’s support I would not have been able to complete
all these works. I also thank some of my very good colleagues who have regularly
mentored me: Dr. Zhibo Zhang, Dr. Manuel Quevedo and Dr. Husam Alshareef of Texas
Instruments, Dr. S. C. Song and Mr. Joel Barnett of SEMATECH, Austin. I must thank
Mr. Barry Sassman, Miss Dana Larison, Mr. Gabe Gebara, Mr. Sidi Lanee and Mr. James
Price of SEMATECH for their wonderful and persistent friendly help.
Finally, I want to talk about my family members without whom I cannot even
think about my existence. My motivational mom Mrs. Hosne Ara Begum has taken all
the pains since I came in her womb. My inspiring father Dr. Mohammad Abdul Hakim
has supported me in my every deed. My loving wife Mrs. Sadaq I Iffat (Zarah) has made
my daily life amazingly easy. My flamboyant brother Mr. Mohammed Rashidul Hassan
has nurtured me in almost every step of my life. And at last, I tenderly remember my
beloved cat Bagha for her relaxing company during the crucial part of my graduate study.
I know I am missing a lot of those who have contributed greatly in my life. This is
not intentional. Rather my forgetful mind is now betraying. Thank you all!
vii
ADVANCED FABRICATION PROCESSES FOR SUB-50 nm CMOS
Publication No. -----------------
Muhammad Mustafa Hussain, Ph.D.
The University of Texas at Austin, 2005
Supervisor: Baxter F. Womack
Scaling CMOS technology into sub-50 nm has presented a significant new
challenge for the semiconductor community. In these devices, silicon oxide gate
dielectric and poly-silicon gate electrode need to be replaced with high-k and metal,
respectively, due to the limitation of scaling gate dielectrics and high gate leakage
current. One of the major challenges in this new high-k/metal CMOS implementation is
the advanced process integration of dual metal gate CMOS to realize nanoscale CMOS
operation. Therefore, in this thesis, deposition-etch-deposition based dual metal gate
CMOS integration has been deeply explored. Highly selective wet process development,
its integration issues, effect on high-k dielectric surface, impacts on CMOS performance
has been investigated. Primary research results have been used to integrate complete dual
metal gate CMOS and the significant device data have been presented. In addition,
thermal annealing effects have been probed to examine physical property change in a
representative high-k/metal film stack. Finally, a comparative study and feasibility of a
simplistic method has been discussed and future research direction has been pointed out.
viii
Table of Contents
List of Tables xi
List of Figures xii
Nomenclature xvi
Chapter 1 Introduction 1
Integration Options 6
Focused Integration Scheme 9
Motivation 10
Approach 10
Chapter 2 Metal Wet Etch Process Development 13
Experimental 14
Wet Etch Results 15
Effects of Wet Etch Chemistries on Film Surfaces 18
Initial Electrical Results of Actual Device Performance 21
Summary 23
Chapter 3 Wet Etch Issues and Effects in Dual Metal Gate CMOS
Integration
24
Wet Etch Issues in Dual Metal Gate CMOS Integration 24
Wet Etch Effects in Dual Metal Gate CMOS 32
ix
Summary 36
Chapter 4 Wet Etch Impact on Dual Metal Gate CMOS Performance
and Reliability
37
Experimental 38
EOT vs Jg 39
Transistor Characteristics 41
Electron and Hole Mobility 43
Fast Transient Charge Trapping 44
PBTI 45
NBTI 46
Summary 47
Chapter 5 Promise of Gate Wet Etch 49
Experimental 50
Results and Discussions 50
Summary 56
Chapter 6 Device Performance of Complete Dual Metal Gate CMOS 57
Fabrication Processes 57
Ru/TaSiN Dual Metal Gate CMOS Characterization 58
TiN/TaCN Dual Metal Gate CMOS Characterization 63
Summary 70
x
Chapter 7 Thermal Annealing Effects on Physical Properties of High-
k/Metal Film Stack
71
Experimental 71
Results and Discussion 73
Summary 78
Chapter 8 Comparative Study 79
Feasibility of Implantation Based Metal Gate Electrode 81
Present Status of Dual Metal Gate CMOS Integration 85
Chapter 9 Conclusion
Key Findings of the Current Work 89
Future Directions 91
Bibliography 93
Vita 106
xi
List of Tables
2.1 Process conditions for various film deposition 14
2.2 Etch Rates (Å/min) of Different Materials for Dual Metal CMOS Fabrication 16
2.3 Etch Rates of Different Materials for Dual Metal CMOS Fabrication 17
3.1 Etch rates of various chemistries on different dielectric films 25
3.2 Etch selectivity of SC1 metal etch over dielectric film etch 25
3.3 Etch rates of 29% NH4OH (10:1) at 60 ºC on different films 27
3.4 Atomic percentage of various elements obtained by surface Auger analysis
after TaSiN(90% Si) wet etch
34
5.1 EOT vs Vfb 52
8.1 Work function table for implantation based TiN metal gate 82
xii
List of Figures
1.1 Gate leakage current versus gate voltage for various oxide thicknesses 2
1.2 Dual Metal Gate CMOS 5
1.3 Inter diffusion based Dual Metal Gate CMOS 7
1.4 Replacement/Damascene Gate Dual Metal CMOS 8
1.5 FUSI Dual Metal Gate CMOS 8
1.6 Deposition-Etch-Deposition Based Dual Metal Gate CMOS 9
2.1 Variation of etch rate of TaSiN due to change in amount of silicon 17
2.2 A scanning electron microscope (SEM) image taken from a wafer after
the initial TEOS and then the exposed TaSiN wet etch.
18
2.3 AFM topography of TaSiN surface after TEOS hard mask removal 19
2.4 AFM topography of HfO2 surface 20
2.5 C-V curves of TaSiN films on HfO2 22
2.6 J-V curves of TaSiN films on HfO2 22
3.1 Initial issues during α-Si dry etch process development 28
3.2 New dry etch process for α-Si removal 29
3.3 SIMS analysis done on PVD TaSiN (Si 90%)/20 Å HfO2/Si substrate 31
3.4 Metal (PVD TaSiN) wet etch does not etch or undercut the α-Si hard
mask
32
3.5 AFM image of high-k surface, after TaSiN removal by wet etching 33
xiii
3.6 Surface Auger spectra taken from the PMOS region after the TaSiN
wet etch
34
3.7 SEM image indicates that final α-Si hardmask wet etching process
from an ALD TaCN wafer
35
3.8 AFM image of high-k dielectric film, after final hardmask wet etching
from a CVD TiSiN indicates high-k surface was smooth
36
4.1 CV characteristics measured on 1X10-5 cm2 NMOS overlap capacitors 39
4.2 Accumulation Jg vs EOT for the devices 40
4.3 Within-wafer Distribution of linear Vt of 10x1 μm transistors 41
4.4 ID-VG CURVES OF 10X1 μm transistors 42
4.5 Charge pumping results measured on 10X1 μm NMOSFETs 42
4.6 (a) Electron mobility, and (b) Hole mobility measured by DC
technique
44
4.7 (a) A representative pulse Id-Vg curve of a 10x0.25 μm NMOSFET.
(b) Normalized Id during pulse voltage stress.
45
4.8 PBTI-induced Vt instability for NMOSFET with different process
conditions
46
4.9 NBTI-induced Vt instability for PMOSFET with different process
conditions
47
5.1 Gate etch of a TaSiN NMOSFET 50
5.2 CV characteristics of 20 x 20 μm TaSiN NMOSFET 51
xiv
5.3 Id-Vg curves 51
5.4 Ig-Vg curves 52
5.5 Vt roll-off characteristics 53
5.6 Cumulative plot of Vt in “as processed” TaSiN NMOSFET 54
5.7 Gate leakage component for a device with a direct tunnel gate oxide 55
5.8 Ig at different channel length 55
6.1 Outline of the dual metal gate CMOS fabrication utilizing a metal wet
etch module
57
6.2 Cross sections TEM pictures 59
6.3 CV characteristics 59
6.4 Id-Vd characteristics 60
6.5 Id-Vg curves 61
6.6 Vt roll-off characteristics 61
6.7 Electron and hole mobility 62
6.8 Impact of TaSiN wet etch 63
6.9 TEM of dual metal gate CMOS 63
6.10 HRTEM of dual metal gate stacks 64
6.11 STEM EELS and EDX 64
6.12 CV characteristics of HfSiON dual metal gate CMOS 65
6.13 CV characteristics of HfO2 dual metal gate CMOS 65
6.14 Id-Vd characteristics of HfSiON dual metal gate CMOS 66
6.15 Id-Vd characteristics of HfO2 dual metal gate CMOS 66
xv
6.16 Id-Vg characteristics of dual metal gate CMOS 66
6.17 Jg-Vg characteristics of HfSiON dual metal gate CMOS 67
6.18 Jg-Vg characteristics of HfO2 dual metal gate CMOS 67
6.19 Vt roll-off characteristics 67
6.20 Ion vs Ioff characteristics 68
6.21 Electron and hole mobility of HfSiON dual metal gate CMOS 69
6.22 Electron and hole mobility of HfO2 dual metal gate CMOS 69
6.23 Pulse measurement of dual metal gate CMOS 69
7.1 Percentile change of pre and post anneal physical properties of
HfO2/TiN film stack
73
7.2 Pre and post annealed SEM images of TiN films 74
7.3 N2 profile from XPS analysis 75
7.4 Titanium profile from XPS analysis 76
7.5 O2 profile from XPS analysis 76
7.6 Stress profile of HfO2/TiN film stack 77
8.1 Implantation based dual metal gate CMOS 81
8.2 C-V curves for HfO2/TiN MOSCAP 82
8.3 C-V curves for HfSiON/TiN MOSCAP 83
8.4 SIMS analysis on the implanted and non-implanted MOSCAP 84
9.1 Dual cap dual metal gate CMOS integration process flow 91
xvi
Nomenclature
Acronym Elaboration
AES Auger Electron Spectroscopy
AFM Applied Force Microscopy
ALD Atomic Layer Deposition
ATDF Advanced Technology Development Facility
CMOS Complimentary Metal Oxide Semiconductor
CVD Chemical Vapor Deposition
DMG Dual Metal Gate
EDS Energy Dispersive Spectrometer
EELS Electron Energy Loss Spectroscopy
EOT Equivalent Oxide Thickness
ER Etch Rate
HRTEM High Resolution Transmission Electron Microscopy
IC Integrated Chip
ISSG In-situ Steam Generation (Usually used for SiO2)
MGF Metal Gate First
MGL Metal Gate Last
NBTI Negative Bias Temperature Instability
NMOSFET n-type Metal Oxide Semiconductor Field Effect Transistor
PBTI Positive Bias Temperature Instability
xvii
Acronym Elaboration
PETEOS Plasma Enhanced Tetra Ethyl Ortho Silicate
PMOSFET p-type Metal Oxide Semiconductor Field Effect Transistor
PVD Physical Vapor Deposition
SCP Santa Clara Plasitc
SEM Scanning Electron Microscope
SIMS Secondary Ion Mass Spectroscopy
TDDB Time Dependent Dielectric Breakdown
TEM Transmission Electron Microscopy
XPS X-ray Photoelectron Spectroscopy
1
Chapter 1: Introduction
Shrinking the conventional MOSFET beyond the 50 nm technology node requires
innovations to circumvent barriers due to the fundamental physics that constrains the
conventional MOSFET. The limits most often cited [1-9] are:
1) Quantum mechanical tunneling of carriers through the thin gate oxide;
2) Quantum mechanical tunneling of carriers from the source to drain, and from
drain to the body of the MOSFET;
3) Control of the density and location of dopant atoms in the MOSFET channel and
location of dopant atoms in the MOSFET channel and source/drain region to
provide a high on-off current ratio;
4) The finite sub-threshold slope.
In CMOS scaling gate dielectric has a very prominent role. Silicon dioxide has been
used as a gate dielectric in silicon based CMOS since 1957 [10]. For today’s mainstream
MOSFET gate oxide thickness of ≅ 1.5 – 2 nm are used [11]. These ultra thin dielectric
layers are grown in a standard thermal diffusion furnace using pure oxygen or preferably
a mixture of oxidizing gases at temperatures between 900ºC and 1000ºC. Before
oxidation the silicon surface must be cleaned carefully with high purity chemicals. The
SiO2 layer grows controllably in a layer by layer mode, where the growth rate can be
described by the Deal-Grove reaction model. However, thinning down the oxide
thickness raises severe technological problems:
2
1) Dielectric thickness variation;
2) Penetration of impurities, in particular boron, from the highly doped poly-silicon
gate;
3) Reliability and lifetime problems for devices made with ultra thin oxides;
4) Gate leakage current increases exponentially with decreasing thickness.
The problem of gate leakage is demonstrated in Figure 1.1, which shows the
measured and simulated leakage currents versus the gate voltage for various oxide
thicknesses ranging from 3.6 to 1.0 nm. The leakage current at a gate bias of 1 V changes
from 1 pA/cm2 at 3.5 nm to 10 A/cm2 at 1.5 nm, which is 13 orders of magnitude. The
practical SiO2 thickness limit in a MOSFET device is reached when the gate leakage
becomes equal to the off-state source to drain sub-threshold leakage current. Beyond this
limit direct electron tunneling from the p-Si through the thin oxide into an n+-poly-silicon
becomes the dominant leakage mechanism. Tunneling of holes is less critical since the
tunneling probability for holes is much smaller than for electrons [13].
Figure 1.1: Measured (bold) and simulated (dotted) gate leakage current versus gate
voltage for various oxide thicknesses. The leakage current increases exponentially as the
oxide thickness is scaled down [12].
3
For low power applications in the field of portable equipment (mobile phones, palm
tops, etc.) gate leakage in serious excess of the off current is unacceptable. The gate
leakage current reduces battery life in stand-by mode. Here, gate leakage currents above
approx. 1 A/cm2 are not acceptable. For high performance applications (such as
microprocessors) stand-by power consumption is less of an issue. However, power
dissipation becomes critical at about 10 A/cm2.
High-k materials can solve the leakage problem of silicon dioxide based dielectrics
since their thickness can be made significantly larger, as the equivalent oxide thickness
(EOT) is given by:
xfilm
SiO tEOTεε
2=
However, it should be noted that leakage current is limited only by the direct
tunneling current in nearly perfect materials. There are several other leakage mechanisms
associated with material defects that can contribute to leakage far in excess of the
fundamental tunnel current leakage limit. Furthermore, the tunnel current is low only if
the energy band offsets of the dielectric relative to silicon are sufficiently high.
Now, in the standard CMOS process, heavily doped poly-silicon is applied as a
gate contact materials in the transistor MOS capacitor. The main advantage of poly-
silicon is that the work function can be adjusted by doping for p- and n-channel devices.
In addition, the process is well known and provides high yield. The disadvantage of poly-
silicon use is the formation of a depletion layer within the poly-silicon and its high
resistivity. The resistivity limits the drive current and the depletion requires the use of
4
thinner gate dielectrics. For high current transistor operation, a high charge in the channel
in inversion is the key parameter. Thus, a high capacitor equivalent thickness (CET) is
required. The depletion in the semi metallic poly-silicon adds “dielectric thickness” to the
true dielectric thickness, the EOT. Typically 0.4 nm “thickness” is added to the CET
value in inversion. Because of the high carrier density in metals the depletion effect is
negligible. However, many transition metals react with SiO2 at elevated temperatures to
form metal silicide and metal oxide layers [14,15]. Hence, the use of metal gates relaxes
the requirements of the high-k materials. For a given high-k material, the gate dielectrics
can be made thicker and the gate leakage can be reduced. Also, the thermal instability of
most high-k materials may require the use of a low thermal budget process after the gate
dielectric deposition, the high temperature gate poly-silicon activation step necessarily
occurs after the gate dielectric formation [16]. A further potential benefit of metal gate
electrodes is the elimination of carrier mobility degradation due to plasmon scattering
from the gate dielectric. The plasmon frequency of a highly conductive metal electrode is
too high to interact with the carriers in the inversion layer [17]. Consequently, researchers
have made hefty efforts to replace poly silicon gate with the metal one [18-36].
From a device design point of view, the most important consideration for the gate
electrode is the work function of the material. While the poly-silicon gate technology has
somewhat locked in the gate work functions to values close to the conduction band and
the valence band of silicon, the use of a metal gate material opens up the opportunity to
choose the work function of the gate and redesign the device to achieve the best
combination of work function and channel doping. But, NMOS and PMOS transistors
5
would require gate materials with different work functions: smaller for NMOS and larger
fro PMOS. And this initiates the concept of Dual Metal Gate CMOS (Figure 1.2).
Figure 1.2: Dual Metal Gate CMOS
While there are plenty of metal choices that may satisfy the work function
requirements, other device and integration considerations narrow down the choices
significantly. The requirements of a low gate dielectric/silicon interface state density and
low gate dielectric fixed charges imply that a damage free metal deposition process (e.g.,
traces of the Chemical Vapor Deposition (CVD) in stead of sputtering) is required. At the
same time, the deposition process must not introduce impurities (e.g., traces of the CVD
precursor materials) into the gate stack. The thermal stability of the metal electrode must
at least withstand the thermal anneals required to passivate the silicon/gate dielectric
interface (e.g., forming gas anneal) after the metal deposition, as well as thermal
processing of the back end metallization processes. Furthermore, it is desirable to have a
low resistivity (at least similar to conventional silicides such as CoSi2 and TiSi2),
STINMOS PMOS
N - meta P-meta
STI NMOS PMOS
N - metal P-metal
6
although this requirement may be relaxed by strapping the gate electrode of the proper
work function with a lower resistivity material on top.
The gate electrode work function issue is further complicated by the fact that the
work function measured in vacuum is different from the work function value when the
metal is in contact with a dielectric. In general, a dipole forms at the metal/dielectric
interface combination [37,38]. Thus the choice of appropriate metal electrode is then also
dependent upon the choice of the gate dielectric: SiO2 or high-k material.
Integration Options
Different techniques have been tried to successfully implement either single metal
gate electrode or dual metal gate CMOS [39-78]. However, if metals with two different
work functions are employed for NMOS and PMOS, respectively, the integration of
NMOS and PMOS in a CMOS process remains a challenge. A gate first CMOS process
using two different metals relies on reactive ion etching (RIE) process to simultaneously
pattern two dissimilar gate metals, with high selectivity to the ultra thin gate dielectric
[48]. The Ru-Ta alloys proposed by Zhong et al. can possess superior thermal stability
and wide work function tuning range [33,42]. However, the work function modulation
seems not to be continuous so that the work function values with interest for advanced
transistor structures (4.4-5 eV) would be unachievable. On the other hand, the Pt-Ta
alloys proposed by Tsui et al. are demonstrated to possess wide and continuous work
function modulation [34], but the issue of gate dielectric integrity degradation mentioned
7
in [48] would be problematic due to the lack of suitable integration methods. Similarly, S.
H. Bae et al proposed that the laminated metal gate stacks HfN-Ti-TaN and Ti-Ta can
possess P and NMOS compatible work function values (5.1 and 4.35 eV) [49]. However,
the process integration of these two distinct laminated metal stacks into dual metal gate
CMOS process is still problematic [48]. Otherwise, a novel work function modulation
using nitrogen implanted Mo was proposed by Ranade et al. [50]. The major advantage
of this method is the ease of process integration, while the value strongly depends on the
implant parameters and subsequent annealing conditions. Precise work function
modulation would not be easily achievable.
Figure 1.3: Inter diffusion based Dual Metal Gate CMOS
Gate last approach utilizing damascene/replacement technique (Figure 1.4) avoids
difficult issues related to high temperature budget, contamination and metal etching [51-
60]. However, damascene metal gate transistors with the sputtered-TiN barrier metal
were found to show large threshold voltage deviation [51].
STINMOS PMOS
RuTa
Selectively Pattern Ta on Ru
STINMOS PMOS
RuTa
STINMOS PMOS
RuTa
Selectively Pattern Ta on Ru
STINMOS PMOS
RuRu/Ta
Anneal to Form Alloy
STINMOS PMOS
RuRu/Ta
Anneal to Form Alloy
8
Figure 1.4: Replacement/Damascene Gate Dual Metal CMOS
Another process called fully silicided (FUSI) metal gate (Figure 1.5) has been
extensively investigated [61-70]. In this process, poly-Si is totally silicided with metals.
A FUSI metal gate has several advantages, including tunable work function and CMOS
compatible processing. Among common silicide systems reported, NiSi FUSI has been
shown to have the best work function tenability and stable silicide/gate oxide interface
[62-68]. The CoSi2 work function tuning is limited [69], while gate oxide integrity is
degraded when TiSi2 is used as a FUSI metal gate [63]. However, NiSi has the poorest
thermal stability among the three silicide systems [70]. Therefore, a metal wet etch based
deposition-etch-deposition integration system is more versatile and promising to explore
[44,47].
Figure 1.5: FUSI Dual Metal Gate CMOS
Poly Poly FUSI
Conventional Poly CMOS CMP to Expose Gate FUSI Gate Formation
PolyPoly PolyPoly FUSIFUSI
Conventional Poly CMOS CMP to Expose Gate FUSI Gate Formation
Poly
Fabricate Poly/ISSG CMOS and CMP to Expose Gate
Remove Poly/ISSG Deposit High-k and Metal Gate
MetalPolyPoly
Fabricate Poly/ISSG CMOS and CMP to Expose Gate
Remove Poly/ISSG Deposit High-k and Metal Gate
MetalMetal
9
Focused Integration Scheme
As the name implies, 1st metal deposition, selective etch and 2nd metal deposition
steps are performed sequentially. Figure 1.6 illustrates schematic process flow of this
approach. After depositing high-k, 1st metal is deposited. The 1st metal can be either
NMOS or PMOS metal. The selection of 1st metal is mainly determined by wet etch
compatibility. Masking process is required to selectively etch 1st metal. Photo resist is
only served as a mask during etching the hardmask selectively. Hardmask should have
good selectivity with 1st metal. Chemical reaction between hardmask and 1st metal should
also be avoided. Wet etch is preferred to etch 1st metal in order to reduce possible damage
on high-k from dry etch. After selective etching of 1st metal, the hard mask should be
removed. Since high-k is exposed, wet etch is also preferred in this step. Critical aspect of
this step includes wet etch selectivity between the hardmask and underlying high-k. After
this, 2nd metal will be deposited on top of 1st metal and high-k exposed. Selective etching
of 2nd metal on 1st metal is optional, but necessary if device characteristic is affected by
presence of 2nd metal on top of 1st metal.
Figure 1.6: Deposition-Etch-Deposition Based Dual Metal Gate CMOS
Hard Mask
1st MetalHigh-k
2nd Metal
Hard Mask
1st MetalHigh-k
2nd Metal
10
Motivation
Therefore, the learning curve is long and steep for developing the same (or a
better) level of etch selectivity and profile control for the metal gate compared to the
poly-silicon gate [45,46]. In addition, wet etch effects, issues and impacts in dual metal
gate CMOS fabrication, characteristics and reliability is also need to be studied.
To address all these issues properly, extensive in-depth research with specific
focus is a fundamental requirement. Dual metal gate CMOS is the ideal candidate to
replace the conventional CMOS. Successful integration of dual metal gate CMOS at sub-
50 nm node is a challenging issue for the researchers. Therefore, a comprehensive, in
depth research with specific focus on study of advanced fabrication processes for sub-50
nm CMOS has been carried out.
Approach
To achieve the goal, a methodical approach was set and followed. All the
experimental details and results have been systematically organized in the following
chapters.
Since, highly selective etch chemistries are required to successfully integrate the
dual metal gate CMOS, therefore, an effective and very selective wet etch module
development was the primary necessity. Hence, in chapter 1, metal wet etch process
development has been described in detail.
11
As the number of potential candidate gate metals is quite large, therefore the
whole integration process becomes more complex. Right combinations of high-k
dielectric film and hard mask to realize the practical device becomes challenging.
Therefore, not only wet etch solution development rather an optimized and simplified
module development became very important. Also, their effects on the integration have
important significance on device fabrication and performance. Therefore, in chapter 3,
optimized wet etch module development has been stated. Also, integration issues and
possible solutions have been discussed. Uniform, defect free film surface is an important
condition for higher mobility. In this chapter, film morphology has also been presented to
show the film uniformity, surface defect, roughness and particle detection with SEM,
AFM and Auger reports.
Chapter 4 presents a comparative study of the impact of metal wet etch process on
carrier mobility and metal gate/high-k device characteristics and reliabilities. A TaSiN
metal wet etch process highly selective to underlying HfO2 dielectric has been used to
conduct the experiment. The metal wet etch resulted in a slight degradation of the
electron mobility, however, not the hole mobility. It did not show any effect on the fast
transient charge trapping, and in fact resulted in improved NBTI and PBTI. All the
electrical results have been stated in this chapter.
Dry etch of metal gate with the presence of different varieties of candidate metals
is a complicated issue. Therefore, an experimental plan was set up to see whether wet
12
etch can replace dry etch. A TaSiN NMOS transistor was fabricated using the
conventional process flow. The only thing varied was the gate metal release. One split
was dry etched and the other one was wet etched. Performance variations due to these
two methods have been shown in chapter 5.
Since, the ultimate objective of this whole study is to demonstrate dual metal gate
CMOS on high-k dielectric films, therefore two different stacks were fabricated and their
electrical characteristics have been shown with physical structures in Chapter 6. Also, for
the first time a complete dual metal gate CMOS has been demonstrated on HfSiON
dielectric layer.
As deposited metals eventually go through subsequent high thermal budget
processes, therefore, as a complementary study, sheet resistance, refractive index and
extinction coefficient variations were also studied with annealed and un-annealed
conditions. Especially refractive index and extinction coefficient variation may introduce
errors in optical measurement of the film thickness. These results have been presented in
Chapter 7.
Finally in chapter 8, all the experimental results have been compiled with brief
discussion about the significant findings. Also, a concise comparative study has been
done with all the options for sub-50 nm dual metal gate CMOS fabrication. Lastly, a
summary of all the works and a direction for future research scope has been pointed out
in concluding chapter 9.
13
Chapter 2: Metal Wet Etch Process Development
This work is in support of the process integration for wet etch based dual metal
gate transistor structure. SEMATECH, Austin TX has funded these experiments and
Advanced Technology Development Facility (ATDF) class 1 clean room has been used
to perform them. Since the solutions need to be implemented in industry eventually, they
need to meet basic industry criteria. Etch rate, economy and environmental safety and
health issues (non-toxic, non-flammable and non-corrosive) are three of the more
important concerns. Therefore, choice of a chemistry with a fast but controllable etch
rate, mild in nature, economical and stable is essential. An additional factor for selection
of an appropriate chemistry is selectivity, where the chemistries would precisely remove
the metallic film without affecting the high-κ dielectric or remove the corresponding hard
mask without attack of the underlying metals and exposed high-κ. High-κ removal and
roughening must be minimized to ensure that device degradation did not occur. The
combination of all of these issues has made this a challenging project. Therefore, etch
rates were collected in ATDF’s class 1 clean room following the subsequent experimental
setup. At first 1 kÅ thermal oxide and then metals were deposited using relevant
deposition techniques. After that etching was performed for various chemistries at
different temperature. Etch time was varied and also etching was performed with
different time gaps to confirm the repeatability of the developed solutions. Spectroscopic
ellipsometry was used to measure the pre and post etch film thickness. Also, four-point
probe was used in possible cases to verify the sheet resistance and thus thickness.
14
Experimental
Materials
Different films being considered for metal gate electrodes were deposited on 200
mm wafers [10]. Process conditions are shown in Table 2.1. Deposition thicknesses were
100 Å for metal films and high-k dielectrics and 3000 Å for PETEOS.
Table 2.1. Process conditions for various film deposition
(“x” means data was not collected)
Deposition
Method
Tool Films Category♣ Power Temperature Pressure Flow
PVD Anelva TiN
Ta
TaN
TaSiN
Mid-gap
NMOS
Mid-gap
NMOS
100-
1000W
x 2E-04
Torr
Ar
3-50 sccm
ALD Aviza TaCN
TiN
HfO2
PMOS
High-k
x 350-500 ºC 1-2 Torr 50 sccm
700 sccm
CVD - TiSiN PMOS x 350 ºC x TDEAT+NH3
followed by
10 sec SiH4
Thermal
Oxidation
AMAT PETEOS Hard
mask
x 400 ºC x x
15
♣ NMOS = Below 4.4 eV
PMOS = Higher than 4.8 eV
Mid-gap = In between 4.4 eV to 4.8 eV
Chemistries
Standard fab chemicals SC1 (DI:H2O2:NH4OH), SC2 (DI:H2O2:HCl), HCl,
NH4OH, SPM (H2O2:H2SO4), H2O2 and HF were used for wet etch experiments.
Tools
Wet etches were performed in ATDF’s class 1 cleanroom using an FSI Mercury
OC processor (FSI), a Santa Clara Plastics 8400 wet bench (SCP), and a SEZ 203 spin
etcher (SEZ). Film thicknesses were measured using a four-point probe (Tencor
RS55TC) and a spectroscopic ellipsometer (Optiprobe Thermawave 5240).
Wet Etch Results
Detailed etch rate tables are shown in Tables 2.2 and 2.3. Heated SC1, SC2, and
SPM all etched ALD and PVD TiN aggressively, but SC1 showed the highest selectivity
to the high-k dielectrics and the hard mask. In contrast, HF (60:1) at 22 ºC etched the
HfSixOy and PETEOS films very fast (Table 2.2). The SC1 worked by continually
oxidizing and then etching the surface of the wafer, and dissolving the metals into
solution. The fluorine component of the HF attacked all the films.
16
Table 2.2. Etch Rates (Å/min) of Different Materials for Dual Metal CMOS Fabrication
(“x” means data was not collected)
Che
mis
try
Rat
io
Tem
p. (º
C)
PV
D T
iN♠
PVD
Ta
PVD
TaN
♠
PVD
TaS
iN
(Si-3
0%)
TEO
S
ALD
HfO
2
ALD
HfS
i xOy1
H2O2 13.4:1 60 x 0.74 0.68 0.96 0.71 0 0.1
SC1♣ 10:1.1:1 60 >10 0.81 6.6 >21 3 0.01 0.06
SC1 10:1.1:1 22 17.6 x x x 0.26 0 0.01
SC1 5:1.1:1 60 > 20 1.92 8.09 x 4.53 0.01 0.11
SC2 10:1.1:1 60 > 10 0.9 0.08 0.01 0.14 0.05 0.06
SPM 4:1 60 > 10 0.07 0.09 0 0 0.08 1.1
HCl 10:1 60 0.3 0.01 0.02 0.02 0.01 0 0.03
HF 1000:1 56 0.2 0 0 0.15 2.07 0.02 25.9
BHF 8:1 24 x 0.25 0.06 x 177 0 9.5
HF 50:1 60 1.32 4.2 0.03 33.6 247 0.12 > 32.4
HF 10:1 25 2.47 46 4.1 50.3 x 0.1 x
♣ A little higher ratio of H2O2 helps to minimize pitting created by NH4OH.
♠ TaN and TiN are stoichiometric. 1 Rutherford Backscattering Spectrum (RBS) analysis shows for HfSiO (20% Hf) the atomic concentration,
Depth Layer Thickness Atomic Concentration
(Å) (Å) O Si Zr Hf
< 110 100 68 10 0.1 22.0
Total Hf atoms/cm2 = 1.89e16
17
Table 2.33: Etch Rates of Different Materials for Dual Metal
CMOS Fabrication (all etch rates are in Å/min)
Che
mis
try
Rat
io
Tem
p. (º
C)
ALD
TiN
ALD
TaC
N
CV
D T
iSiN
PVD
TaS
iN
(75%
-Si)
SC1 10:1.1:1 22 8 x 6 x
SC1 5:1.1:1 60 x 9.8 x 7
NH4OH 10:1 60 0.0 0.12 1.1 0.06
SC1 (10:1.1:1) etched TaSiN (Si-30%) with an etch rate of more than 20Å/min at
60°C. As the concentration of Si was increased, TaSiN transformed into a silicon rich
silicon nitride film, and the etch rate decreased. The higher percentage of Si in TaSiN
required a more concentrated SC1 (Figure 2.1).
Figure 2.1: Variation of etch rate of TaSiN due to change in amount of silicon2
2 Depending on the process conditions, percentage of silicon was varied for different wafers. The
actual composition of TaSiN is where % of Si = 100*{y/(y+x)}. In the figure, for all TaSiN composition, N
05
10152025
20 40 60 80 100% of Si
Etch Rate (Å /min)
18
For pure metal Ta, SC1 showed a poor etch rate (0.8 Å/min). Higher Ta etch rates
of 46 Å/min were obtained by using HF (10:1) at 25 ºC.
Effects of Etch Chemistries on Film Surfaces
Short-loop test wafers with the TEOS hard mask and TaSiN (Si-30%) metal were
run to test and verify the effects of the wet etch chemistries on films. The exposed TaSiN
was etched using SC1 (10:1.1:1) at 60 ºC. The TaSiN was completely removed and only
15 Å of the remaining TEOS hard mask was etched (Figure 1.6 and 2.2).
Figure 2.2: A scanning electron microscope (SEM) image taken from a wafer after the
initial TEOS and then the exposed TaSiN wet etch. It can be seen that the TEOS/TaSiN
have a sharp edge and no recesses.
concentration was same. More explicitly N was 50% of the whole composition for any type of TaSiN.
Therefore, for Si=30%, TaSiN exact composition was Ta0.35Si0.15N0.5.
TEOS/TaSiN
HfO2
TEOS/TaSiN
HfO2
19
Figure 2.3 shows the final TaSiN surface after removal of the TEOS hard mask.
Atomic force microscopy (AFM) was employed to study the surface topography of the
TaSiN. The surface of the remaining TaSiN film after the final TEOS hard mask removal
was relatively smooth, with a Rrms3 = 1.81 Å.
Figure 2.3: AFM topography of TaSiN surface after TEOS hard mask removal. Vertical
axis shows the surface roughness.
Figure 2.4 presents AFM images of the HfO2 surface after the TaSiN etch and the
TEOS removal. The HfO2 film surface became smoother (Rrms = 1.69 Å) after the TEOS
hard mask was removed. This could be due to the HfO2 being slightly etched by the
diluted HF, which may have removed some sharp extrusions of HfO2 from the top
surface of the film.
3Rrms = Root Mean Square Roughness (square root of the sum of the squares divided by the number of points)
(b)(b)
20
Figure 2.4: AFM topography of HfO2 surface (a) after TaSiN wet etch and
(b) after final TEOS hard mask removal. Vertical axis shows the surface
roughness.
(a)(a)
(b)(b)
21
Initial Electrical Results of Practical Device Performance
To investigate the electrical impacts of metal wet etch and hard mask strips on the
underlying high-k dielectrics, an NMOS capacitor lot was used to simulate the metal wet
etch module processes. Deposited metal was etched away to expose the underlying
dielectric and then it was re-deposited to define the characteristics of the wet etch
process. For comparison, a reference sample was deposited but did not go through the
wet etch process and re-deposition. The gate dielectric studies included both ALD HfO2
and ALD HfSixOy (20% SiO2). All wafers had a poly silicon cap over metal and received
a 10-sec 1000 oC rapid thermal anneal (RTA) to activate the poly implant. The electrical
test results were consistent with the physical characterization study: HfO2 could tolerate
the HF wet etch processes used to remove the TEOS hard mask, but HfSixOy could not.
The capacitor fabricated with 20% HfSixOy dielectrics and subjected to the TEOS hard
mask process had much higher leakage current.
C-V and current voltage (I-V) were measured to study the electrical
characteristics of the HfO2 gate stacks. Each wafer was tested at five sites. The C-V and
J-V curves for the TaSiN metal with and without an extra TaSiN deposition and wet etch
removal with are shown in Figs. 2.5 and 2.6. All C-V and J-V curves behaved well; the
differences could be attributed to the slight equivalent oxide thickness (EOT) differences
of the underlying gate dielectrics. The EOT difference between the NMOS and PMOS
regions was 0.8 Å (13.6 vs. 12.8 Å), and the leakage current (Jg) difference was 3.6x.
22
Figure 2.5: C-V curves of TaSiN films on HfO2
Figure 2.6: J-V curves of TaSiN films on HfO2
Jg-Vg Curvs of HfO2/TaSiN with and Without Wet Processes
1.0E-10
1.0E-08
1.0E-06
1.0E-04
1.0E-02
1.0E+00
1.0E+02
1.0E+04
0 1 2 3 4 5 6Vg (-V)
Jg (A
/cm
2)
Without Wet Etch
With Wet Etch
CV Curves of HfO2/TaSiN with and without Wet Processes
0.0E+00
2.0E-11
4.0E-11
6.0E-11
8.0E-11
1.0E-10
1.2E-10
-2 -1.5 -1 -0.5 0 0.5 1Vg (V)
Cap
acita
nce
(F)
Without Wet Etch
With Wet Etch
Area = 5X10-5 cm2
Frequency = 100 KHz
CV Curves of HfO2/TaSiN with and without Wet Processes
0.0E+00
2.0E-11
4.0E-11
6.0E-11
8.0E-11
1.0E-10
1.2E-10
-2 -1.5 -1 -0.5 0 0.5 1Vg (V)
Cap
acita
nce
(F)
Without Wet Etch
With Wet Etch
Area = 5X10-5 cm2
Frequency = 100 KHz
23
Summary
This chapter reports the metal electrode wet etch process development for dual
metal gate CMOS. The developed chemistries have fast, controllable, uniform etch rates
and high selectivity to high-k dielectric and appropriate mask materials. Device
performance characteristics have shown well behaved C-V and J-V curves. New metal
electrode materials are under development as are appropriate chemistries suitable for use
in dual metal gate CMOS integration.
24
Chapter 3: Wet Etch Issues and Effects in Dual Metal Gate
CMOS Integration
This chapter discusses metal wet etch issues and their effects on high-k/metal
films in dual work function metal gate CMOS integration. In last chapter, a
comprehensive metal wet etch module has been demonstrated to successfully integrate
dual metal gate CMOS. Different high-k/metal films, combinations of films, etch
selectivity, thermal stability, interactions among the films, and finally surface conditions
have made the implementation of metal wet etch challenging. Here in this chapter,
representative results using HfO2, HfSiON, ISSG, TiN, Ta, TaSiN, TaCN, TiSiN,
amorphous silicon (α-Si) and TEOS in dual metal CMOS processing are presented.
Wet Etch Issues in Dual Metal Gate CMOS Integration
Since, a variety of metals were considered as potential candidate, attention was given
to finding a common metal wet etch chemistry and a common hard mask. Since, the
metal etch chemistry can potentially damage the dielectric layer thus its selectivity over
relevant films (dielectric and hardmasks both) was a bare necessity. Non heat-treated and
poly heat-treated high-k materials (HfO2 and HfSixOy) were tested with various wet etch
process. The poly heat-treated wafers went through either the single wafer RTP chamber
(at 620 °C) or the batch horizontal furnace (at 550 °C) poly temperature cycle without
actual poly deposition; they were only exposed to N2 gas. Whether or not it received a
25
poly heat treatment, the HfSixOy was rapidly etched by HF; but both the HfO2 and
HfSixOy were minimally etched by the metal wet etch chemistries (Table 3.1).
Table 3.1: Etch rates of various chemistries on different dielectric films
(All etch rates are in Å/min and at 60ºC)
Chemistry Composition Ratio HfO2 HfSiON RTP
PHT
HfO2
FUR
PHT
HfO2
RTP
PHT
HfSiON
FUR
PHT
HfSiON
ISSG
SC1 DI:NH4OH:H2O2 5:1.1:1 0.01 0.1 0 0 0.06 0.05 0.4
HF DI:HF 50:1 0.12 >32.24 0.35 0.36 31.71 31.76 x
In comparison to HF and other wet etch chemistries, SC1 was found to have high
selectivity to all of the tested high-k materials, ISSG and hard masks (Table 3.2).
Table 3.2: Etch selectivity of SC1 metal etch over dielectric film etch
Metal Ratio Temperature
(ºC)
HfO2 HfSiON ISSG
PVD TiN 10:1.1:1 22 1760:1 176:1 44:1
PVD TaN 5:1.1:1 60 800:1 80:1 20:1
PVD TaSiN 5:1.1:1 60 700:1 70:1 17:1
ALD TiN 10:1.1:1 22 800:1 80:1 20:1
ALD TaCN 5:1.1:1 60 980:1 98:1 24:1
CVD TiSiN 10:1.1:1 22 600:1 60:1 15:1
26
However, ISSG/metal gate stack processing showed enhanced ISSG etch rate with
concentrated SC1 at elevated temperature. Metal oxide formation at the interface might
be the potential reason behind this enhanced etch rate.
Based upon the high selectivity and effectiveness, SC1 was the first chemistry
screened for metal wet etches. Additional efforts were made to optimize different
concentrations of SC1 at various temperature conditions in an attempt to keep SC1 as a
unique etch chemistry for most of the metals [72].
Although initial experiments used a TEOS hardmask, it was found TEOS was
ineffective as a hard mask. It was easily etched if HF was used as the metal etch
chemistry, and the underlying HfSiON films were attacked when it was removed with
HF. Therefore, integrating a gate stack of Ta/HfSiON becomes challenging. HfO2 shows
an etch rate of 1.04 Å/min. Concentrated HF (10:1) at 22 ºC is required to etch Ta,
removing a substantial amount of TEOS as well.
One potential substitute that was tested as a hard mask was α-Si. After extensive
experimentation, it was found that am-Si could be etched with 29% NH4OH (10:1) at
60ºC with an average etch rate of 80 Å/min in the FSI spray tools. When NH4OH‘s etch
selectivity was tested on all the candidate high-k/metals, it was found to be a highly
selective for all of them (Table 3.3).
27
Table 3.3: Etch rates of 29% NH4OH (10:1) at 60 ºC on different films.
Film Etch Rate
(Å/min)
PVD TaN 0.1
ALD Ta(C)N 0.12
PVD TiN 0.06
ALD TiN 0
CVD Ti(Si)N 1.1
PVD Ta 0
PVD TaSiN 0.2
α-Si 70
HfO2 0.1
HfSiON 0.13
RTP PHT HfO2 0
FUR PHT HfO2 0.1
RTP PHT HfSiON 0
FUR PHT HfSiON 0.1
ISSG 0.3
During the α-Si hard mask integration characterization, the following issues were
discovered:
1) Plasma etch of the thin a-Si (400 Å) stopping on metal resulted in severe
oxidization of the metal (Figure 3.1a);
28
2) Metal wet etch undercut the photoresist at least by 150 nm (Figure 3.1b).
3) After NMP removal of the photoresist, corrosion of a-Si was observed (Figure
3.1c).
Figure 3.1: Initial issues during α-Si dry etch process development, (a) plasma etch of
the thin α-Si stopping on TaSiN resulted in severe oxidization of metal after the process;
(b) with wet etch, there was ~150nm undercut of photoresist; (c) after NMP removal of
the photoresist, corrosion of α-Si was observed.
Oxide
Photoresist
AmS TaSiN
Undercut
TaSiN AmSiCorrosion
(a)
(b)
(c)
29
Therefore, a new plasma etch process was developed that used no oxygen. To avoid
oxidation of the metal layer, an NH3 ash process was followed by an NMP clean process.
This new process etches out the exposed α-Si hardmask and stops on the metal, leaving
the photoresist and the hardmask unaffected (Figure 3.2).
Figure 3.2: New dry etch process for α-Si removal, (a) leaves photoresist intact; (b)
shows (i) nice smooth edge, (ii) smooth metal surface and (iii) no undercutting of the
hardmask.
Photoresist
(i)
(ii) (iii)
(a)
(b)
30
However, because native oxide is easily grown on α-Si after brief exposure to the
environment, α-Si surfaces needs to be pre-cleaned with HF. But during this process HF
can etch out the already exposed metal. Hence, SC1 (10:1.1:1) at 60 ºC was optimized as
a relatively benign pre-cleaner. However, for a tungsten/α-Si, gate stack, it was found
that SC1 etched tungsten at more than 20 Å/min. Therefore, instead of SC1, HF was used
because it did not etch tungsten and performed the pre-cleaning without problems.
The choice of first metal is also delicate. For example, for one of the gate stacks, a
PMOS material (TaCN) was deposited before the NMOS material (TaSiN-90% Si).
Because, etching TaSiN (with 90% Si) requires a more concentrated SC1 for a longer
etch time [29,46]. TaCN was first deposited and etched with a lower concentration SC1
to make it cost and production effective. Another issue is, silicon penetration into the
TaSiN during the high-temperature α-Si deposition, making it relatively Si rich (Figure
3.3). This impedes the etching. Annealing can also reduce the etch rate, although
different annealing temperatures do not have significant impact on etch rate [73].
However, this result suggests that consecutive high-temperature processing might anneal
the metal somewhat, thereby reducing etch rate.
Because concentrated chemistries need more chemicals, the etch chemistries were
optimized, to make them both effective and economically attractive. For instance,
although TaCN can be etched with SC1 (2:1.1:1) at 10.5 Å/min, SC1 (5:1.1:1) was
chosen with an etch rate of 9.8 Å/min.
31
Figure 3.3: SIMS analysis done on PVD TaSiN (Si 90%)/20 Å HfO2/Si substrate is
shown. Ta+N signal fades toward TaSiN surface exponentially, whereas Si+N signal is
relatively constant across the film. Si signal is high across the film, indicating that
significant intrusion of poly Si. Such phenomenon would affect the etch rate.
1E+00
1E+01
1E+02
1E+03
1E+04
1E+05
1E+06
0 5 10 15 20 25
Depth (nm)
Cou
nts/
sec
12C18O29Si29Si+14N29Si+16O2181Ta+14N181Ta+16O181Ta+28Si180Hf+16O2
TaSiN HfO2
32
Wet Etch Effects in Dual Metal Gate CMOS
Smooth film surface is good for reduced gate leakage, greater reliability, and
higher mobility. Therefore, after every etch step film surfaces were carefully studied
using atomic force microscopy (AFM), Auger, and scanning electron microscopy (SEM).
Three different films (PVD TaSiN, ALD TaCN and CVD TiSiN) have been tested with
SC1 for this experiment.
SEM image of a fully processed TaSiN patterned wafer shows that the metal wet etch
did not undercut the α-Si hard mask from any of the films (Figure 3.4).
Figure 3.4: Metal (PVD TaSiN) wet etch does not etch or undercut the α-Si hard
mask.
AFM of the high-k surface confirms the underlying high-k dielectric surface is
smooth (Figure 3.5). The samples were analyzed using Digital Instruments Nanoscope III
33
with a Dimension 5000 Multimode AFM in tapping mode. In-line thermal wave
measurement was employed to measure the metal film thickness before and after the
metal wet etch. The complete removal of metal from the intended regions was ensured
by 20% over etch. One wafer was pull out of line after the metal wet etch process and
submitted for Auger analysis.
Figure 3.5: AFM image of high-k surface, after TaSiN removal by wet etching,
shows it was smooth. Ra value was 0.115 nm for 1 micron image.
Auger analysis was carried out with the PHI 670 FE-Auger using a 10 keV 10 nÅ
electron beam. The depth profile was obtained by alternately acquiring data in the
spectral regions of interest and removing the top layer of material by sputtering with a 3
keV Ar ion beam rastered over a 5 x 5 mm2 area. Under these sputter conditions 20 Å of
34
SiO2 was removed per minute. Approximate atomic concentrations (%) were calculated
from the dN(E)/dE multiplexed data (signal averaging in the spectral regions of interest)
using standard-less sensitivity factors. The surface Auger analysis confirmed the
complete removal of TaSiN from the PMOS region. The Auger spectra taken from one
center die and one edge die are shown (Figure 3.6), and the atomic percentages of various
elements are also listed (Table 3.4). It was seen that HfO2 was exposed all the way to the
surface and no more than half monolayer of TaSiN residues was present on the HfO2 gate
dielectric.
Figure 3.6: Surface Auger spectra taken from the PMOS region after the TaSiN wet etch
Table 3.4: Atomic percentage of various elements obtained by surface Auger analysis
after TaSiN(90% Si) wet etch. The TaSiN residue is estimated to be less than half
monolayer.
500 1000 1500 20000
1
2
3
4
5
6
7
8
9
10
O
C
Hf Hf HfHf
HfHf
HfF
Hf
N
Ta Ta TaTaTa
TaTa
Ta
SiSi
Center
Notch
4120204- 15
AES Sur vey PC 13 Jan 05 Area: 1 Acq Time: 15.53 min File: 0112084 4120204-15 N otch P-Plus Scale: 394.118 kc/s Offset: -2075.036 kc/s Ep: 10.00 kV Ip: 9.212e-09A
Kinetic Energy (eV)
N(E
)*E,
smo9
,ndi
ff9
500 1000 1500 20000
1
2
3
4
5
6
7
8
9
10
O
C
Hf Hf HfHf
HfHf
HfF
Hf
N
Ta Ta TaTaTa
TaTa
Ta
SiSi
Center
Notch
4120204- 15
AES Sur vey PC 13 Jan 05 Area: 1 Acq Time: 15.53 min File: 0112084 4120204-15 N otch P-Plus Scale: 394.118 kc/s Offset: -2075.036 kc/s Ep: 10.00 kV Ip: 9.212e-09A
Kinetic Energy (eV)
N(E
)*E,
smo9
,ndi
ff9
35
Same experiments were run for fully processed ALD TaCN and CVD TiSiN
patterned wafers. In the next stage of the experiment, the α-Si hardmask was removed
from an ALD TaCN wafer using 29% NH4OH (10:1) at 60ºC. SEM images show that the
hardmask was completely removed without affecting either the underlying metal or the
high-k (Figure 3.7).
Figure 3.7: SEM image indicates that final α-Si hardmask wet etching process from
an ALD TaCN wafer removes the hardmask without affecting the required metal and the
already exposed high-k dielectric film.
AFM of the high-k confirms the smoothness of the surface. Ra is 0.123 nm (Figure
3.8). Auger analysis done of the high-k surface, after final hardmask removal from a fully
processed TiSiN patterned wafer confirms that 26% Hf and 62% O2 are present.
Therefore, exposed high-k is unaffected by the hardmask removal process. The 1% Si,
1%N, and <0.4% Ti indicate that the metal is completely removed.
36
Figure 3.8: AFM image of high-k dielectric film, after final hardmask wet etching from a
CVD TiSiN indicates high-k surface was smooth.
Summary
From these observations, it can be seen that the developed chemistries can
successfully remove the metals (invariable to the deposition method) without affecting
the underneath high-k dielectric film, required metal and the hard mask. Also, the film
surfaces are smooth. In addition, some integration issues have been identified and their
possible solutions have been recommended too.
37
Chapter 4: Impact of Wet Etch on Dual Metal Gate CMOS
Performance and Reliability
In the deposition-etch-deposition based versatile method for dual metal gate
CMOS integration, the first metal is selectively etched from either NMOS or PMOS
region before depositing the second metal. In chapter 2 and 3, it has been shown that,
metal wet etch processes highly selective to HfO2 and HfSiON high-k dielectrics have
been developed, and SC1 has been identified as a suitable wet chemical for a number of
metal gate materials. Utilizing this selective metal wet etch process, dual metal
gate/high-k CMOS transistors with gate length down 85 nm have been successfully
fabricated which will be shown in chapter 8. The effects of HfO2 exposure to wet
chemical HCl on NMOS Vt and electron mobility have also been reported [74]. However,
detailed studies of the impact of metal deposition plus metal wet etch on transistor
characteristics, especially on device reliabilities, was lacking. Therefore in this chapter, a
comparative study of the effects of TaSiN metal wet etch on carrier mobility, transient
charge trapping, and NBTI and PBTI in TiN/HfO2 CMOS transistors have been
presented.
38
Experimental
Experiments were designed to simulate the impact of metal wet etch on HfO2 gate
dielectric in a dual metal gate CMOS integration process flow (Figure 1.6). A chemical
oxide ~1 nm thick was first grown on a (100) Si substrate. 2 nm of HfO2 was deposited
by an Atomic Layer Deposition (ALD) technique, followed by NH3 post-deposition
anneal at 700 oC for 30 sec. A reactive physical vapor deposition (PVD) process was used
to deposit 10 nm TaSiN, which would serve as the first metal gate in a dual metal gate
CMOS flow. TaSiN was then wet etched using SC1 (5:1.1:1) at 60 oC. In one split, the
length of the metal wet etch was targeted for a complete removal of the TaSiN plus 10%
over etch. In another split, a much longer over etch time (50%) was used. The exposed
HfO2 was then rinsed in NH4OH (10:1) to simulate the removal of the α-Si hard mask.
Next, TiN 10 nm in thickness was deposited by ALD technique, which would be the
second metal in a dual metal gate CMOS flow, capped with 100 nm α-Si cap. A plasma
etch process was used to etch the gate stack. Other process steps are the same as those in
a conventional poly/SiO2 baseline CMOS flow.
To differentiate the impact of wet chemical exposure from the effects of metal
deposition and metal wet etch, in another experimental split, TaSiN metal deposition was
skipped, however, the HfO2 was exposed to SC1 and NH4OH wet chemicals before the
deposition of the ALD TiN metal gate. As a comparison, control TiN/HfO2 CMOS
transistors without the metal deposition and wet chemical exposures were also fabricated.
39
Results and Discussion
Since PVD deposition of the first metal generally results in larger damage to the
underlying high-k dielectrics than CVD and ALD techniques, the results from this
experiment would be close to the worst case scenario. Because both NMOS and PMOS
transistors were studied, ALD TiN, which has a mid-gap work function, was chosen as
the second metal gate material.
EOT and Jg
In chapter 8, it will be shown that the metal wet etch resulted in ~0.7 Å effective
oxide thickness (EOT) loss in TaSiN/HfO2 stack. Even though this is a small EOT loss,
considering the very high selectivity of SC1 and NH4OH to HfO2, it is puzzling which
process step results in such an EOT loss. Figure 4.1 shows the CV characteristics
measured on 1X10-5 cm2 NMOS overlap capacitors.
Figure 4.1: CV characteristics measured on 1X10-5 cm2 NMOS overlap capacitors
0.0E+00
2.0E-11
4.0E-11
6.0E-11
8.0E-11
1.0E-10
1.2E-10
1.4E-10
-2 -1.5 -1 -0.5 0 0.5 1
Contro l
Wet Chemical Only
10% Over Etch50% Over Etch
Gate Bias (V)
Cap
acita
nce
(F)
0.0E+00
2.0E-11
4.0E-11
6.0E-11
8.0E-11
1.0E-10
1.2E-10
1.4E-10
-2 -1.5 -1 -0.5 0 0.5 1
Contro l
Wet Chemical Only
10% Over Etch50% Over Etch
Gate Bias (V)
Cap
acita
nce
(F)
40
The EOT is 1.14 nm, 1.12 nm, 1.05 nm, and 10.4 nm for the control device, the
device received wet chemical exposures only, the device received 10% over etch, and the
device received 50% over etch, respectively. These results confirm that SC1 wet etch
process itself has very high selectivity to the underlying HfO2. Most of the EOT loss for
the device received TaSiN wet etch is not due to the high-k thickness loss during the
metal over etch. Instead, the most of the EOT loss (~0.7 Å) is likely resulted from the
loss of a TaSiN/HfO2 interface layer at the end of the TaSiN wet etch. The wet etch
chemical exposure by itself did not result in any Vfb shift, however, the TaSiN deposition
and wet etch led to a small Vfb shift compared to the control device (from -0.55 V and -
0.57 V).
The gate leakages of all devices are consistent with their EOT’s (Figure 4.2). At
Vg = Vfb-1V, Jg increased by 4.4-4.8X for the devices received TaSiN wet etch compared
to the control device. These results are consistent with what we reported before. The Jg
vs. EOT scaling is below the normal Jg vs. EOT trend line for HfO2 dielectrics [75, 76],
confirming that no extra leakage mechanisms were introduced by the metal wet etch
process.
Figure 4.2: Accumulation Jg vs EOT for the devices shown in Figure 21
1.0E-01
1.0E+00
1.0E+01
1.0E+02
1.0E+03
1 1.05 1.1 1.15 1.2EOT (nm)
J gat
Vg
= V f
b–
1V (A
/cm
2 ) SiO2 Model
1.0E-01
1.0E+00
1.0E+01
1.0E+02
1.0E+03
1 1.05 1.1 1.15 1.2EOT (nm)
J gat
Vg
= V f
b–
1V (A
/cm
2 ) SiO2 Model
EOT (nm)
J gat
Vg
= V f
b–
1V (A
/cm
2 ) SiO2 Model
41
Transistor Characteristics
The within-wafer distributions of linear Vt of NMOSFET and PMOSFET are
shown in Figure 4.3. It can be seen that the Vt distribution is not degraded by the metal
wet etch, indicating a uniform metal wet etch process across the wafer. For NMOSFET,
the metal wet etch resulted in a negligible Vt shift, because the effects of the small
negative Vfb shift and the slightly thinner EOT cancel etch other. For PMOSFET, the
metal wet etch led to ~20 mV reduction in the linear Vt.
Figure 4.3: Within-wafer Distribution of linear Vt of transistors: (a) NMOSFET,
and (b) PMOSFET
Figure 4.4 illustrates the Id-Vg curves of NMOSFET and PMOSFET. The Id-Vg
curves of all four splits almost overlap with each other. The sub-threshold slope is ~ 69
mV/dec for NMOSFET and ~70 mV/dec for PMOSFET, respectively. The metal wet
etch did not show any effect on sub-threshold slope, indicating that the TaSiN deposition
and wet etch did not significantly affect the quality of the high-k/Si interface.
0102030405060708090
100
0.55 0.60 0.65 0.70 0.75
Control
Wet Chemical Only
10% Over Etch
50% Over Etch0
102030405060708090
100
-0.90 -0.80 -0.70 -0.60
Control
Wet Chemical Only
10% Over Etch
50% Over Etch
(a) (b)
Linear Vt (V) Linear Vt (V)
Pro
babi
lity
(%)
0102030405060708090
100
0.55 0.60 0.65 0.70 0.75
Control
Wet Chemical Only
10% Over Etch
50% Over Etch0
102030405060708090
100
-0.90 -0.80 -0.70 -0.60
Control
Wet Chemical Only
10% Over Etch
50% Over Etch
(a) (b)
Linear Vt (V) Linear Vt (V)
Pro
babi
lity
(%)
42
Figure 4.4: ID-VG curves transistors. The Sub-threshold slope is ~69 mV/dec for
NMOSFET and ~70 mV/dec for PMOSFET.
Figure 4.5 shows the charge pumping results measured on NMOSFET. The wet
chemical exposure only and the longer over etch time do not increase the interface trap
density, however, the metal deposition and metal wet etch increase the Nit by ~30%. This
Nit increase could be related to the TaSiN PVD deposition, which can have a negative effect
on the interface trap density.
Figure 4.5: Charge pumping results measured on NMOSFETs
0.0 1.0 2.0
Contro l
Wet Chemical Only10% Over Etch50% Over Etch
1.0E-131.0E-121.0E-111.0E-101.0E-091.0E-081.0E-071.0E-061.0E-051.0E-041.0E-03
-2.0 -1.0 0.0Gate Bias (V)
Dra
in C
urre
nt (A
)
PMOS NMOS
|Vds|= 50 mV
0.0 1.0 2.0
Contro l
Wet Chemical Only10% Over Etch50% Over Etch
1.0E-131.0E-121.0E-111.0E-101.0E-091.0E-081.0E-071.0E-061.0E-051.0E-041.0E-03
-2.0 -1.0 0.0Gate Bias (V)
Dra
in C
urre
nt (A
)
PMOS NMOS
|Vds|= 50 mV
0.0E+00
5.0E+09
1.0E+10
1.5E+10
2.0E+10
-1.5 -1 -0.5 0
Contro l
Wet Chemical Only
10% Over Etch
50% Over Etch
Gate Bias (V)
Nit (c
m-2
)
0.0E+00
5.0E+09
1.0E+10
1.5E+10
2.0E+10
-1.5 -1 -0.5 0
Contro l
Wet Chemical Only
10% Over Etch
50% Over Etch
Gate Bias (V)
Nit (c
m-2
)
43
Electron and Hole Mobility
Figure 4.6 (a) and (b) show the electron and hole mobility measured by DC
technique.
Figure 4.6: (a) Electron mobility, and (b) Hole mobility measured by DC
technique
For NMOSFET, the wet chemical exposure only has a negligible effect on
electron mobility, however, the TaSiN deposition and wet etch degrades both peak
mobility and high-field mobility. At Eeff = 1 MV/cm, the high-field electron mobility
decreases from 200 cm2/V-sec for the control device to ~188 cm2/V-sec for the devices
received the metal wet etch. For PMOSFET, the effects of the TaSiN deposition and wet
etch on hole mobility are negligible. The device received wet chemical exposure only in
fact shows slightly improved peak hole mobility and high-field hole mobility. The
0
10
20
30
40
50
60
70
80
2.0E+05 6.0E+05 1.0E+06 1.4E+06 1.8E+06
ControlWet Chemal Only10% Over Etch50% Over EtchHole Univeral
0
50
100
150
200
250
300
350
400
2.0E+05 6.0E+05 1.0E+06 1.4E+06 1.8E+06
ControlWet Chemal Only10% Over Etch50% Over EtchElectron Univeral
(a)
Effective Field (V/cm)
Ele
ctro
n M
obilit
y (c
m2 /V
-sec
)H
ole
Mob
ility
(cm
2 /V-s
ec)
(b)
0
10
20
30
40
50
60
70
80
2.0E+05 6.0E+05 1.0E+06 1.4E+06 1.8E+06
ControlWet Chemal Only10% Over Etch50% Over EtchHole Univeral
0
50
100
150
200
250
300
350
400
2.0E+05 6.0E+05 1.0E+06 1.4E+06 1.8E+06
ControlWet Chemal Only10% Over Etch50% Over EtchElectron Univeral
(a)
Effective Field (V/cm)
Ele
ctro
n M
obilit
y (c
m2 /V
-sec
)H
ole
Mob
ility
(cm
2 /V-s
ec)
(b)
44
degradation of the electron mobility by metal deposition and metal wet etch processes is
coincident with the increased Nit for the devices received metal wet etch process. Since
the hole mobility is generally less sensitive to the interface quality than the electron
mobility, it is not surprising that the TaSiN metal wet etch does not impact the hole
mobility. These results imply that n-type metal should be deposited first in the dual metal
gate CMOS fabrication so that only PMOS portion will undergo the metal wet etch
process.
Fast Transient Charge Trapping
For high-k devices, the transient charge trapping is an important parameter
because it not only leads to Vt instability but also distorts the mobility extraction in a
conventional DC measurement technique [77, 78]. In this work, a pulse measurement
technique [77, 78] was employed to study the impact of the metal wet etch on the fast
transient charge trapping characteristics of the HfO2 gate dielectrics. The follows are the
measurement conditions: the pulse rise and fall times = 5 μs, the pulse width = 100 μs,
Vds = 100 mV, and Vg is swept between –1 V and 1.8 V. Figure 4.7(a) presents the pulse
Id-Vg curve of the control NMOSFET. The pulse Id-Vg cures of all other splits are
similar. Very small hysterias was observed, indicating little fast transient charging for all
HfO2 devices. Figure 4.7(b) illustrates the normalized Id during the pulse Vg stress.
Again, negligible Id drop was observed for all devices. These results indicate that the 20
Å HfO2 high-k dielectric is essentially charge trapping free during the fast pulse
measurement. The TaSiN deposition and wet etch and the wet chemical exposure did not
45
create extra bulk charge traps in the HfO2 dielectric and therefore did not change its fast
transient charge trapping characteristics.
Figure 4.7: (a) A representative pulse Id-Vg curve of NMOSFET. (b)
Normalized Id during pulse voltage stress.
PBTI
The Vt instability is one of the most important reliability parameters in high-k
transistors. The Vt instability under positive bias stress (PBTI) has been found to be
more sever than conventional SiO2 gate dielectric [79, 80]. It is believed that PBTI is due
to the filling of the pre-existing bulk traps in high-k dielectrics [77]. In this work, PBTI
0.0E+00
2.0E-04
4.0E-04
6.0E-04
8.0E-04
1.0E-03
1.2E-03
-1 -0.5 0 0.5 1 1.5 2
(a)
Gate Bias (V)
Dra
in C
urre
nt (A
)
4.0E-05 8.0E-05 1.2E-04 1.6E-04
Control
Wet Chemical Only
10% Over Etch
50% Over Etch
(b)
Stress Time (sec)
Nor
mal
ized
I d (a
.u.)
0.0E+00
2.0E-04
4.0E-04
6.0E-04
8.0E-04
1.0E-03
1.2E-03
-1 -0.5 0 0.5 1 1.5 2
(a)
Gate Bias (V)
Dra
in C
urre
nt (A
)
4.0E-05 8.0E-05 1.2E-04 1.6E-04
Control
Wet Chemical Only
10% Over Etch
50% Over Etch
(b)
Stress Time (sec)
Nor
mal
ized
I d (a
.u.)
4.0E-05 8.0E-05 1.2E-04 1.6E-04
Control
Wet Chemical Only
10% Over Etch
50% Over Etch
(b)
Stress Time (sec)
Nor
mal
ized
I d (a
.u.)
46
was tested on NMOSFET. The stress condition was chosen as Eox = (Vg – Vt)/EOT = 9
MV/cm and temperature = 125oC. The total stress time was 2100 sec. After certain
stress time, a short Vg sweep was applied and the Vt was determined from the Id-Vg
curve. All samples were measured at exactly the same condition to allow a direct
comparison.
Figure 4.8: PBTI-induced Vt instability for NMOSFET with different process conditions
Figure 4.8 shows the impact of the metal wet etch processes on the PBTI-induced
Vt shift of HfO2 devices. Compared to the control device, the device received the wet
chemical exposure only shows slightly lower Vt instability, and the devices received
TaSiN metal wet etch show comparable and substantially lower Vt instability. After
2100 sec stressing, the ΔVt = 28 mV, 23 mV, 13 Mv and 12 mV for the control device,
the device received wet chemical exposure only, and the device received metal wet etch
plus 10% over etch, and the device received metal wet etch plus 50% over etch. These
results are consistent with the fast transient charging results measured by the pulse
measurement technique, confirming that the wet chemical exposure and the metal wet
1.0E-03
1.0E-02
1.0E-01
1 10 100 1000 10000
Contro lWet Chemical Only10% Over Etch50% Over Etch
Stress Time (sec)
ΔVt(V
)
1.0E-03
1.0E-02
1.0E-01
1 10 100 1000 10000
Contro lWet Chemical Only10% Over Etch50% Over Etch
Stress Time (sec)
ΔVt(V
)
47
etch do not introduce extra bulk charge traps in the HfO2 gate dielectric. Since the PBTI
generally improves with decreasing high-k thickness [75], the smaller PBTI’s for the
devices received wet chemical exposure and metal wet etch are likely due to their thinner
HfO2 physical thickness.
NBTI
Negative bias stress induced Vt instability (NBTI) has also been observed in Hf-
based high-k dielectrics [77]. It was found that NBTI in high-k devices is comparable to
SiO2 and SiON devices. Since the Hf-based high-k stack always has a SiO2 or SiON
bottom interface, it is believed that the same de-passivation of the oxide/Si interface and
subsequent proton diffusion are responsible for the NBTI in high-k devices [77].
Figure 4.9: NBTI-induced Vt instability for PMOSFET with different process
conditions
Figure 4.9 illustrate the NBTI-induced Vt instabilities measured on PMOSFET at
Eox = (⏐Vg – Vt⏐)/EOT = 9 MV/cm and temperature = 125 oC. The wet chemical
exposure did not show any effect on NBTI, while the metal wet etch resulted in slightly
1.0E-03
1.0E-02
1.0E-01
1 10 100 1000 10000
Contro lWet Chemical Only10% Over Etch50% Over Etch
Stress Time (sec)
ΔVt(V
)
48
improved Vt instabilities. The smaller NBTI for devices received metal wet etch again
could be associated with their reduced HfO2 thickness.
Summary
A comparative study of the impact of metal wet etch on TiN/HfO2 transistor
characteristics and reliabilities has been presented. It is found that most of the EOT loss
(~0.7 Å) of the HfO2 gate dielectric after metal wet etch is due to the loss of a
metal/dielectric interface layer at the end of the metal wet etch, while not due to an
inadequate selectivity of the metal wet etch chemistries to HfO2 dielectric. The metal wet
etch results in a small Vfb shift (~20 mV) and does not affect the sub-threshold slope.
The metal wet etch also leads to a small degradation in the electron mobility, however,
not the hole mobility. The reduced electron mobility is coincident with an increased
interface trap density (Nit). This negative effect can be avoided by depositing n-type
metal first in a dual metal gate CMOS flow so that the metal wet etch will be applied to
the PMOS portion. More importantly, the metal deposition and metal wet etch do not
increase the bulk trap density in HfO2 gate dielectric, and in fact result in improved NBTI
and PBTI.
49
Chapter 5: Promise of Gate Wet Etch
Plasma processes involved in the fabrication of advanced CMOS devices become
increasingly challenging. The increase in complexity comes from the introduction of new
materials as well as the decrease in feature dimension. Regarding to the fabrication
technology of ULSI devices, plasma processes are widely employed to transfer the
shrinking feature size successfully. However, the plasma process induced charging
damage was found to degrade the electric characteristic and reliability of gate dielectric
[81-87]. The effect of the damage on the wafer and consequently on the device depends
on the type of surface or material that is exposed to the plasma. The damage arises due to
(i) bombardment by high energy particles, (ii) unwanted chemical reactions, (iii) creation
of electron–hole pairs due to ultraviolet (UV) light, (iv) impurity deposition and
subsequent permeation, and (v) charge deposition in the dielectric film. Also, halogen
based dry etch chemistry to etch new metal gate or their alloys is extremely difficult. In
dual metal gate CMOS, presence of two different metals and may be of different
thicknesses have this task more complicated [88-89]. Therefore, an experimental plan
was set up to see whether wet etch can be used to reduce gate leakage. Since, the
developed wet etch module mostly depend on very weak chemistries and the module can
etch every potential metal with high selectivity over high-k dielectric films therefore a
possibility exists where wet etch can be used for gate etch.
50
Experimental
100 Å PVD TaSiN NMOSFET and TiN NMOSFET were fabricated on 25 Å
HfO2 and HfSiON dielectric films. TiN NMOSFET was used as an industry standard
reference NMOSFET. However, splits were made and the gate was etched either with
standard dry etch or with the developed wet etch module (Figure 5.1).
Figure 5.1: Gate etch of a TaSiN NMOSFET
Results and Discussions
All the transistors show well behaved C-V (Figure 5.2) and Id-Vg characteristics
(Figure 5.3). Inversion and accumulation capacitances are same, indicating elimination of
gate depletion effect. A little reduction in EOT in the wet etched devices can be attributed
to the wet etch mechanism (Table 5.1).
Poly-Si (1kÅ)PVD TaSiN Metal Gate (100Å)
High-k Dielectric (HfO2 and HfSiON)
Metal gate was etched withconventional dry etch or wet etch
Poly-Si (1kÅ)PVD TaSiN Metal Gate (100Å)
High-k Dielectric (HfO2 and HfSiON)
Metal gate was etched withconventional dry etch or wet etch
51
Figure 5.2: CV characteristics of 20 x 20 μm TaSiN NMOSFET
Figure 5.3: Id-Vg curves for various combinations of process and dielectric films for
TaSiN NMOS transitor
-2.00E-05
0.00E+00
2.00E-05
4.00E-05
6.00E-05
8.00E-05
1.00E-04
1.20E-04
1.40E-04
1.60E-04
1.80E-04
0 0.5 1 1.5 2 2.5
Vg [V]
Id [A
]
HfO2/TiNHfO2/TaSiN-DryHfO2/TaSiN-WetHfSiO/TaSiN-DryHfSiO/TaSiN-WetHfSiO/TiN
0.00E+00
1.00E-12
2.00E-12
3.00E-12
4.00E-12
5.00E-12
6.00E-12
7.00E-12
8.00E-12
9.00E-12
1.00E-11
-1 -0.5 0 0.5 1Voltage [V]
Cap
acita
nce
[F] HfO2/TiN
HfO2/TaSiN-DryHfO2/TaSiN-WetHfSiO/TaSiN-DryHfSiO/TaSiN-WetHfSiO/TiN
52
Table 5.1 EOT and Vfb
Gate Stack EOT (Å) Vfb (V)
HfO2/TiN 11.1 0.61
HfO2/TaSiN-Dry Etched 12.3 0.59
HfO2/TaSiN-Wet Etched 12.03 0.59
HfSiON/TiN 12.28 0.5
HfSiON/TaSiN-Dry Etched 13.06 0.55
HfSiON/TaSiN-Wet Etched 13.01 0.55
The Ig-Vg curves of accumulation portion of capacitor are shown in Figure 5.4.
Dry etched HfSiO-TaSiN devices show abnormal behavior.
Figure 5.4: Ig-Vg curve
1.00E-13
1.00E-12
1.00E-11
1.00E-10
1.00E-09
1.00E-08
1.00E-07
1.00E-06
1.00E-05
1.00E-04
-2 -1.5 -1 -0.5 0 0.5 1 1.5 2Vg [V]
Ig [A
]
HfO2/TiNHfO2/TiNHfO2/TaSiN-DryHfO2/TaSiN-DryHfO2/TaSiN-WetHfO2/TaSiN-WetHfSiO/TaSiN-DryHfSiO/TaSiN-DryHfSiO/TaSiN-WetHfSiO/TaSiN-WetHfSiO/TiNHfSiO/TiN
53
In Figure 5.5 it has been shown that fabricated NMOS showed normal Vt roll off,
indicating uniform fabrication process throughout all the channel lengths.
Figure 5.5: Vt roll off characteristics
However, the threshold voltage is the most sensitive parameter with respect to
oxide charging and interface damage and it is also one of the significant device
parameters that determine the yield of the device. A negative charge in the oxide will
shift the value of Vt in the positive direction, while a positive charge will change Vt
negatively. In Figure 5.6, it has been shown that the dry etched devices have a larger
positive Vt shift, implying a larger amount of electron trapping. This abnormally
excessive shift in Vt is due to charging damage during the plasma etching process [90].
In addition to the charging damage, a different kind of damage [87,91,92] known
as edge damage occurs in MOS transistors during gate etching. The thin oxide layer, as
well as the silicon substrate, around the poly gate edge is directly exposed to the plasma
4.00E-01
4.50E-01
5.00E-01
5.50E-01
6.00E-01
6.50E-01
7.00E-01
0 0.2 0.4 0.6 0.8 1 1.2
Lg [um]
Vt [V
]
HfO2-TiNHfO2-TaSiN-DryHfO2-TaSiN-WetHfSiO-TaSiN-DryHfSiO-TaSiN-Wet
54
during poly gate etching. The edge damage is expected to depend directly on the plasma
over etch time and on the plasma chemistry [93]. To study this damage, a bias
configuration (Vg = Vd and Vd = 0V) has been applied that becomes significant for
devices with direct tunnel gate oxides. In this case the gate leakage occurs uniformly
across the device area, which represents an additional leakage mechanism that is not
present in more conventional CMOS technology with thicker gate oxides (tox > 3 nm).
The leakage in Figure 5.7 must also be considered when analyzing the off-state power
consumption for devices with direct tunnel oxides.
Figure 5.6: Cumulative plot of threshold voltage in “as processed” HfO2/TaSiN
NMOSFETS
HfO2/ TaSiN D-E (2w )HfO2/ TaSiN W-E (2w )HfO2/TiN Control (2w )
Probability Chart - Lot(s): 5031404_N2 [L1]0.1 N-mos Vert. Extrapolated gate voltage
Threshold Voltage
Units (VOLTS)0.660.640.620.60.580.560.540.520.50.480.46
Pro
babi
lity
Dis
trib
utio
n (%
)
100
90
80
70
60
50
40
30
20
10
0
55
Figure 5.7: Gate leakage component for a device with a direct tunnel gate oxide. Arrows
indicate the direction of electron flow in an NMOS device.
This Ig is significantly higher in our dry etched NMOSFETs, mostly because of
plasma damage (Figure 5.8).
Figure 5.8: Ig at different channel length
Gate current @ Vg=Vt+0.85V, Vd=0V
1.00E-08
1.00E-07
1.00E-060 0.2 0.4 0.6 0.8 1
Lg (um)
Igat
e (A
)
HfO2/TiNHfO2/TaSiN-DryHfO2/TaSiN-WetHfSiO/TaSiN-DryHfSiO/TaSiN-WetHfSiO/TiN
56
Summary
A representative metal gate NMOSFET transistor was processed with dry and wet
etched gate profile. And the result clearly indicates that the gate etch has caused damage
and results in enhanced gate leakage and charge trapping. Besides this device
performance defect, dry etch is becoming challenging day by day because of the presence
of new metals or their alloys in complicated dual metal gate CMOS. On the other hand,
the developed wet etch module can be used to etch currently available all the potential
candidate gate metals. Therefore, is the undercutting caused by wet etch is controlled,
which may be possible because of the presence of weak chemistries, wet etch might be a
very good option for gate etch thus gate definition.
57
Chapter 6: Complete Dual Metal Gate CMOS Integration
This chapter presents the process module development results and well-behaved
dual metal gate CMOS transistors with Lg down 45 nm integrated on both 20 Å HfO2 and
30 Å HfSiON gate dielectrics. At first, dual Metal Gate CMOS using TaSiN (NMOS)
[29] and Ru (PMOS) [42] have been demonstrated with Lg down to 85 nm. Then thin
ALD TiN (NMOS) and ALD TaCN (PMOS) are chosen as dual metal gate candidates
with a work function separation larger than that of TaSiN and Ru to fabricate sub-50 nm
devices with well-behaved device characteristics.
Fabrication Process
The metal wet etch module (Figure 6.1) is incorporated into the conventional
CMOS flow to demonstrate TaSiN (NMOS) and Ru (PMOS) dual metal gate CMOS
transistors.
Figure 6.1: Outline of the dual metal gate CMOS fabrication utilizing a metal wet etch
module. Major challenges include: a) Selective wet etch of the 1st metal and the removal
of the hardmask without damaging the underlying high-k, and b) the plasma etch of the
dual metal gate stacks without breaking through the high-k dielectrics.
High-kα-Si
NMOSPMOS
1st Metal
HM Format ion
High-k
Metal Wet Et ch
NMOSPMOS
1st Metal2nd Metal
NMOSPMOS
Deposi t 2nd Metal Deposit Poly and Etch Gate
NMOSPMOS
High-kα-Si
NMOSPMOS
1st Metal
HM Format ion
α-Si
NMOSPMOS
1st Metal
HM Format ion
High-k
Metal Wet Et ch
NMOSPMOS
1st Metal
Metal Wet Et ch
NMOSPMOS
1st Metal2nd Metal
NMOSPMOS
Deposi t 2nd Metal
2nd Metal
NMOSPMOS
Deposi t 2nd Metal Deposit Poly and Etch Gate
NMOSPMOS
Deposit Poly and Etch Gate
NMOSPMOS
58
After the ALD deposition of 30 Å HfO2, 100 Å of TaSiN was deposited by a PVD
process, followed by the TEOS hardmask deposition. The PMOS region was then opened
using the Source/Drain implant mask, and TaSiN is wet etched using SC1. The remaining
TEOS hardmask is removed using a diluted HF. Next, 100 Å Ru electrode and 100 Å
TaN barrier layer are deposited using a PVD process, capped with 1000 Å α-Si. To have
an easier comparison between various metal gate/high-k transistors, other process steps
including the channel and source/drain implantation conditions are kept the same as those
in the poly/SiO2 baseline CMOS flow.
For the second set of device, after the ALD deposition of either 20 Å HfO2 or 30
Å HfSiON, 100 Å of TaCN is deposited by an ALD process, followed by the α-Si
hardmask deposition. The NMOS region is then opened using the S/D implant mask, and
TaCN is wet etched. The remaining α-Si hardmask is removed using a NH4OH solution.
Next, a thin TiN metal electrode is deposited using ALD process, capped with 1000 Å α-
Si.
Ru/TaSiN Dual Metal Gate CMOS Characterization
Figure 6.2 illustrates TEM pictures of the TaSiN/Ru/TaN and Ru/TaN metal gate
stacks. STEM EELS and EDS element scans across the gate stacks indicate that the
intermixing of various metal layers and high-k dielectrics is minimal even after the high-
temperature CMOS flow. The work function of TaSiN and Ru on HfO2 after 1000 oC 5
59
sec RTA, determined by an improved Vfb vs. EOT technique [94], is 4.45 eV and 4.64
eV, respectively.
Figure 6.2: Cross-section TEM pictures of (a) HfO2/TaSiN/Ru/TaN, and (b)
HfO2/Ru/TaN gate stacks.
Figure 6.3 presents the CV characteristics measured on 20 μm X 20 μm
transistors.
Figure 6.3: CV characteristics of dual metal gate CMOS transistors measured on
20 μm X 20 μm devices
5 nmSi Subst rat e
HfO2
TaN
Ru
TaSiN
(a)
10 nmSi Substrate
HfO2
Ru
TaN
Poly(b)Poly
5 nmSi Subst rat e
HfO2
TaN
Ru
TaSiN
(a)
10 nmSi Substrate
HfO2
Ru
TaN
Poly(b)Poly
012
3456
78
-1.75 -1.25 -0.75 -0.25 0.25 0.75 1.25 1.75
Cap
acita
nce
(pF)
Gate Bias (V)
PMOSFETTinv = 19.5Å
NMOSFETTinv = 20.4Å
012
3456
78
-1.75 -1.25 -0.75 -0.25 0.25 0.75 1.25 1.75
Cap
acita
nce
(pF)
Gate Bias (V)
PMOSFETTinv = 19.5Å
NMOSFETTinv = 20.4Å
60
The inversion oxide thickness (Tinv) difference between NMOS and PMOS is less
than 1 Å despite that the PMOS side went through TaSiN wet etch and TEOS hardmask
removal. The inversion capacitance matches well with the accumulation capacitance for
both NMOS and PMOS, indicating that the gate depletion effect has been eliminated with
the metal gates.
Figure 6.4 shows the Id-Vd characteristics of 10 μm X 0.1 μm transistors,
demonstrating well-behaved devices with physical gate length down to 85 nm.
Figure 6.4: Id-Vd characteristics of dual metal gate CMOS transistors (physical
gate length equals to 85nm)
The Id-Vg characteristics of long-channel devices are presented in Figure 6.5. The
sub-threshold slop (SS) is 72 mV/dec and 75 mV/dec for TaSiN NMOSFET and Ru
PMOSFET, respectively.
0
200
400
600
800
1000
1200
1400
-2.0 -1.0 0.00.0 1.0 2.0
|Vg-Vt|=0~1.5V
Step: 0.25V
PMOSFET NMOSFET
Drain Voltage (V)
Dra
in C
urre
nt (μ
A/μ
m)
0
200
400
600
800
1000
1200
1400
-2.0 -1.0 0.00.0 1.0 2.00
200
400
600
800
1000
1200
1400
-2.0 -1.0 0.00.0 1.0 2.0
|Vg-Vt|=0~1.5V
Step: 0.25V
PMOSFET NMOSFET
Drain Voltage (V)
Dra
in C
urre
nt (μ
A/μ
m)
61
Figure 6.5: Id-Vg characteristic of dual metal gate CMOS transistors
Both NMOSFETs and PMOSFETs exhibit stable Vt roll-off characteristics,
indicating a uniform device fabrication process across various channel lengths (Figure
6.6). The Vt values are consistent with the work functions of TaSiN and Ru on HfO2 gate
dielectrics after the high-temperature anneal. Further process optimizations will bring the
Vt down to a reasonable range.
Figure 6.6: Vt roll-off characteristics of dual metal gate CMOS transistors
1.E-131.E-121.E-111.E-101.E-091.E-081.E-071.E-061.E-051.E-041.E-031.E-02
-2.0 -1.0 0.00.0 1.0 2.0
PMOSFET NMOSFET
|Vds| = 1.2 Vand 50 mV
SS = 75 mV/dec SS = 72 mV/dec
Gate Voltage (V)D
rain
Cur
rent
(A)
1.E-131.E-121.E-111.E-101.E-091.E-081.E-071.E-061.E-051.E-041.E-031.E-02
-2.0 -1.0 0.00.0 1.0 2.0
PMOSFET NMOSFET
|Vds| = 1.2 Vand 50 mV
SS = 75 mV/dec SS = 72 mV/dec
Gate Voltage (V)D
rain
Cur
rent
(A)
0.0
0.2
0.4
0.6
0.8
-1.0-0.8-0.6-0.4-0.20.0
0.0 0.2 0.4 0.6 0.8 1.0
Satu
ratio
n V
t(V
)
Gate Length (μm)
TaSiN NMOSFET
Ru PMOSFET
0.0
0.2
0.4
0.6
0.8
-1.0-0.8-0.6-0.4-0.20.0
0.0 0.2 0.4 0.6 0.8 1.0
Satu
ratio
n V
t(V
)
Gate Length (μm)
TaSiN NMOSFET
Ru PMOSFET
62
Figure 6.7 presents the electron and hole mobility obtained by a pulse
measurement technique. At Eeff = 1 MV/cm, 83% and 76% of the universal mobility has
been achieved for the TaSiN/HfO2 NMOSFET and the Ru/HfO2 PMOSFET,
respectively.
Figure 6.7: Electron and hole mobility measured by the pulse technique, which
eliminates the charge trapping effect
To study the impact of metal wet etch processes on the reliability of the HfO2 gate
dielectrics, time dependence dielectric breakdown (TDDB) test is performed on the
TaSiN/HfO2 gate stack, with and without wet etch processes (Figure 6.8). With 10 year
lifetime, the extrapolated dielectric breakdown voltage decreases from -2.95 V to -2.75 V
for the wafer that underwent metal wet etch processes, and both are well above the
normal operating voltage. Again, the decrease in the breakdown voltage can be
completely attributed to the 0.8 Å EOT difference between the control wafer and the
0
50
100
150
200
250
300
350
400
0.0E+00 5.0E+05 1.0E+06
Mob
ility
(cm
2 /V-s
)
Effective Field (V/cm)
Electron Universal
Hole Universal
TaSiN NMOSFET
Ru PMOSFET0
50
100
150
200
250
300
350
400
0.0E+00 5.0E+05 1.0E+06
Mob
ility
(cm
2 /V-s
)
Effective Field (V/cm)
Electron Universal
Hole Universal
TaSiN NMOSFET
Ru PMOSFET
63
wafer undergone metal wet etch processes, indicating that the metal wet etch and TEOS
removal processes do not degrade the reliability of the HfO2 gate dielectrics.
Figure 6.8: Impact of TaSiN wet etch and TEOS hardmask removal on the TDDB of
HfO2 gate dielectrics
TiN/TaCN Dual Metal Gate CMOS Characterization
Figure 6.9 illustrates cross-section TEMs of the dual metal gate CMOS transistors
with Lg down to 45 nm.
Figure 6.9: TEM of dual metal gate CMOS: (a) Thin-TiN/HfSiON NMOSFET, Lg =
45 nm. (b) TiN/TaCN/HfSiON PMOSFET, Lg = 60 nm.
1.E+001.E+011.E+021.E+031.E+041.E+051.E+061.E+071.E+081.E+09
0.0 1.0 2.0 3.0 4.0 5.0
10 Year Lifetime
Gate Stress Voltage (-V)
Mea
n T
ime
to F
ailu
re (s
ec)
1.E+001.E+011.E+021.E+031.E+041.E+051.E+061.E+071.E+081.E+09
0.0 1.0 2.0 3.0 4.0 5.0
10 Year Lifetime
Gate Stress Voltage (-V)
Mea
n T
ime
to F
ailu
re (s
ec)
50 nm 50 nm
(a) (b)
50 nm 50 nm
(a) (b)
64
The HRTEMs of the dual metal gate stacks are shown in Figure 6.10, revealing that
the thin ALD TiN is continuous.
Figure 6.10: HRTEM of dual metal gate stacks: (a) Thin-TiN/HfSiON NMOSFET,
and (b) TiN/TaCN/HfSiON PMOSFET.
STEM EELS and EDS element scans across the PMOS gate stack show the evidence
of Ti diffusion into the TaCN (Figure 6.11), indicating that the high work function of
TaCN/TiN is likely due to the intermixing of these two metal layers [95].
Figure 6.11: STEM EELS and EDX element scans across the TiN/TaCN/HfSiON
PMOS gate stack. There is an evidence of Ti diffusion into the TaCN metal layer.
5 nmSiOx
HfSiON
C-Si
TiN
poly
(a)
5 nm
SiOx
HfSiON
C-Si
TiN
TaCN
poly(b)
5 nmSiOx
HfSiON
C-Si
TiN
poly
(a)
5 nmSiOx
HfSiON
C-Si
TiN
poly
(a)
5 nm
SiOx
HfSiON
C-Si
TiN
TaCN
poly(b)
5 nm
SiOx
HfSiON
C-Si
TiN
TaCN
poly(b)
Position (nm)2520151050
O EELSSi EELS N EELS Ti EELS
Ta EDXSHf EDXS
Inte
nsity
(a.u
.)
SiSiOxHfSiON
TaCN
TiN
Poly
Position (nm)2520151050
O EELSSi EELS N EELS Ti EELS
Ta EDXSHf EDXS
O EELSSi EELS N EELS Ti EELS
Ta EDXSHf EDXS
Inte
nsity
(a.u
.)
SiSiOxHfSiON
TaCN
TiN
Poly
65
Figures 6.12 and 6.13 show CV curves of the dual metal gate CMOS transistors on
HfSiON and HfO2, respectively, confirming that the gate depletions have been
eliminated. The thicker Tinv’s of PMOSFETs are due to the oxygen diffusion
from/through the TaCN layer [96], which can be prevented with an improved ALD
deposition process.
Figure 6.12: CV characteristics of dual
metal gate HfSiON CMOS transistors. The
thicker PMOS EOT is due to an un-
optimized ALD TaCN deposition process.
Figure 6.13: CV characteristics of dual
metal gate HfO2 CMOS transistors. The
thicker PMOS EOT is due to an un-
optimized ALD TaCN deposition process.
Figures 6.14 and 6.15 show the Id-Vd characteristics, demonstrating well-behaved
devices on both HfO2 and HfSiON with Lg down to 60 nm. The long-channel sub-
threshold slopes (SS) are ~65 mV/dec and ~72 mV/dec for thin-TiN NMOSFET and
TaCN/TiN PMOSFET, respectively, with no significant difference between HfSiON and
HfO2 devices (Figure 6.16).
0123456789
10
-1.75 -1.25 -0.75 -0.25 0.25 0.75 1.25 1.75
Cap
acit
ance
(pF)
Gate Bias (V)
PMOSFETTinv = 21.6 Å
NMOSFETTinv = 16.9 Å
0123456789
10
-1.75 -1.25 -0.75 -0.25 0.25 0.75 1.25 1.75
Cap
acit
ance
(pF)
Gate Bias (V)
PMOSFETTinv = 21.6 Å
NMOSFETTinv = 16.9 Å
0123456789
10
-1.75 -1.25 -0.75 -0.25 0.25 0.75 1.25 1.75
Cap
acit
ance
(pF)
Gate Bias (V)
PMOSFETTinv = 18.5 Å
NMOSFETTinv = 14.8 Å
0123456789
10
-1.75 -1.25 -0.75 -0.25 0.25 0.75 1.25 1.75
Cap
acit
ance
(pF)
Gate Bias (V)
PMOSFETTinv = 18.5 Å
NMOSFETTinv = 14.8 Å
66
Figure 6.14: Id-Vd characteristics of dual
metal gate HfSiON CMOS (Lg = 60 nm)
Figure 6.15: Id-Vd characteristics of dual
metal gate HfO2 CMOS (Lg = 60 nm).
Figure 6.16: Id-Vg characteristics of dual metal gate CMOS: HfO2 devices, and
HfSiON devices.
0
500
1000
1500
2000
2500
-1.5 -1.0 -0.5 0.00.0 0.5 1.0 1.5
|Vg-Vt|=0~1.5V
Step: 0.3V
PMOSFET NMOSFET
Drain Voltage (V)
Dra
in C
urre
nt (μ
A/μ
m)
0
500
1000
1500
2000
2500
-1.5 -1.0 -0.5 0.00.0 0.5 1.0 1.5
|Vg-Vt|=0~1.5V
Step: 0.3V
PMOSFET NMOSFET
Drain Voltage (V)
Dra
in C
urre
nt (μ
A/μ
m)
0
500
1000
1500
2000
2500
-1.5 -1.0 -0.5 0.00.0 0.5 1.0 1.5
|Vg-Vt|=0~1.5V
Step: 0.3V
PMOSFET NMOSFET
Drain Voltage (V)
Dra
in C
urre
nt (μ
A/μ
m)
0
500
1000
1500
2000
2500
-1.5 -1.0 -0.5 0.00.0 0.5 1.0 1.5
|Vg-Vt|=0~1.5V
Step: 0.3V
PMOSFET NMOSFET
Drain Voltage (V)
Dra
in C
urre
nt (μ
A/μ
m)
1.E-121.E-111.E-101.E-091.E-081.E-071.E-061.E-051.E-041.E-031.E-02
-2.0 -1.5 -1.0 -0.5 0.00.0 0.5 1.0 1.5 2.0
HfO2SS=66 mV/dec
|Vds| = 50 mV
HfO2SS=72 mV/dec
Gate Voltage (V)
Dra
in C
urre
nt (A
)
PMOSFET NMOSFET
HfSiONSS=71 mV/dec
HfSiONSS=64 mV/dec
1.E-121.E-111.E-101.E-091.E-081.E-071.E-061.E-051.E-041.E-031.E-02
-2.0 -1.5 -1.0 -0.5 0.00.0 0.5 1.0 1.5 2.0
HfO2SS=66 mV/dec
|Vds| = 50 mV
HfO2SS=72 mV/dec
Gate Voltage (V)
Dra
in C
urre
nt (A
)
PMOSFET NMOSFET
HfSiONSS=71 mV/dec
HfSiONSS=64 mV/dec
67
Figures 6.17 and 6.18 illustrate the Jg-Vg characteristics. The gate leakages are
consistent with their respective EOT.
Figure 6.17: Jg-Vg characteristics of dual
metal gate HfSiON CMOS transistors
Figure 6.18: Jg-Vg characteristics of dual
metal gate HfO2 CMOS transistors
Both NMOSFETs and PMOSFETs exhibit stable Vt roll-off characteristics, indicating
a uniform device fabrication process across various channel lengths (Figure 6.19).
Figure 6.19: Vt roll-off characteristics of dual metal gate CMOS transistors
1.E-061.E-051.E-041.E-031.E-021.E-01
1.E+001.E+011.E+02
-2.0 -1.5 -1.0 -0.5 0.00.0 0.5 1.0 1.5 2.0
NMOSFETEOT=13.4Å
PMOSFETEOT=18.0Å
Gate Voltage (V)
Gat
e Lea
kage
(A/c
m2)
1.E-061.E-051.E-041.E-031.E-021.E-01
1.E+001.E+011.E+02
-2.0 -1.5 -1.0 -0.5 0.00.0 0.5 1.0 1.5 2.0
NMOSFETEOT=13.4Å
PMOSFETEOT=18.0Å
Gate Voltage (V)
Gat
e Lea
kage
(A/c
m2)
1.E-061.E-051.E-041.E-031.E-021.E-01
1.E+001.E+011.E+021.E+03
-2.0 -1.5 -1.0 -0.5 0.00.0 0.5 1.0 1.5 2.0
NMOSFETEOT=11.4Å
PMOSFETEOT=15.1Å
Gate Voltage (V)
Gat
e L
eaka
ge (A
/cm
2 )
1.E-061.E-051.E-041.E-031.E-021.E-01
1.E+001.E+011.E+021.E+03
-2.0 -1.5 -1.0 -0.5 0.00.0 0.5 1.0 1.5 2.0
NMOSFETEOT=11.4Å
PMOSFETEOT=15.1Å
Gate Voltage (V)
Gat
e L
eaka
ge (A
/cm
2 )
0.00.20.40.6
0.8
-1.0-0.8-0.6-0.4-0.20.0
0.0 0.2 0.4 0.6 0.8 1.0
Thin-TiN/HfSiON NMOSFET
Thin-TiN/HfO2 NMOSFET
TiN/TaCN/HfSiON PMOSFETTiN/TaCN/HfO2 PMOSFETSa
tura
tion V
t(V
)
Gate Length (μm)
0.00.20.40.6
0.8
-1.0-0.8-0.6-0.4-0.20.0
0.0 0.2 0.4 0.6 0.8 1.0
Thin-TiN/HfSiON NMOSFET
Thin-TiN/HfO2 NMOSFET
TiN/TaCN/HfSiON PMOSFETTiN/TaCN/HfO2 PMOSFETSa
tura
tion V
t(V
)
Gate Length (μm)
68
The Vt values are consistent with the workfunctions of thin-TiN and TaCN/TiN on
high-k after the high-temperature anneal. Further process optimizations will bring the Vt
down to a reasonable range.
The Ion vs. Ioff characteristics of dual metal gate CMOS are shown in Figure 6.20. At
Ioff = 100 nA/μm, Ion = ~1000 μA/μm and ~400 μA/μm for NMOS and PMOS,
respectively. The dual metal gate CMOS device performances match those of their single
metal gate counterparts.
Figure 6.20: Ion vs. Ioff characteristics of dual metal CMOS transistors: HfO2
devices, and HfSiON devices.
Figures 6.21 and 6.22 present the electron and hole mobility on HfSiON and HfO2,
respectively. At Eeff = 1MV/cm, 87-88% of the universal mobility has been achieved for
both thin-TiN/high-k NMOSFETs and TiN/TaCN/high-k PMOSFETs.
1.E-02
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
0 200 400 600 800 1000 1200Ion (μA/ μm)
Ioff
(nA
/ μm
)
NMOS
PMOS
1.E-02
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
0 200 400 600 800 1000 1200Ion (μA/ μm)
Ioff
(nA
/ μm
)
NMOS
PMOS
69
Figure 6.21: Electron and hole mobility of
dual metal gate HfSiON CMOS measured
by DC technique. At Eeff = 1MV/cm, μe =
88% and μh = 88% of the universal
mobility.
Figure 6.22: Electron and hole mobility
of dual metal gate HfO2 CMOS measured
by DC technique. At Eeff = 1MV/cm, μe =
87% and μh = 88% of the universal
mobility.
Figure 6.23 illustrates the pulse measurement results of dual metal gate CMOS
transistors on HfO2, indicating that the transient charge trappings of the 20 Å HfO2 are
negligible.
Figure 6.24: Pulse measurement of dual metal gate HfO2 CMOS. The charge trappings in
dual metal gate HfSiON CMOS transistors are even smaller.
0
50100
150
200
250
300
350
400
2.0E+05 6.0E+05 1.0E+06 1.4E+06
Mob
ility
(cm2 /
V-s)
Effective Fiel d (V/cm)
Electron Universal
Hole Universal
Thin-Ti N/HfSiON NMOS
TiN/TaCN/HfSiON PMOS0
50100
150
200
250
300
350
400
2.0E+05 6.0E+05 1.0E+06 1.4E+06
Mob
ility
(cm2 /
V-s)
Effective Fiel d (V/cm)
Electron Universal
Hole Universal
Thin-Ti N/HfSiON NMOS
TiN/TaCN/HfSiON PMOS 0
50
100
150
200
250
300
350
400
2.0E+05 6.0E+05 1.0E+06 1.4E+06
Thin-Ti N/HfO2 NMOS
TiN/TaCN/HfO2 PMOS
Mob
ility
(cm2
/V-s
)
Effective Fi eld (V/cm)
Elect ron Universal
Hole Univers al
0
50
100
150
200
250
300
350
400
2.0E+05 6.0E+05 1.0E+06 1.4E+06
Thin-Ti N/HfO2 NMOS
TiN/TaCN/HfO2 PMOS
Mob
ility
(cm2
/V-s
)
Effective Fi eld (V/cm)
Elect ron Universal
Hole Univers al
0.000.050.100.150.20
0.250.300.350.40
-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0Gate Voltage (V)
Dra
in C
urre
nt (m
A)
tr tf
tw
tr , t f = 5 μsTw = 100 μs|Vds|= 100 mV
NMOSPMOS
0.000.050.100.150.20
0.250.300.350.40
-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0Gate Voltage (V)
Dra
in C
urre
nt (m
A)
tr tf
tw
tr , t f = 5 μsTw = 100 μs|Vds|= 100 mV
tr tf
tw
tr , t f = 5 μsTw = 100 μs|Vds|= 100 mV
NMOSPMOS
70
Summary
Dual metal gate CMOS devices have been successfully integrated on both 20 Å
HfO2 and 30 Å HfSiON. Key process modules such as a highly selective metal wet etch
process and a dual metal gate plasma etch process have been developed. Well-behaved
CMOS transistors with Lg down to 45 nm have been demonstrated. Very high mobility
has been achieved for both NMOSFET and PMOSFET. These process modules can be
readily utilized to fabricate dual metal gate CMOS for the 45 nm technology node.
71
Chapter 7: Thermal Annealing Effects on a Representative
High-k/Metal Film Stack
During high-k/metal integration process, they go through high-thermal budget operation
[97-99]. However, a very few studies has been done on the effects of this high
temperature operations [100]. The importance of considering annealing effects becomes
clear here. On the other hand, it is easy to predict that such treatments may have strong
and definitive effects on the density and hence on a lot of film properties [101].
Therefore, the characterization of thermal annealing may be helpful for a deeper
knowledge of the intrinsic properties of a representative high-k/metal film stack. For that
reason, in this chapter, some of the important factors like thickness, surface roughness,
density, sheet resistance, refractive index, extinction coefficient, composition, stress and
bow variations on a HfO2/TiN film stack have been carefully observed due to
temperature annealing.
Experimental
A very thin layer of HfO2 (~20 Å) was deposited on 200 mm wafers using atomic
layer deposition (ALD) technique. Then ~100 Å of TiN was deposited on the high-k
layer using ALD too. When all the depositions were completed, wafers were sent for high
temperature annealing in vacuum for 60 seconds at 1000 ºC. Pre and post annealed
thickness (t), stress (S), bow variation (Bow), sheet resistance (Rs), surface roughness
(R), density (d), composition (N, O and Ti), refractive index (RI) and extinction
72
coefficient (k) were measured using Woollam Optiprobe Thermawave 5240
Spectroscopic Ellipsometry, JVX 5200T XRR Tool, TENCOR FLX-5400 Automated
Thin Film Stress Measurement Systems, PHI 5700 x-ray photoelectron spectroscopy
(XPS) and Tencor RS55TC. The stress tool measured the changes in the radius of
curvature of a substrate caused by deposition of a stressed thin film. The stress in the thin
film was calculated from the radius of curvature of the substrate using the following
equation:
( )f
sv
ERR t
tePost
2
2
Pr 111
61
−⎟⎟⎠
⎞⎜⎜⎝
⎛−=σ
Where,
σ = stress in the film after deposition
RPre = substrate radius of curvature before deposition
RPost = substrate radius of curvature after depsotion
E = Young’s modulus
ν = Poisson's ratio
ts = substrate thickness
tf = film thickness as deposited
73
Results and Discussion
All the results have been shown in figure 7.1 according to their percentile change
in pre and post annealed conditions.
Figure 7.1: Percentile change of pre and post anneal physical properties of HfO2/TiN
film stack [SC1 (5:1.1:1) at room temperature was used for etch rate (ER)]
With annealing at higher temperature, thickness (t) goes down because of granular
densification [101]. This is hypothesis is also supported by XRR data where it shows the
density was increased by about 2.5%. Rs decreased by almost 25%. This change reflects
the decrease in carrier concentration due to decreasing defects through annealing
[102,103]. Annealed samples looked smother in SEM images (Figure 7.2). TMS3000-W
-30.00
-20.00
-10.00
0.00
10.00
20.00
30.00
40.00
50.00
60.00
70.00
t Rs RI k d R S Bow ER N Ti O
Physical parameters
% c
hang
e fro
m n
on-a
nnea
led
to a
nnea
led
sam
ple
74
Texture Measurement System gives a roughness reduction by about 15%. Although,
refractive index can be changed due to various reasons, here it is assumed that mostly
densification as well as roughness reduction attributed to this fact. It is believed that the
as-oxidized film is non-stoichiometric and has many defects due to a loose arrangement.
The high temperature annealing increases the mobility of the atoms or molecules of the
film and favors the formation of more closely packed thin films, which leads to a higher
refractive index [104,105]. However, this measurement has an standard error of the mean
0.0042.
Figure 7.2: Pre (left) and post (right) annealed SEM images of TiN film
Extinction coefficient went way up during the high temperature annealing,
although it also has a standard error of the mean of 0.0065, possibly because of phase
transition [106] or may be lack of O2 incorporation [107]. The later assumption is
supported by the XPS data where it shows that O2 was reduced by around 8%. This fact
75
also contributed in sheet resistance reduction [108]. This refractive index and extinction
coefficient variation indicate that the thickness measurement result obtained from an
ellipsometry can only be a representative figure – not an accurate one.
The significant property change due to annealing is its composition as the N2 is
increased by 6%. It may be because of a little amount of N2 purging during vacuum
annealing in an aging tool (Figure 7.3). Titanium concentration was not changed (Figure
7.4). Even though it was deposited as TiN film, because of natural oxidation, it got
oxidized, which can be seen from its high oxygen content (Figure 7.5).
Figure 7.3: N2 profile from XPS analysis
200.00
400.00
600.00
800.00
1000.00
1200.00
1400.00
1600.00
394.00 396.00 398.00 400.00 402.00Binding Energy (eV)
Cou
nts
[a.u
.]
Not Annealed Annealed
76
Figure 7.4: Titanium profile from XPS analysis
Figure 7.5: O2 profile from XPS analysis
1000.00
1200.00
1400.00
1600.00
1800.00
2000.00
2200.00
2400.00
2600.00
2800.00
3000.00
525.00 530.00 535.00 540.00Binding Energy (eV)
Cou
nts
[a.u
.]
Not Anneled Annealed
300
800
1300
1800
2300
2800
450.00 455.00 460.00 465.00 470.00 475.00Binding Energy (eV)
Cou
nts
(a.u
.)
Not Annealed Annealed
77
Stress profile shows that after thinner (~20 Å) high-k dielectric film deposition
the wafers went through a tensile stress nature and then after relatively thick (~90 Å)
metal film deposition the wafers continued to have higher tensile stress. Finally when the
wafers were annealed that increased the stress by 33% (Figure 7.6).
Figure 7.6: Stress profile of HfO2/TiN film stack after every processing step
A significant findings in the whole experiment is the etch rate falls down for
annealed samples. This fact can be attributed to the granular densification. This
information has also been verified with PVD TaSiN and PVD TiN thin films. In those
films with thermal annealing the etch rates fall down by more than 25~40%. This is also
significant from processing viewpoint, as in dual metal gate CMOS after metal deposition
the hard mask deposition process occurs in 620 ºC. Therefore, during the first metal etch,
the reported etch rate may be slower. Hence, to confirm complete removal of the metal, a
20% over etch is recommended.
0.00E+00
2.00E+09
4.00E+09
6.00E+09
8.00E+09
1.00E+10
1.20E+10
1.40E+10
1.60E+10
1.80E+10
Blanket Wafer HfO2 Deposition TiN Deposition Post AnnealProcess Condition
Stre
ss (d
yne/
cm2)
78
Summary
Since, high-k/metal integration scheme goes through some high thermal budget
process therefore the current study has revealed some important facts, especially about
the change in sheet resistance, optical properties (refractive index and extinction
coefficient) and etch rate. Although major change in optical properties have some
standard error margin, theoretical and previous studies show usually they change with
high temperature. Therefore, this change in optical property may further induce some
error in optical spectroscopy based measurement in ultra thin films. Another important
finding is important for dual metal gate CMOS integration – as etch rate may reduce by
around 20% therefore, during processing 20% over etch is always a good idea to ensure
the complete removal of the metal.
79
Chapter 8: Comparative Study
Dual Metal Gate CMOS will be the solution for next generation integrated chip
(IC) technology, provided the IC industry eventually decides to adopt high-k/metal gate
stack instead of existing SiO2/poly-Si gate stack. So far, four different complete dual
metal gate CMOS have been demonstrated [38,43,44,47]. All of these demonstrations
have successfully showed the advantage of metal gates over poly silicon gate.
Yee-Chia et. al. have demonstrated that their device have comparable hole
mobility that is predictable by the universal mobility model [38]. However, the lower
than expected electron mobility at low vertical field can be attributed to additional
scattering due to trapped carriers at SiO2/Si interface states in the upper-half of the silicon
band gap. They have also shown negligible gate depletion and low gate leakage. But the
threshold voltage for the NMOSFET was higher than desired because of higher channel
doping and gate work function. Also, their PMOSFET and NMOSFET tox difference was
9 Å. The thinner tox for PMOSFET is due to non-optimized wet etch solution, which
removed the gate dielectric in PMOSFET region. It should be noted that the effective
work function of the gate metal depends on this dielectric thickness due to the formation
of a dipole layer at the dielectric-metal interface [109]. Finally they demonstrated their
dual metal gate CMOS on Si3N4 dielectric film, not on high-k dielectric films like HfO2
or HfSiON, which are under serious consideration as the suitable high-k films. Also they
recommended in their publication, that improving the wet etch selectivity over the metals
and high-k dielectric films might have improved their device performance.
80
Although Samavedam et al. first demonstrated an industry scale dual metal gate
CMOS [44] with much improved performance but they used TEOS as a hard mask. It has
been shown that TEOS hard mask etch will affect the high-k dielectric layer specially
HfSiON. Also, they have used a mid-gap work function metal gate TiN.
In a more simplistic scheme Polishchuk et. al. have demonstrated dual work
function metal gate CMOS [43] using nickel and titanium inter diffusion. Here the
threshold voltage of NMOSFET is determined solely by titanium, the threshold voltage
of PMOSFET is determined by nickel rich titanium-nickel alloy. The advantage of this
method is low threshold voltages for surface channel NMOSFET and PMOSFET can be
achieved simultaneously. At the same time, the integrity of the dielectric layer is
preserved as no etching of metal is required. With gate depletion eliminated these
MOSFETs exhibit high inversion charge and drive current. However, in this method they
deposited thicker layer of nickel on a thinner layer of titanium and then they selectively
etched nickel over titanium from the NMOSFET region. Here, etch selectivity is required
between the two metals. Also, deposition of a metal on the other will definitely introduce
some inter mixing at the metal interface. Then when the top metal will be etched the
mixed level of film will still be there on the top of the bottom film. In chapter 3, it has
been shown how the mask (α-Si) can change composition of certain metals. Also, after
the selective etching of the top metal they annealed the films to inter diffuse. This may
affect the underneath high-k dielectric layer. Also, in chapter 7 it has been shown how the
relevant physical properties may change with thermal annealing. Therefore, a
complicated process step to optimize the annealing condition will be necessary for
81
successful implementation of this process. Also, their PMOSFET shows large off-state
leakage current because of tunneling between drain and gate in the large overlap region.
This can be resolved by self-aligned fabrication process. Since, titanium is known to react
with SiO2 above 400 ºC and can be only in a gate last approach.
Feasibility of Implantation Based Metal Gate Electrode and CMOS
Since, deposition-etch-deposition based dual metal gate CMOS technique still has
chance to cause high-k dielectric damage because of dry etch and also the process is a
little complicated therefore, a new technique consisting of implantation has been
considered with a simple experiment (Figure 8.1).
Figure 8.1: Implantation based dual metal gate CMOS
Experimental
Simple MOSCAP were fabricated on ~35 Å HfO2 and HfSiON. 250 Å CVD TiN
was used as metal with and without Si (10 keV/1 e15) implantation.
STI NMOS PMOS
Mo
Implant
STI NMOS PMOS
Metal
82
Results
The work function got a boost with Si implantation as may be seen (Table 8.1).
Table 8.1: Work function table for implantation based TiN metal gate
Without implantation With implantation
HfO2/TiN 4.71 eV 4.84 eV
HfSiON/TiN 4.69 eV 4.9 eV
Well behaved C-V curves have been obtained for silicon implanted and non-
implanted TiN MOSCAP on HfO2 (Figure 8.2) and HfSiON (Figure 8.3).
Figure 8.2: C-V curves for HfO2/TiN. Pink lines are for implanted electrodes.
0.0E+00
5.0E-12
1.0E-11
1.5E-11
2.0E-11
2.5E-11
3.0E-11
-2 -1.5 -1 -0.5 0 0.5 1 1.5 2
Voltage [V]
Cap
acita
nce
[F]
83
Figure 8.3: C-V curves for HfSiON/TiN. Pink lines are for implanted electrodes.
Physical evidences using SIMS were also sought for the prepared capacitors
(Figure 8.4). The analyses were performed on the Physical Electronics ADEPT-1010.
12C, 18O, F, 28Si, 29Si, and 48TN were monitored as negative ions under Cs+ bombardment
at an impact energy of 500 eV incident at 60 °C. Secondary ions were collected from the
center 20% of a 500 μm X 500 μm rastered area. 1 cm2 pieces were taken from the
center of each wafer. The pieces were etched in HF to remove any oxide and silicides
followed by etching in warm KOH to remove the poly Si.
0.0E+00
5.0E-12
1.0E-11
1.5E-11
2.0E-11
2.5E-11
3.0E-11
3.5E-11
-2 -1.5 -1 -0.5 0 0.5 1 1.5 2
Voltage [V]
Cap
acita
nce
[F]
#18
#20
84
Figure 8.4: SIMS analysis on the non-implanted and the implanted capacitors
1E+02
1E+03
1E+04
1E+05
1E+06
0 10 20 30 40 50
Depth (nm)
Cou
nts/
sec
28Si29Si*19.728Si-(29Si*19.7)
1E+02
1E+03
1E+04
1E+05
1E+06
0 10 20 30 40 50
Depth (nm)
Cou
nts/
sec
28Si29Si*19.728Si-(29Si*19.7)
85
Using the known isotopic abundances of 28Si to 29Si, the 28Si intensity was
calculated by subtracting off the contribution from naturally occurring Si from the
implanted 28Si. After this the profiles show that the Si is found deeper in implanted
sample. Therefore, although silicon implantation boosts the work function and causes low
interface charge density, clear relation between work function and amount of silicon
concentration cannot be derived. Also implantation of metal is an uncertain process
because of the presence of their heavy atoms. Tedious optimization of silicon
implantation may give a better result but in context of production cost and timing that
might not be feasible either.
Present Status of Dual Metal Gate CMOS Integration
The introduction of high-k gate dielectrics has taken longer than originally
envisioned. The material selection process has been an arduous journey that began by
focusing on materials with the highest dielectric constant that were stable in contact with
silicon, with ZrO2 and HfO2 being two of the leading candidates [110]. More recent work
has focused on high-k materials that provide good electrical stability, specifically low
charge trapping as measured by pulsed Id-Vg [111-112]. To date, HfSiON has emerged as
the most physically and electrically stable high-k material [113-115]. Historically, HfO2
had been thought to be more scalable than HfSiON, but recent data indicate that HfSiON
can be scaled to an equivalent oxide thickness (EOT) less than 1 nm with either poly
silicon or metal gate electrodes and that the dielectric constant of HfSiON can be equal to
or higher than that of HfO2 [111,116]. While HfSiON has been identified as a scalable
and stable high-k material with respect to EOT and gate leakage, acceptable electron and
86
hole mobility have not yet been reported for materials with less than 1 nm EOT. The
degradation mechanisms of mobility associated with high-k dielectrics are not fully
understood, but trapped charge and/or phonon scattering are thought to be the major
contributors [117]. Even with the difficulties in obtaining a scalable and stable high-k
material with high mobility, the principal challenge that has impeded implementation of
high-k is the threshold voltage (Vt) offset observed when high-k dielectrics are integrated
with poly silicon gate electrodes, which can be as much as 600 mV for PMOS devices
[111,118]. The source of the offset is not well understood, but poly silicon/high-k
reactions [119,120], charge due to dopant incorporation [121] and oxygen vacancies
[122] in the dielectric have all been proposed as possible explanations. While no
solutions to the Vt offset for poly silicon on high-k have been reported, metal gate
electrodes are expected to greatly mitigate or eliminate the offset.
In contrast to the high-k dielectric selection that is nearing consensus, the
identification of a dual work function metal gate electrode system is in its infancy. In
general, CMOS integration requires metals with work functions near the Si band edges
equating to a work function of about 4.0 eV for NMOS and of about 5.0 eV for PMOS.
There are many materials under investigation to meet this requirement, and there are
many resulting integration schema to implement them. The dual work function metal gate
electrode integration schema generally falls into either metal gate first (MGF) (Figure
1.6) or metal gate last (MGL) (Figure 1.5) categories.
87
MGF integration is extremely challenging because it requires the gate electrode to
undergo many front-end steps. The first step is to form different metals over the NMOS
and PMOS transistors. This can be accomplished by consecutive deposition and etches,
but requires highly selective etch chemistries to prevent damage to the underlying gate
dielectric. Once the electrodes are formed, the ability to define the gates by
simultaneously dry etching the two dissimilar materials must be established. Integration
of the patterned electrode with the subsequent cleans and sidewall formation is
challenging as well. Since MGF integration requires the metal gate electrode to be in
contact with the gate dielectric during the source/drain activation anneal, the stability of
the gate electrode with respect to the underlying gate dielectric and any other films (e.g.,
sidewalls) in the gate stack is a critical issue. Many of the metals considered for NMOS,
such as Ti, Hf, Zr and Ta, tend to be quite reactive with the dielectric. As a result of this
high reactivity, the electrical thickness and leakage current of the gate dielectric and/or
the work function of the electrode itself may be uncontrollably modified during high-
temperature processing. Metal nitrides are interesting candidates since they tend to be
more stable in contact with dielectrics than the transition metals. Changing the nitrogen
concentration can modify the work function of TiNx [30], but the tuning is over a small
range. It may be possible to tune the work function of ternary metal nitrides, such as
TiAlN [123], over a wider range. MGF CMOS integration with band edge electrodes has
not yet been reported on any gate dielectric.
Even though MGL integration options are attractive because they eliminate
exposure of the gate metal to many of the front-end process steps associated with MGF
flows and they relax the thermal stability requirements of the gate stack materials, MGL
88
integration schema are not without their own issues. The damascene replacement gate
process flow extensively used for evaluation of metal gates [124] has inherent
disadvantages, such as etching down to the gate dielectric, having a gate dielectric grown
at low temperatures, planarization control and self-alignment issues. Full silicidation,
called doped FuSi, using NiSi formed from doped polysilicon has received much
attention lately as a MGL approach [125]. The use of NiSi is highly desirable because it
utilizes known materials and processes with only modest modifications to the standard
integration, can be scaled to narrow line widths and has a relatively low volume
expansion upon full silicidation. Even with these advantages, this approach is not without
its own challenges. For example, the work function setting mechanism is not understood
yet, work function tuning to band edge values for NiSi have not been reported yet on
high-k gate dielectrics, there could be problems with the simultaneous silicidation of
NMOS and PMOS gates, and potential orientation and grain size effects on threshold
voltage uniformity need to be comprehended.
From this view point, it may be seen that deposition-etch-deposition based
technique has real promise to be the unique solution for dual metal gate CMOS
integration, provided a unique wet etch module is developed with high selectivity over
high-k dielectric films and the relevant materials. This approach has flexibility to
integrate any combination of metals. Also, till now the two full scale dual metal gate
CMOS fabricated at industry scale have followed this method.
89
Chapter 9: Conclusion
Key Findings of The Current Work
Advanced fabrication process needs more control in fabrication. Sub-50nm
CMOS or structures fabrication is a job which complicates simple processing steps. In
this regard, this work started as a humble effort to develop a highly selective wet etch
module to satisfy successful integration of dual metal gate CMOS using deposition-etch-
deposition method. Therefore:
A highly selective unique wet etch module using SC1 and NH4OH has been
developed to successfully etch any potential candidate gate metal.
Amorphous silicon has been identified has been a suitable hard mask for dual
metal gate CMOS integration.
Integrations issues have been discussed and possible solutions have been
proposed.
Since smooth dielectric surface is a requirement for improved device
performance, physical evidences have been presented to show benign effects of
the developed wet etch module.
90
Metal wet etch impact on device performance and reliability has been tested. It
has been found that wet etch in fact enhances hole mobility and improves
reliability.
As dry etching of two different metals (may be of different thicknesses) placed
adjacent to each other is complicated, therefore, promise of wet etch as a gate etch
solution has been investigated. It has been found that, wet etching of gate reduces
gate leakage.
Full scale dual metal gate CMOS with 0.2 eV work function separation have been
demonstrated with Ru as a PMOS and TaSiN as an NMOS metal. Developed wet
etch solution has been used in this industry scale integrations.
Since, HfSiON has been proved as the most potential high-k dielectric film, for
the first time, dual metal gate CMOS with Lg down to 45 nm using ALD TaCN
and ALD TiN has been demonstrated.
High-k/metal gate stack goes through high thermal budget processes. Hence, as a
supplemental work, thermal anneal effects on physical properties of high-k/metal
film stack has been studied.
Feasibility of implantation based gate metal electrode has been probed.
91
Future Directions
Usage of capping layer has shown better promise for appropriate work function
separation in dual metal gate CMOS. Also, two different types of capping layer may be
required for NMOS and PMOS region. Therefore, to use deposition-etch-deposition
based method needs to be remodeled a bit. Some very important objectives may be
attained with a little modification in the integration scheme:
1. Complete metal separation (gate stacks without two metals – one top of the
other);
2. Less number of wet etch treatment on high-k dielectric film;
3. Integration two different capping layers on high-k dielectric films.
4. More flexibility in integration.
Therefore, a new method can be investigated further (Figure 8.5).
Figure 9.1: Dual Cap Dual Metal Gate CMOS integration process flow
High-k + Al2O3
Etch a-Si and Remove Photoresist Wet Etch P-metal and Strip high-k
Deposit high-k, PDA, then N-metal and a-Si
Photoresist Pattern
Wet Etch N-metal and Remove High-k Remove AmSi HM
Etch a-Si Stopping on N-metal
P-metal
STI
a-Si
Photoresist
PMOS NMOS STI
a-Si
PMOS NMOS
P-metal
STIPMOS NMOS
a-SiP-metal
STIPMOS NMOS
a-SiP-metal N-metal
a-Si
a-Si
Photoresist
STIPMOS NMOS
a-SiP-metal
a-Si
a-SiPhotoresist
STIPMOS NMOS
a-SiP-metal
a-Si
STIPMOS NMOS
a-SiP-metal
a-Si
STIPMOS NMOS
P-metal N-metal
High-k + Al2O3
Etch a-Si and Remove Photoresist Wet Etch P-metal and Strip high-k
Deposit high-k, PDA, then N-metal and a-Si
Photoresist Pattern
Wet Etch N-metal and Remove High-k Remove AmSi HM
Etch a-Si Stopping on N-metal
P-metal
STI
a-Si
Photoresist
PMOS NMOS
P-metal
STI
a-Si
Photoresist
PMOS NMOS STI
a-Si
PMOS NMOS
P-metal
STI
a-Si
PMOS NMOS
P-metalP-metal
STIPMOS NMOS
a-SiP-metal
STIPMOS NMOS
a-SiP-metalP-metal
STIPMOS NMOS
a-SiP-metal N-metal
a-Si
a-Si
STIPMOS NMOS
a-SiP-metal
STIPMOS NMOS
a-SiP-metalP-metal N-metal
a-Si
a-Si
Photoresist
STIPMOS NMOS
a-SiP-metal
a-Si
a-SiPhotoresist
STIPMOS NMOS
a-SiP-metal
a-Si
a-Si
STIPMOS NMOS
a-SiP-metal
STIPMOS NMOS
a-SiP-metalP-metal
a-Si
a-SiPhotoresist
STIPMOS NMOS
a-SiP-metal
a-Si
Photoresist
STIPMOS NMOS
a-SiP-metal
STIPMOS NMOS
a-SiP-metalP-metal
a-Si
STIPMOS NMOS
a-SiP-metal
a-Si
STIPMOS NMOS
a-SiP-metal
STIPMOS NMOS
a-SiP-metalP-metal
a-Si
STIPMOS NMOS
P-metal N-metal
STIPMOS NMOS
P-metalP-metal N-metal
92
In this integration process, hard mask is not removed after the first metal removal.
Hence, it reduces hard mask wet etch step and reduces wet etch exposure on the high-
k dielectric film. The high-k dielectric film is removed after the first metal removal
from the etched gate region. Then the high-k dielectric film is re-deposited followed
by the capping layer deposition. This gives flexibility to deposit any type of dielectric
layer and capping layer. Also, at the end two gate stacks have their own metals only.
Since, the gate stacks will have poly-silicon/metal/capping layer/high-k dielectric
film, therefore, gate etch with dry etch will be very challenging. Thus, all wet etch for
gate etch can be a probable solution. To realize this plan needs a lot of work.
It may also be seen the wet etch impact on device performance and reliability,
where the metals will be deposited by different techniques (PVD, CVD and ALD).
Also, wet etch mechanism in context of physical properties of different films and
different deposition methods can be investigated to understand the physical science
behind etch mechanism in ultra thin metallic films. Optimization of wet etch to
control the undercutting caused by wet etch will be an important work to use wet etch
for complicated gate stack etch. In short, considerable work in advanced fabrication
process remains for a full industry scale, efficient sub-50nm CMOS. Hopefully, the
current work will play a significant role in eventual evolution of production level dual
metal gate CMOS to realize the nano-scale CMOS operation, as well as in non-
classical CMOS fabrication like FinFET and nanowire transistor or structure
fabrication (by direct patterning or imprinting mold) using controlled and/or
orientation dependent wet etch solution.
93
Bibliography
1. P. Packan. Science 285, 2079 (1999)
2. B. Hoeneisen and C. A. Mead. Solid State Electron. 15, 819 (1972)
3. J. Meindl. Proc. IEEE 83, 619 (1995)
4. S. Asai and Y. Wada. Proc. IEEE 85, 505 (1997)
5. Y. Taur, D. Buchanan, W. Chen, D. Frank, K. Ismail, S.-H. Lo, G. Sai-Halasz, R.
Viswanathan, H.-J. C. Wann, S. Wind, and H.-S. Wong. Proc. IEEE 85, 486
(1997)
6. H.-S. P. Wong, D. Frank, P. M. Solomon, H.-J. Wann, and J. Welser. Proc. IEEE
87, 537 (1999)
7. D. Frank, R. Dennard, E. Nowak, P. Solomon, Y. Taur, and H.-S. Wong. Proc.
IEEE 89, 259–288 (2001)
8. R. W. Keyes. Proc. IEEE 89, 227–239 (2001)
9. J. Plummer and P. Griffin. Proc. IEEE 89, 240–258 (2001)
10. D. A. Buchanan, IBM J. Res. Develop. 43, 245, 1999
11. Rainer Weiser. Nanoelectronics and Information Technology, Wiley-VCH, 2003
12. S. H. Lo, D. A. Buchanan, Y. Taur and W. Wang. IEEE Electronic Device Letter
209 (1997)
13. H. -S. P. Wong. IBM J. Res. Develop. Volume 46, Numbers 2/3, 2002
14. S. Q. Wang and J. W. Mayer. J. Appl. Phys. 64, 4711 (1988)
15. R. Pretorius, J. M. Harris, M-A.Nicolet. Solid State Electron. 21, 667 (1978)
16. E. P. Gusev, E. Cartier, D. A. Buchanan, M. Gribelyuk, M. Copel, H. Okorn-
Schmidt and C. D’Emic. Microelectronic Engineering 59, (2001) 341-349
94
17. M. Fischetti. J. Appl. Phys. 89, 1232–1250 (2001).
18. Y.-C. Yeo, Q. Lu, P. Ranade, H. Takeuchi, K.J. Yang, I. Polishchuk, T.-J. King,
C. Hu, S.C. Song, H.F. Luan and D.-L. Kwong. IEEE Electron Device Lett. 22 5
2001 (May), pp. 227–229
19. B. Cheng, M. Cao, R. Rao, A. Inani, P.V. Voorde, W.M. Greene, J.M.C. Stork, Z.
Yu, P.M. Zeitzoff and J.C.S. Woo. IEEE Trans. Electron Devices 46 47 1999
(Jul.), pp. 1537–1544
20. I. De, D. Johri, A. Srivastava and C.M. Osburn. Solid-State Electron. 44 6 2000
(Jun.), pp. 1077–1080
21. H.-S. P. Wong. IBM J. Res. Develop. 46 (2002), pp. 133–168
22. P. Ranade, Y.C. Yeo, Q. Lu, T.-J. King and C. Hu. Mater. Res. Soc. Symp. Proc.
611 (2000 (Apr.)), pp. C3.2.1–C3.2.6 (San Francisco, CA)
23. B. Tavel, T. Skotnicki, G. Pares, N. Carrière, F. Leverd, C. Julien, J. Torres and
R. Pantel in International Electron Device Meeting Tech. Digest, IEEE,
Piscataway NJ, USA 2001 (Dec.), pp. 825–828
24. W.P. Maszara, Z. Krivokapic, P. King, J.-S. Goo and M.-R. Lin in International
Electron Device Meeting Tech. Digest, IEEE, Piscataway NJ, USA 2002 (Dec.),
pp. 367–370
25. Z. Krivokapic, W.P. Maszara, K. Achutan, P. King, J. Gray, M. Sidorow, E. Zhao,
J. Zhang, J. Chan, A. Marathe and M.-R. Lin in International Electron Device
Meeting Tech. Digest, IEEE, Piscataway NJ, USA 2002 (Dec.), pp. 271–274
26. J.H. Sim, H.C. Wen, J.P. Lu and D.L. Kwong. IEEE Electron Device Lett. 24
2003, pp. 631–633
95
27. C.-Y. Lin, M.W. Ma, A. Chin, Y.-C. Yeo, C. Zhu, M.F. Li and D.-L. Kwong.
IEEE Electron Device Lett. 24 5 2003 (May), pp. 348–350
28. J.C. Hu, H. Yang, R. Kraft, A.L.P. Rotondaro, S. Hattangady, W.W. Lee, R.A.
Chapman, C.-P. Chao, A. Chatterjee, M. Hanratty, M. Rodder and I.-C. Chen in
International Electron Device Meeting Tech. Digest, IEEE, Piscataway NJ, USA
1997 (Dec.), pp. 825–828
29. Y.-S. Suh, G.P. Heuss, J.-H. Lee and V. Misra. IEEE Electron Device Lett. 24 7
2003 (Jul.), pp. 439–441
30. H. Wakabayashi, Y. Saito, K. Takeuchi, T. Mogami and T. Kunio. IEEE Trans.
Electron Devices 48 10 2001 (Oct.), pp. 2363–2369
31. J.K. Schaeffer, S.B. Samavedam, D.C. Gilmer, V. Dhandapani, P.J. Tobin, J.
Mogab, B.Y. Nguyen, B.E. White, Jr., S. Dakshina-Murthy, R.S. Rai, Z.X. Jiang,
R. Martin, M.V. Raymond, M. Zavala, L.B. La, J.A. Smith, R. Garcia, D. Roan,
M. Koeeke and R.B. Gregory. J. Vac. Sci. Technol. B 21 (2003), pp. 11–17
32. H. Zhong, G. Heuss and V. Misra. IEEE Electron Device Lett. 21 12 2000 (Dec.),
pp. 593–595
33. H. Zhong, S.-N. Hong, Y.-S. Suh, H. Lazar, G. Heuss and V. Misra in
International Electron Device Meeting Tech. Digest, IEEE, Piscataway NJ, USA
2001 (Dec.), pp. 467–470
34. B.-Y. Tsui and C.-F. Huang. IEEE Electron Device Lett. 24 3 2003 (Mar.), pp.
153–155
35. Y.-C. Yeo, P. Ranade, T.-J. King and C. Hu. IEEE Electron Device Lett. 23 6
2002 (Jun.), pp. 342–344
96
36. Y.-C. Yeo, T.-J. King and C. Hu. J. Appl. Phys. 92 12 2002 (Dec.), pp. 7266–
7271
37. J. Tersoff. Phys. Rev. B 30, 4874 (1984).
38. Y.-C. Yeo, P. Ranade, Q. Lu, R. Lin, T.-J. King, and C. Hu in Symposium on
VLSI Technology, Digest of Technical Papers, 2001, pp. 49–50.
39. P. Ranade, H. Takeuchi, T.-J. King, and C. Hu. Electrochem. Solid-State Lett. 4,
G85 (2001)
40. R. Lin, Q. Lu, P. Ranade, T.-J. King, and C. Hu. IEEE Electron Device Lett. 23,
49 (2002)
41. C. S. Park, B. J. Cho, and D.-L. Kwong. IEEE Electron Device Lett. 24, 298
(2003)
42. J. H. Lee, H. Zhong, Y.-S. Suh, G. Heuss, J. Gurganus, B. Chen, and V. Misra In
Tech. Dig. - Int. Electron Devices Meet. 2002, 359
43. I. Polishchuk, P. Ranade, T.-J. King, and C. Hu. IEEE Electron Device Lett. 23,
200 (2002)
44. S. B. Samavedam, L. B. La, J. Smith, S. Dakshina-Murthy, E. Luckowski, J.
Schaeffer, M. Zavala, R. martin, V. Dhandapani, D. Triyoso, H. H. Tseng, P. J.
Tobin, D. C. Gilmer, C. Hobbs, W. J. Taylor, J. M. grant, R. I. Hegde, J. Mogab,
C. Thomas, P. Abramowitz, M. Moosa, J. Conner, J. Jiang, V. Arunachalam, M.
Sadd, B.-Y. Nguyen, and B. White in IEDM Technology Digest 433 (2002).
45. B. Clafin, K. Flock and G. Lucovsky. Mat. Res. Soc. Symp. Proc. Vol. 567, 1999
46. Y-C Yeo. Thin Solid Films 462-263 (2004) 34-41
97
47. Z.B. Zhang, S.C. Song, C. Huffman, J. Barnett, N. Moumen, H. Alshareef, P.
Majhi, M. Hussain, M.S. Akbar, J.H. Sim, S.H. Bae, B. Sassman, and B.H. Lee in
2005 Symposia on VLSI Technology and Circuits, Kyoto-Japan, 14-18 June 2005
48. Q. Lu, Y. C. Yeo, P. Ranade, H. Takeuchi, T. J. King, and C. Hu in Symp. VLSI
Tech. Dig. 2000, pp. 72–73
49. S. H. Bae, W. P. Bai, H. C. Wen, S. Mathew, L. K. Bera, N. Balasubramanian, N.
Yamada, M. F. Li, and D. L. Kwong in Symp. VLSI Tech. Dig. 2004, pp. 188–189
50. P. Ranade, Y.-K. Choi, D. Ha, A. Agarwal, M. Ameen, and T. -J. King in IEDM
Tech. Dig. 2002, pp. 363–366.
51. A. Yagishita, T. Saito, K. Nakajima, S. Inumiya, K. Matsuo, Y. Akasaka, Y.
Ozawa, G. Minamihaba, H. Yano, Y. Matsui, Y. Tsunashima, K. Suguro, T.
Arikado, and K. Okumura in IEDM Tech. Dig. 1999, pp. 257–260
52. Ren, C.; Yu, H.Y.; Kang, J.F.; Wang, X.P.; Ma, H.H.H.; Yee-Chia Yeo; Chan,
D.S.H.; Li, M.-F.; Kwong, D.-L. IEEE Electron Device Letters Volume 25, Issue
8, Aug. 2004 Page(s): 580 – 582
53. Doris, B.; Park, D.G.; Settlemyer, K.; Jamison, P.; Boyd, D.; Li, Y.; Hagan, J.;
Staendert, T.; Mezzapelli, J.; Dobuzinsky, D.; Linder, B.; Narayanan, V.;
Callegari, S.; Gousev, E.; Guarini, K.; Jammy, R.; Leong, M. in 2005 IEEE VLSI-
TSA International Symposium on 25-27 April 2005 Page(s): 101 – 102
54. Monroe, D.; Hergenrother, J. Solid-State Circuits Conference, 2000. Digest of
Technical Papers. ISSCC. 2000 IEEE International 7-9 Feb. 2000 Page(s): 134 –
135
98
55. Chatterjee, A.; Chapman, R.A.; Joyner, K.; Otobe, M.; Hattangady, S.; Bevan,
M.; Brown, G.A.; Yang, H.; He, Q.; Rogers, D.; Fang, S.J.; Kraft, R.; Rotondaro,
A.L.P.; Terry, M.; Brennan, K.; Aur, S.-W.; Hu, J.C.; Tsai, H.-L.; Jones, P.; Wilk,
G.; Aoki, M.; Rodder, M.; Chen, I.-C. Electron Devices Meeting, 1998. IEDM '98
Technical Digest., International 6-9 Dec. 1998 Page(s): 777 – 780
56. Achard, H.; Ducroquet, F.; Coudert, F.; Previtali, B.; Lugand, J.F.; Ulmer, L.;
Farjot, T.; Gobil, Y.; Heitzmann, M.; Tedesco, S.; Nier, M.E.; Deleonibus, S.
Solid-State Device Research Conference, 2000. Proceeding of the 30th European
11-13 September 2000 Page(s): 408 – 411
57. Guillaumot, B.; Garros, X.; Lime, F.; Oshima, K.; Tavel, B.; Chroboczek, J.A.;
Masson, P.; Truche, R.; Papon, A.M.; Martin, F.; Damlencourt, J.F.; Maitrejean,
S.; Rivoire, M.; Leroux, C.; Cristoloveanu, S.; Ghibaudo, G.; Autran, J.L.;
Skotnicki, T.; Deleonibus, S. Electron Devices Meeting, 2002. IEDM '02. Digest.
International 8-11 Dec. 2002 Page(s): 355 – 358
58. Matsuo, K.; Saito, T.; Yagishita, A.; Iinuma, T.; Murakoshi, A.; Nakajima, K.;
Omoto, S.; Suguro, K. VLSI Technology, 2000. Digest of Technical Papers. 2000
Symposium on 13-15 June 2000 Page(s): 70 – 71
59. Pan, J.; Woo, C.; Ngo, M.V.; Besser, P.; Pellerin, J.; Qi Xiang; Ming-Ren Lin
Electron Device Letters, IEEE Volume 24, Issue 9, Sept. 2003 Page(s):547 – 549
60. Akasaka, Y.; Miyagawa, K.; Syoji, H.; Ogawa, O.; Kawahara, T.; Horiuchi, A.;
Mitsuhashi, R.; Maeda, T.; Muto, A.; Kasai, N.; Yasuhira, M.; Arikado, T.
Gate Insulator, 2003. IWGI 2003. Extended Abstracts of International Workshop
on 6-7 Nov. 2003 Page(s): 94 – 95
99
61. K. G. Anil, A. Veloso, S. Kubicek, T. Schram, E. Augendre, J.-F. de Marneffe, K.
Devriendt, A. Lauwers, S. Brus, K. Henson, and S. Biesemans in VLSI Symp.
Tech. Dig. 2004, pp. 190–191
62. J. H. Sim, H. C. Wen, J. P. Lu, and D. L. Kwong. IEEE Electron Device Lett. vol.
24, no. 10, pp. 631–633, Oct. 2003
63. P. Xuan and J. Bokor. IEEE Electron Device Lett. vol. 24, no. 10, pp. 634–636,
Oct. 2003
64. J. Kedzierski, E. Nowak, T. Kanarsky, Y. Zhang, D. Boyd, R. Carruthers, C.
Cabral, R. Amos, C. Lavoie, R. Roy, J. Newbury, E. Su, J. Benedict, P. Saunders,
K. Wong, D. Canaperi, M. Krishnan, K.-L. Lee, B. A. Rainey, D. Fried, P.
Cottrell, H. S. Wong, M. Leong, and W. Haensch in IEDM Tech. Dig. 2002, p.
247
65. J. Kedzierski, D. Boyd, P. Ronsheim, S. Zafar, J. Newbury, J. Ott, C. Cabral, M.
Ieong, and W. Haensch in IEDM Tech. Dig. 2003, pp. 13.3.1–13.3.4
66. J. Kedzierski, D. Boyd, Y. Zhang, M. Steen, F. F. Jamin, J. Benedict, M. Ieong,
and M. Haensch in IEDM Tech. Dig. 2003, pp. 18.4.1–18.4.4
67. C. H. Huang, D. S. Yu, A. Chin, C. H. Wu, W. J. Chen, C. Zhu, M. F. Li, B. J.
Cho, and D.-L. Kwong in IEDM Tech. Dig. 2003, pp. 13.4.1–13.4.4.
68. J. H. Sim, H. C.Wen, J. P. Lu, and D. L. Kwong. IEEE Electron Device Lett. vol.
25, no. 9, pp. 610–612, Sep. 2004
69. B. Tavel, T. Skotnicki, G. Pares, N. Carriere, M. Rivoire, F. Leverd, C. Julien, J.
Torres, and R. Pantel in IEDM Tech. Dig. 2001, pp. 37.5.1–37.5.4.
100
70. S.-L. Zhang and M. Ostling. Crit. Rev. Solid Mater. Sci. vol. 28, no. 1, pp. 1–129,
Mar. 1, 2003
71. H. N. Alshareef, P. Majhi, Z. Zhang, P. Zeitzoff, B. H. Lee, and H. Huff, Future
Fab in Press
72. Muhammad Mustafa Hussain, Naim Moumen, Joel Barnett, Jason Saulters, David
Baker, Mohammad Akbar, Zhibo Zhang in Electrochemical Society 207th
Meeting, Quebec City-Canada, 16-21 May 2005
73. Muhammad Mustafa Hussain, Naim Moumen, Joel Barnett, Jason Saulters, David
Baker, Zhibo Zhang. Electrochem. Solid-State Lett. 8, G333 (2005)
74. M.S. Akbar, N. Moumen, J. Barnett, B.H. Lee, and J.C. Lee. IEEE Elec. Dev.
Lett. vol. 26, pp. 163-165, 2005.
75. P.D. Kirsch, et al. in Proc. ESSDERC, 2005
76. S. Datta, et al. IEDM Tech. Digest pp. 653-656, 2003
77. S. Zafar, A. Kumar, E. Gusev, and E. Cartier. IEEE Trans. Dev. Matr. Reliability,
vol. 5, pp. 45-64, 2005
78. C.D. Young, P. Zeitzoff, G.A. Brown, G. Bersuker, B.H. Lee and J.R. Hauser.
IEEE Elec. Dev. Lett. vol. 26, pp. 586-589, 2005
79. M. Houssa, A. Stesmans, M. Naili, and M.M. Heyns. Appl. Phys. Lett. vol. 77, pp.
1381-1383, 2000
80. W.J. Zhu, T.P. Ma, S. Zafar, and T. Tamagawa. IEEE Elec. Dev. Lett. vol. 23, pp.
597-599, 2002.
81. J. P. McVittie in 1st Int. Symp. Plasma Process Induced Damage, 1996, p. 7
101
82. C. C. Chen, H. C. Lin, C. Y. Chang, M. S. Liang, C. H. Chien, S. K. Hsien, and T.
Y. Huang. IEEE Electron Device Lett. vol. 21, pp. 15–17, Jan. 2000
83. Pei-Jer Tzeng, Yi-Yuan Chang, Kuei-Shu Chang-Liao. IEEE Electron Device
Letters Volume 22, Issue 11, Nov. 2001 Page(s):527 - 529
84. C. Gabriel and J. McVittie. Solid-State Technol. 35, 81 (1992)
85. S. Fang and J. McVittie. IEEE Electron Device Lett. 13, 347 (1992)
86. S. J. Fonash, C. R. Viswanathan, and Y. D. Chan. Solid-State Technol. 37, 99
(1994)
87. H. Shin, K. Noguchi, and C. Hu. IEEE Electron Device Lett. 14, 509 (1993)
88. M. Tuda, K. Shintani, and H. Ootera. J. Vac. Sci. Technol. A 19, 711 (2001)
89. A.H. Perera, Hsing-Huang Tseng. IEEE Electron Device Letters Volume 17,
Issue 11, Page(s): 528 – 530
90. O. Joubert, E. Pargon, X. Detter, J. Chevolleau, G. Cunge, L. Vallier in Plasma-
and Process-Induced Damage, 2003 8th International Symposium 24-25 April
2003 Page(s): 12 - 15
91. X. Li et al. IEEE Electron Device Lett. 22, 285 (1994)
92. T. Gu et al. IEEE Electron Device Lett. 15, 2 (1994)
93. X. Li et al. in Proceedings of the 1995 IEEE International Reliability Physics
Symposium, Las Vegas (1995), p. 250.
94. G. Brown et. al. discussed in SISC 2004
95. Z.B. Zhang, et al, Proc. of Device Research Conf. 2005
96. K. Choi, et al., unpublished results
102
97. S. B. Samavedam, H. Tseng, and P. Tobin, in Symp. VLSI Tech. Dig. 2002, pp.
24–25
98. S. Matsuda, H. Yamakawa, A. Azuma, and Y. Toyoshima, in Symp. VLSI Tech.
Dig. 2001, pp. 63–64
99. D. Park, K. Lim, H. Cho, T. Cha, J. Kim, J.Ko, I.Yeo, and J. Park, in Symp. VLSI
Tech. Dig. 2002, pp. 65–66
100. James Pan, Christy Woo, Minh-Van Ngo, James Xie, David Matsumoto,
Dakshi Murthy, Jung-Suk Goo, Qi Xiang and Ming-Ren Lin. IEEE Transactions
on Electron Devices Vol. 51, No. 4, April 2004
101. G. Andreasen, P. L. Schilardi, O. Azzaroni, and R. C. Salvarezza.
Langmuir 2002, 18, 10430-10434
102. Yuji Matsui, Yuichi Yamamoto and Satoshi Takeda in Mat. Res. Soc.
Symp. Proc. Vol 621
103. Arwyn L. E. Smalley, Seok Kim, and David C. Johnson. Chem. Mater.
2003, 15, 3847-3851
104. Katsuhiro Yokota, Kazuhiro Nakamura, Tomohiko Kasuya, Katsuhisa
Mukai and Masami Ohnishi. J. Phys. D: Appl. Phys. 37 No 7 (7 April 2004)
1095-1101
105. G. He, Q. Fang, J. X. Zhang, L. Q. Zhu, M. Liu and L. D. Zhang.
Nanotechnology 16 (2005) 1641-1647
106. Wen-Hsiang Wang and Shiuh Chao. Optics Letters Vol 23, No. 28 1417-
1419
103
107. Z. W. Zhao, B. K. Tay, L. Huang, S. P. Lau, J. X. Gao. Optical Materials
27 2004 465-469
108. H.B. Bhuvaneswarib, V. Rajagopal Reddyb, R. Chandramanic, G. Mohan
Rao. Applied Surface Science 230 (2004) 88-93
109. J. Robertson and C. W. Chen. Appl. Phys. Lett., vol. 74, no. 8, pp. 1168–
1170, Feb. 1999
110. G.D. Wilk, R.M. Wallace, and J.M. Anthony. Journal of Applied Physics
89, 5243-5275 (2001)
111. A.L.P. Rotondaro, M.R. Visokay, J.J. Chambers, A. Shanware, R.
Khamankar, H. Bu, R.T. Laaksonen, L. Tsung, M. Douglas, R. Kuan, M.J. Bevan,
T. Grider, J. McPherson, and L. Colombo, in Symposium on VLSI Technology
Digest of Technical Papers (Honolulu, HI, 2002), p. 148-149
112. A. Shanware, M.R. Visokay, J.J. Chambers, A.L.P. Rotondaro, J.
McPherson, and L. Colombo, in Technical Digest of IEEE International Electron
Device Meeting (2003)
113. M. R. Visokay, J.J. Chambers, A.L.P. Rotondaro, A. Shanware, and L.
Colombo. Appl. Phys. Lett. 80, 3183 (2002)
114. A. Shanware, J. McPherson, M.R. Visokay, J.J. Chambers, A.L.P.
Rotondaro, M.J.B.H. Bu, R. Khamankar, and L. Colombo, in Technical Digest of
IEEE International Electron Device Meeting (2001)
115. A. Shanware, M.R. Visokay, J.J. Chambers, A.L.P. Rotondaro, H. Bu,
M.J. Bevan, R. Khamankar, S. Aur, P.E. Nicollian, J. McPherson, and L.
104
Colombo, in 2003 IEEE International Reliability Physics Symposium Proceedings
(2003), p. 208
116. M. Koike, T. Ino, M. Koyama, Y. Kamata, Y. Kamimuta, M. Suzuki,
Akira Takashima, Y. Mitani, A. Nishiyama, and Y. Tsunashima, in Extended
Abstracts of the 2003 International Conference on Solid State Devices and
Materials (2003), p. 52-53
117. M.V. Fischetti, D.A. Neumayer, and E.A. Cartier. Journal of Applied
Physics 90, 4587-4608 (2001)
118. E. Gusev, D.A. Buchanan, E. Cartier, A. Kummar, D. DiMaria, S. Guha,
A. Callegari, S. Zafar, P.C. Jamison, D.A. Neumayer, M. Copel, M. Gribelyuk, H.
Okorn-Schmidt, C. D'Emic, P. Kozlowski, K. Chan, N. Bojarczuk, L.-A.
Ragnarson, P. Ronsheim, K. Rim, R.J. Fleming, A. Mocuta, and A. Ajmera, in
Technical Digest of IEEE International Electron Device Meeting (2001), p. 451-
454
119. C.C. Hobbs, L.R.C. Fonseca, A. Knizhnik, V. Dhandapani, S.B.
Samavedam, W.J. Taylor, J.M. Grant, L.G. Dip, D.H. Triyoso, R.I. Hegde, D.C.
Gilmer, R. Garcia, D. Roan, M.L. Lovejoy, R.S. Rai, E.A. Hebert, H.-H. Tseng,
S.G.H. Anderson, B.E. White, and P.J. Tobin. Electron Devices, IEEE
Transactions on 51, 971-977 (2004)
120. E. Cartier, V. Narayanan, E.P. Gusev, P. Jamison, B. Linder, M. Steen,
K.K. Chan, M. Frank, N. Bojarczuk, M. Copel, S.A. Cohen, S. Zafar, A.
Callegari, M. Gribelyuk, M.P. Chudzik, C. Cabral, R. Carruthers, C. D'Emic, J.
105
Newbury, D. Lacey, S. Guha, and R. Jammy, in Symposium on VLSI Technology
Digest of Technical Papers (Honolulu, 2004), p. 44-45
121. A. Kaneko, S. Inumiya, K. Sekine, M. Sato, Y. Kamimuta, K. Eguchi, and
Y. Tsunashima, in International Conference on Solid State Devices and Materials
(2003), p. 56-57
122. K. Shiraishi, K. Yamada, K. Torii, Y. Akasaka, K. Nakajima, M. Kohno,
T. Chikyo, H. Kitajima, and T. Arikado, in Symposium on VLSI Technology
Digest of Technical Papers (2004), p. 108-109
123. T.-H. Cha, D.-G. Park, T.-K. Kim, S.-A. Jang, I.-S. Yeo, J.-S. Roh, and
J.W. Park. Applied Physics Letters 81, 4192-4194 (2002)
124. A. Chatterjee, R.A. Chapman, G. Dixit, J. Kuehne, S. Hattangady, H.
Yang, G.A. Brown, R. Aggarwal, U. Erdogan, Q. He, M. Hanratty, D. Rogers, S.
Murtaza, S.J. Fang, R. Kraft, A.L.P. Rotondaro, J.C. Hu, M. Terry, W. Lee, C.
Fernando, A. Konecni, G. Wells, D. Frystak, C. Bowen, M. Rodder, and I.-C.
Chen, in Technical Digest of IEEE International Electron Device Meeting (1997),
p. 821 - 824
125. W. P. Maszara, Z. Krivokapic, P. King, J.-S. Goo, and M.-R. Lin, in
Technical Digest of IEEE International Electron Device Meeting (2002), p. 367 -
370
106
VITA
Muhammad Mustafa Hussain was born in Dhaka, Bangladesh on August 11th,
1976, the youngest son of Mrs. Hosne Ara Begum and Dr. Mohammad Abdul Hakim.
After completing his high school education from Government Laboratory High School
and Dhaka College, he joined in Bangladesh University of Engineering and Technology
(BUET) in 1995. In August 2000, he earned BS in Electrical and Electronic Engineering
from BUET. In January 2001, he started his graduate study in the University of Southern
California, Los Angeles. There he earned his MS in Electrical Engineering in 2002. Then
he joined the Electrical and Computer Engineering Department of the University of
Texas at Austin in January 2003. In August 2004, he earned another MS in Solid State
Electronics Area under Professor Dean P. Neikirk. From September 2004, he started
working at SEMATECH, Austin-TX as an intern in Advanced Gate Cleans project.
Permanent Address: Apt # B-4, 14, Park Road, Baridhara, Dhaka 1212, Bangladesh
This dissertation was typed by the author.