control electronics for ams on antares at ansto · control electronics for ams on antares at ansto...
TRANSCRIPT
CONTROL ELECTRONICS for AMS on ANTARES at ANSTO
Geoff Watt
ANSTO Engineering & Capital Programs
Electrical & Control Services Unit
Contents
2
• Fast Cycling AMS
- Beam chopping
- Bouncing
• Control sequencer
- Original
- Need for change
- Redesign using NI FPGA Card
- Design methodology
- Sequencer support utilities
User interface
FPGA-resident code
- Waveforms
• Future developments
• Acknowledgements
FAST-CYCLING AMS on ANTARES
• Ion source (far lower left) is at elevated
DC voltage
• Ion current is ‘Chopped’ after source
• 12C, 13C, & 14C species is selected at
Injection Magnet by ‘Bouncing’
• Bouncing voltage 0 < V < 13 kV
• Ion currents are measured at detector
end by I:F Conv & gated counters
• Continuously cycles between 12,13,14
measurement at ~5 – 10 Hz rate
• Hardware is controlled by ‘Sequencer’
3
Waveforms during one AMS cycle
Ion current
chopping
HV
bouncing
I:f counting
gates
• Typical counting period ~ 200 ms
• All parameters are selectable by user @typically 10–20 µs time resolution
• All signal edges are synchronous to within 5 ns
4
Ion Beam Chopper Circuit
Simplified schematic of chopper - Fibre-optic pulse isolation
- 2 Totem poles in antiphase
- Output +/- 400 V
Detailed schematic of one totem pole - 1000 V MOSFETs
- High-current gate drivers
- 400 V power supply
- 20 ns rise/fall time
- Circuitry to control commutation
5
HV Bouncer Circuit
Multiplexer
• Mux1 & Mux0 address lines define 4 address values: 00, 01, 10, 11
• Each value corresponds respectively to Rare (14C), Major (12C), Minor (14C), and Extra,
• Address values sequentially applied to the mux select each of 4 DC reference voltages in turn,
• Each DC reference voltage is 1/1500 of the required bouncer voltage for that isotope.
High Voltage Operational Amplifier
• HVOA has a closed loop gain of x1500 (10 V in = 15 kV out)
• Load = 2.2 nF
• Response time to within 0.1% of final output was to be 100 µs
• Peak output current > 300 mA
• Amplifier designed to our specs by Lastek (Adelaide) was initially used, TREK model P0842 is now used
6
Sequencer – original concept Programmable, 65k x 16 bit SRAM
Lookup-table-based state machine
- clocked by 16 bit counter
- absolute determinism & repeatability
SRAM lookup table (65k x 16 bit),
- Time resolution = Clock period
- SRAM address = ‘Time’
- 15 Data bits = 15 signal outputs
All-synchronous design, no glitches
Max cycle length = 65535 clock periods
- Clock period 1µs<dT<128µs
- Pulse widths 1µs<Tp<8.4s (65535x128µs)
Synchronism < 5 ns for all outputs,
Time error < 20 ppm
PC interface is used for memory loading
but…
PC is not needed for stand-alone operation 7
Entering User Data Visual Basic data-entry program
Code embodies limits of hardware –
illegal entries are rejected
Data is saved in a text file for later
memory-loading
Provides visual rendition of output signals:
8
The Need for Change
In 2010 after almost 20 years of fault-free operation we were faced with these issues:
• Difficulty in sourcing obsolete components (e.g. 65k x 16 SRAM)
• Complex interface (bidirectional optocouplers, 8255 I/O cards)
• I/O hardware doesn’t work easily under Windows XP, doesn’t work at all with
Windows 7
• Design is inflexible – fixed architecture
• Design doesn’t make efficient use of available memory
‘Linear’ mapping of SRAM ‘address’ to ‘time’ imposes a fundamental limit of
(max measurement time per cycle) = (time resolution) x (65536)
This can result in thousands of consecutive RAM addresses containing identical data,
during a 14C phase for example.
9
2010 Redesign using Programmable Logic
• National Instruments NI PCI-7811R FPGA card
160 I/O lines, 720 kb user memory
40 MHz clock, 1M gate Xilinx Virtex 2 FPGA
PCI interface, Programmed using LabVIEW
Cost ~ $2000
• Benefits
- Allows for > 4 (8 max) isotopic species,
- Improves efficiency of memory use (‘vectorised’ memory
use, by looping),
- Overcomes 65535-time-tick limitation for all pulse
durations, now 232 – 1 time ticks max,
- Fundamental time resolution can be 0.1 µs for all
sequence durations,
- FPGA implementation has great flexibility & extendability
- FPGA card is well-supported, inexpensive & requires no
special FPGA programming skills
10
New Sequencer Implementation
• 15 User outputs
• Provision for 9 extra outputs
• Additional timebase outputs
• FPGA card is located inside
host computer (below)
11
New Sequencer Implementation (2)
12
FPGA Design Methodology
‘Raw’ FPGA design involves a steep learning curve:
• Competently using FPGA manufacturers development software
• How to best use the features of the selected FPGA
• Knowledge of high-level logic design, e.g. languages like VHDL, Verilog
• How to effectively perform simulation & achieve timing closure, & finally,
• How to lay out a high-speed PCB and mount a 560 pin BGA package on it without
damage, and then hoping that everything finally works in the real world…
NI FPGA Application Boards
• Eliminates most of the issues above
• Supported by FPGA-centric functions in the FPGA module of LabVIEW,
• Designer is free to concentrate on solving the actual system design problem.
13
Sequencer Support Utilities
The FPGA sequencer requires 2 support utilities:
1. A user interface, hosted on a PC, which handles all interactions with users
- selection of data files,
- visualisation of sequencer signals,
- loading of data files to the FPGA,
- selection of user-options
- uses ‘normal’ LabVIEW functions, controls & front-panel
2. A configuration program, which defines the sequencer design in the FPGA
- equivalent to a schematic circuit diagram (hardware-focus) or a VHDL description (function-focus)
- uses FPGA-specific LabVIEW functions targeting unique FPGA features, and,
- uses normal LabVIEW Boolean & Binary arithmetic vi’s, but
- NO front-panel controls, indicators or artwork (because there’s no front panel)
14
LabVIEW PC-resident User Interface
• LV State machine structure
• True graphical display of outputs
- Can be panned & zoomed
15
LabVIEW FPGA-resident Code (part)
Note 1: ‘normal’ LabVIEW elements:
• ‘While’ loop
• Shift Registers
• Multiplexers
• Array functions
• Binary constants
• Binary Arithmetic
• Increment/Decrement
• Boolean variables
• Logical operators
Note 2: LabVIEW FPGA-specific constructs
• I/O connector pane
• FPGA Memory function
• No front panel
• No graphs, control boxes, inputs, indicators
16
Actual FPGA Output Waveforms
Bench test of 12C Measurement Trace 4: Detector-end gating signal
Trace 3: Injection-end gating signal
Trace 2: Ion current chopping signal
Trace 1: HV multiplexer value Mux1.Mux0
Time expanded x5, showing 50% duty cycle
Note:
- 500 µs HV bouncer delay
- Beam off-axis during HV changes
17
Future Development
• Possible to extend to up to 8 separate isotopic species, needing
- Additional 8 gating lines,
- 1 additional multiplexer select line (increase from 2 to 3),
- 4 additional DACs for defining the additional bouncer voltages,
• 100 ns time resolution (presently 1 µs) for finer timing
• Increased maximum count duration from 8.4 s to 430 s at 100 ns time resolution
• “Cycle.exe” spreadsheet program needs upgrading to support this
18
Acknowledgements
In successfully completing this redesign the invaluable assistance of the following
people is gratefully acknowledged:
• Tristan Steele (formerly with ANSTO) who demonstrated the potential of the NI
FPGA card for this project, and provided initial coding ideas
• Dr. Stephen Boronkay, Balaton Technologies, Sydney, who undertook all LabVIEW
programming
• ANTARES scientists who endorsed a redesign using NI FPGA hardware
• The organisers of ATF 2014 for providing the opportunity to describe our system
Thank you
19