computers central processor unit. basic computer system main memory alucntl..... bus controller...
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Computers
Central Processor Unit
Basic Computer System
MAIN MEMORY
ALU CNTL.....
BUS
CONTROLLER
Processor
I/O moduleInterconnections
BUS
Memory
Computer ComponentsProcessing (CPU)
Arithmetic Logic Unit Control Unit Registers Word Clock Instruction sets
Interconnection Local bus Peripheral bus
Primary Storage RAM/ROM Cache
Input/Output Channel Controller Buffers
CPU’s
Inside the CPU
Registers
Instruction Cycle
FetchProcessor locates the next instruction
and loads it into the Instruction Register
ExecuteProcessor carries out the instruction
currently in the Instruction Register
Increment the program counter
CPU Cycle
Start FETCH EXECUTE Halt
Increment Program Counter
FETCH EXECUTE
Instruction Format
Instruction: Operation Codes OperandsWord: set of bits held by registers in the CPU. May contain instructions or data.
OP Code Operands
4 Bits 12 Bits
ASSEMBLER CODE
MACHINE CODE ACTION
op address L(mmm) 0001 mmm Load from memory to
Accum S(mmm) 0010 mmm Store Accum to memory A(mmm) 0101 mmm Add from mmm to Accum
Assembler & Machine Code
Example
Assembler Code FragmentL(940) Load the contents of 940A(941) Add the contents of 941 to
the accumulatorS(941) Store the accumulator to
address 941
ADD numbers in location #940 and #941 STORE them in memory location #941.
Initial State
IR
300 PC
CONTROL ARITHMETIC-LOGIC
ACCUM
PROGRAM
1940
5941
2941
300
301
302
DATA
0003
0002
940
941
CPU Registers: User-visible
Data RegistersUser defined: data values to be used by
the program
Address RegistersIndex register: for relative address
baseSegment pointer (s): for op. System &
other appsStack pointer: for base of the stackCondition codes (flags)
CPU Registers: Control and Status
ExecutionProgram counter: Address of next instruction to be
fetchedInstruction Register: content of instruction most
recently fetched
Memory AccessMemory Address Register: address in memory for
next put or fetchMemory Buffer Register: data for next put or last
fetch
I/O ProcessingI/O Address Register: “I/O Buffer Register: “
Initial State
IR
300 PC
CONTROL ARITHMETIC-LOGIC
ACCUM
PROGRAM
1940
5941
2941
300
301
302
DATA
0003
0002
940
941
L(940) Load the contents of 940: Fetch
IR
300 PC
CONTROL ARITHMETIC-LOGIC
ACCUM
PROGRAM
1940
5941
2941
300
301
302
DATA
0003
0002
940
941
1 940
940 IR
300 PC
CONTROL ARITHMETIC-LOGIC
ACCUM
PROGRAM
1940
5941
2941
300
301
302
1
DATA
0003
0002
940
941
L(940) Load the contents of 940: Execute
3
940 IR
300 PC
CONTROL ARITHMETIC-LOGIC
3 ACCUM
PROGRAM
1940
5941
2941
300
301
302
1
DATA
0003
0002
940
941
L(940) Load the contents of 940: Increment
301
A(941) Add the contents of 941 to
the accumulator Fetch
IR
301 PC
CONTROL ARITHMETIC-LOGIC
3 ACCUM
PROGRAM
1940
5941
2941
300
301
302
DATA
0003
0002
940
941
9415
941 IR
301 PC
CONTROL ARITHMETIC-LOGIC
3 ACCUM
PROGRAM
1940
5941
2941
300
301
302
5
DATA
0003
0002
940
941
A(941) Add the contents of 941 to
the accumulator Execute
5
941 IR
301 PC
CONTROL ARITHMETIC-LOGIC
5 ACCUM
PROGRAM
1940
5941
2941
300
301
302
5
DATA
0003
0002
940
941
A(941) Add the contents of 941 to
the accumulator Increment
302
S(941) Store the accumulator to address 941
Fetch
IR
302 PC
CONTROL ARITHMETIC-LOGIC
5 ACCUM
PROGRAM
1940
5941
2941
300
301
302
DATA
0003
0002
940
941
9412
941 IR
302 PC
CONTROL ARITHMETIC-LOGIC
5 ACCUM
PROGRAM
1940
5941
2941
300
301
302
2
DATA
0003
0002
940
941
S(941) Store the accumulator to address 941
Execute
0005
Instructions
Instructions are broken into parts for operation codes and for addressesThe length of the word dictates how many choices there are of each oneMore extensive instructions may require either multi-word reads or the use of external subroutines
Uses for Instructions
Data Movement: transfer data to or from memory or peripheral deviceData Transformation: Boolean instructions (NOT, AND, OR, XOR) Arithmetic Operations: ADD, SHIFT
Sequence Control: alter the sequence of instructions (BRANCH, JUMP)
Instruction Format
Instruction: Operation Codes OperandsWord: set of bits held by registers in the CPU. May contain instructions or data.
OP Code Operands
4 Bits 12 Bits
Assembler & Machine Code
Machine code and assembler code are the same except that machine code uses the binary representationsAssembler requires managing memory and registers directlyMachine language (assembler) activates chip instructions and microcode instructions stored on ROM
ASSEMBLERCODE
MACHINECODE
USE
L(mmm) 0001mmm Load from memory to AccumS(mmm) 0010mmm Store Accum to memoryA(mmm) 0101mmm Add from mmm to Accum
Assembler & Machine Code
Clock Rate
System timing pulse frequency
Measured in hertz (HZ) – cycles per second
Cycle time = 1/clock rateDon’t confuse with
instruction execution rate (MIPS, MFLOPS)
Word Size
Amount of data CPU processes at one timeHow much faster is a 64-bit processor than a 32-bit?What’s the ratio of associated computer components?
The Physical CPU
Tubes -> transistors -> integrated circuits-> microchipsMicroprocessorsAll circuits and connections needed to implement a CPU
Chip capacity doubles every 18 Months.
And a corollary…
Rock’s Law – The cost of fabrication doubles every four years
Gordon Moore
Moore’s Law
Moore’s Law in Action
© 2000 Intel Corporation
Computer Theory
Mathematical foundations of computingTuring MachinesVon Neumann Architecture
Turing Machines
Theoretical model of a computer developed by Alan M. Turing in 1930’s.Basis for theoretical analysis of languages and machine complexity
Turing Machine
Infinite TapeThe tape is divided into squares any of which
can contain a tape symbol. Initially the tape contains a string of input symbols in the beginning cells and blanks in the others
Tape HeadReads or writes tape symbols
Finite Control limited # of possible internal states
One instruction = One change of state.
Turing Machine
FINITE CONTROL
TAPE
a a a a B B B B
STATE
Von Neumann Architecture:Stored Program Machine
CPUFast MemorySlow StorageBinary Program: executed in sequence
Computer behavior is determined by stored programs.
John Von Neumann and ENIAC