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Page 1: FPGA Co-Processors in SDR Signal Processing · Processor Post-Processor Control Data Data Input Processor Co-Processor Control ... Co-Processing on FPGAs Processor on FPGAProcessor

© 2003 Altera

®

FPGA Co-Processors in SDR Signal ProcessingFPGA Co-Processors in SDR Signal Processing

Proceeding of the SDR 03 Technical Conference and Product Exposition. Copyright © 2003 SDR Forum. All Rights Reserved

Page 2: FPGA Co-Processors in SDR Signal Processing · Processor Post-Processor Control Data Data Input Processor Co-Processor Control ... Co-Processing on FPGAs Processor on FPGAProcessor

2© 2003 Altera

®

AgendaAgendaApplications of FPGA-Based Co-Processors SDRConsiderations for Co-Processor DesignDevelopment Tools & Methodologies Available from Altera to Build Co-Processors− SOPC Builder− DSP Builder

FPGA Co-Processor Development Examples− QAM Modulator− FIR Filter

Proceeding of the SDR 03 Technical Conference and Product Exposition. Copyright © 2003 SDR Forum. All Rights Reserved

Page 3: FPGA Co-Processors in SDR Signal Processing · Processor Post-Processor Control Data Data Input Processor Co-Processor Control ... Co-Processing on FPGAs Processor on FPGAProcessor

3© 2003 Altera

®

Techniques of Implementing of SDR System ReconfigurationTechniques of Implementing of SDR System Reconfiguration

Using parameterized radio (and protocol) modules

Exchange of (a) single component(s) within a module

Exchange of complete radio modules or protocol layers

Proceeding of the SDR 03 Technical Conference and Product Exposition. Copyright © 2003 SDR Forum. All Rights Reserved

Page 4: FPGA Co-Processors in SDR Signal Processing · Processor Post-Processor Control Data Data Input Processor Co-Processor Control ... Co-Processing on FPGAs Processor on FPGAProcessor

4© 2003 Altera

®

Using parameterized radio (and protocol) modulesUsing parameterized radio (and protocol) modules

Applicable within a standard− CDMA2000 – Spreading factors, Viterbi

parameterization− 3GPP – spreading factor, Viterbi parameterization

Not Applicable across widely varying standards− GSM, 3GPP – Need to replace entire physical layer− GSM, CDMA2000 – Need to replace entire network

layer - GSM-MAP and ANSI-41

Proceeding of the SDR 03 Technical Conference and Product Exposition. Copyright © 2003 SDR Forum. All Rights Reserved

Page 5: FPGA Co-Processors in SDR Signal Processing · Processor Post-Processor Control Data Data Input Processor Co-Processor Control ... Co-Processing on FPGAs Processor on FPGAProcessor

5© 2003 Altera

®

Exchange of (a) single component(s) within a moduleExchange of (a) single component(s) within a module

Applicable within a standard− 3GPP – Turbo, Viterbi decoding− GSM/EDGE – Transceiver chain

Not Applicable across widely varying standards− GSM, 3GPP – Need to replace entire physical

layer− GSM, CDMA2000 – Need to replace entire

network layer - GSM-MAP and ANSI-41

Proceeding of the SDR 03 Technical Conference and Product Exposition. Copyright © 2003 SDR Forum. All Rights Reserved

Page 6: FPGA Co-Processors in SDR Signal Processing · Processor Post-Processor Control Data Data Input Processor Co-Processor Control ... Co-Processing on FPGAs Processor on FPGAProcessor

6© 2003 Altera

®

Exchange of complete radio modules or protocol layersExchange of complete radio modules or protocol layers

Applicable across radio standards− GSM to EDGE to 3GPP to CDMA2000 to WIFI

to ….− GSM-MAP to ANSI-41

Proceeding of the SDR 03 Technical Conference and Product Exposition. Copyright © 2003 SDR Forum. All Rights Reserved

Page 7: FPGA Co-Processors in SDR Signal Processing · Processor Post-Processor Control Data Data Input Processor Co-Processor Control ... Co-Processing on FPGAs Processor on FPGAProcessor

7© 2003 Altera

®

Narrowband System PartitioningNarrowband System Partitioning

Proceeding of the SDR 03 Technical Conference and Product Exposition. Copyright © 2003 SDR Forum. All Rights Reserved

Page 8: FPGA Co-Processors in SDR Signal Processing · Processor Post-Processor Control Data Data Input Processor Co-Processor Control ... Co-Processing on FPGAs Processor on FPGAProcessor

8© 2003 Altera

®

Wideband System PartitioningWideband System Partitioning

Proceeding of the SDR 03 Technical Conference and Product Exposition. Copyright © 2003 SDR Forum. All Rights Reserved

Page 9: FPGA Co-Processors in SDR Signal Processing · Processor Post-Processor Control Data Data Input Processor Co-Processor Control ... Co-Processing on FPGAs Processor on FPGAProcessor

9© 2003 Altera

®

FPGA Based SDR RadioFPGA Based SDR Radio

FPGA

MicroController

DDC & FIR

FIR

Symbol Rate

Symbol Rate

Antenna Array

Wideband Signal Detection

Transmit

Proceeding of the SDR 03 Technical Conference and Product Exposition. Copyright © 2003 SDR Forum. All Rights Reserved

Page 10: FPGA Co-Processors in SDR Signal Processing · Processor Post-Processor Control Data Data Input Processor Co-Processor Control ... Co-Processing on FPGAs Processor on FPGAProcessor

10© 2003 Altera

®

Dedicated Hardware Architecture

Perf

orm

ance

(MM

AC

s/Se

c)DSP System Architecture OptionsDSP System Architecture Options

DSP DSP DSP DSP

DSP DSP DSP DSP

DSP DSP DSP DSP

DSP DSP DSP DSP

Processor ArrayStand-Alone Processor

DSP

Processor + Co-Processor

DSP

Proceeding of the SDR 03 Technical Conference and Product Exposition. Copyright © 2003 SDR Forum. All Rights Reserved

Page 11: FPGA Co-Processors in SDR Signal Processing · Processor Post-Processor Control Data Data Input Processor Co-Processor Control ... Co-Processing on FPGAs Processor on FPGAProcessor

11© 2003 Altera

®

Exploring the DSP Design SpaceExploring the DSP Design Space

Digital SignalProcessor

Digital SignalProcessor

Farm

Digital SignalProcessor

with Co-Processor

CustomASIC

Perf

orm

ance

Flexibility

ConventionalProcessor

ConventionalProcessor

AlteraFPGA

Co-Processor

AlteraFPGA with

Nios & Co-Processor

Digital SignalProcessor

AlteraFPGA

Co-Processor

AlteraFPGA

Algorithmin Hardware

The Flexibility Zone

Proceeding of the SDR 03 Technical Conference and Product Exposition. Copyright © 2003 SDR Forum. All Rights Reserved

Page 12: FPGA Co-Processors in SDR Signal Processing · Processor Post-Processor Control Data Data Input Processor Co-Processor Control ... Co-Processing on FPGAs Processor on FPGAProcessor

12© 2003 Altera

®

Co-Processing, Pre-Processing and Post-ProcessingCo-Processing, Pre-Processing and Post-Processing

Pre-Processor Processor

Control

DataData Input

Post-ProcessorProcessor

Control

DataData Input

Co-ProcessorProcessorControl

Data

Proceeding of the SDR 03 Technical Conference and Product Exposition. Copyright © 2003 SDR Forum. All Rights Reserved

Page 13: FPGA Co-Processors in SDR Signal Processing · Processor Post-Processor Control Data Data Input Processor Co-Processor Control ... Co-Processing on FPGAs Processor on FPGAProcessor

13© 2003 Altera

®

FIRFIR

Co-Processing on FPGAsCo-Processing on FPGAs

Processor External to FPGAProcessor External to FPGAProcessor on FPGAProcessor on FPGA

FPGAFPGA

MemoryMemory

MemoryMemory

NCO

FPGA

IQMap

NCO

IQMap

MemoryMemory

ProcessorProcessor

Proceeding of the SDR 03 Technical Conference and Product Exposition. Copyright © 2003 SDR Forum. All Rights Reserved

Page 14: FPGA Co-Processors in SDR Signal Processing · Processor Post-Processor Control Data Data Input Processor Co-Processor Control ... Co-Processing on FPGAs Processor on FPGAProcessor

14© 2003 Altera

®

Off-Loading Algorithms to Co-Processor Reduces Number or Cost of Digital Signal Processors

Applications− Algorithms with Large Amount of Digital Signal Processing &

Small Amount of Control Processing

When Do FPGA Co-Processors Reduce System Cost?When Do FPGA Co-Processors Reduce System Cost?

Expensive Array to DSP + FPGA

Expensive DSP to Inexpensive DSP + FPGA

DSP DSP DSP DSP

DSP DSP DSP DSP

DSP DSP DSP DSP

DSP DSP DSP DSP

FIR

NCO

IQMap

MemoryMemory

DSP

MemoryMemory

DSP$$$

Proceeding of the SDR 03 Technical Conference and Product Exposition. Copyright © 2003 SDR Forum. All Rights Reserved

Page 15: FPGA Co-Processors in SDR Signal Processing · Processor Post-Processor Control Data Data Input Processor Co-Processor Control ... Co-Processing on FPGAs Processor on FPGAProcessor

© 2003 Altera

®

FPGA Co-processor Design Tools and IPFPGA Co-processor Design Tools and IP

Proceeding of the SDR 03 Technical Conference and Product Exposition. Copyright © 2003 SDR Forum. All Rights Reserved

Page 16: FPGA Co-Processors in SDR Signal Processing · Processor Post-Processor Control Data Data Input Processor Co-Processor Control ... Co-Processing on FPGAs Processor on FPGAProcessor

16© 2003 Altera

®

Dedicated Hardware Architecture

Stand-alone Processor

Processor + Co-Processor

FPGA Co-Processor Design ToolsFPGA Co-Processor Design ToolsSOPC BuilderSOPC Builder DSP BuilderDSP Builder

Proceeding of the SDR 03 Technical Conference and Product Exposition. Copyright © 2003 SDR Forum. All Rights Reserved

Page 17: FPGA Co-Processors in SDR Signal Processing · Processor Post-Processor Control Data Data Input Processor Co-Processor Control ... Co-Processing on FPGAs Processor on FPGAProcessor

© 2003 Altera

®

DSP BuilderDSP Builder

Proceeding of the SDR 03 Technical Conference and Product Exposition. Copyright © 2003 SDR Forum. All Rights Reserved

Page 18: FPGA Co-Processors in SDR Signal Processing · Processor Post-Processor Control Data Data Input Processor Co-Processor Control ... Co-Processing on FPGAs Processor on FPGAProcessor

18© 2003 Altera

®

System-Level Design

MATLABAlgorithm Development

and Analysis

SIMULINK

Altera® DSP BuilderAltera® DSP BuilderFixed-Point Hardware Architecture LibrarySystem Architecture IP LibraryAutomatic HDL Generation Automatic Testbench GenerationIntegrated Link to Altera Development BoardsReal-Time Link from Development Board Back to SimulinkLink to SOPC Builder and NiosCustom Instruction

Simulation&

Synthesis

SystemArchitecture

IP Library

Fixed-PointArchitecture

Library

Testbench

HDL Generation

Proceeding of the SDR 03 Technical Conference and Product Exposition. Copyright © 2003 SDR Forum. All Rights Reserved

Page 19: FPGA Co-Processors in SDR Signal Processing · Processor Post-Processor Control Data Data Input Processor Co-Processor Control ... Co-Processing on FPGAs Processor on FPGAProcessor

19© 2003 Altera

®

Dedicated Hardware Architecture

Stand-alone Processor

Processor + Co-Processor

FPGA Co-Processor Design ToolsFPGA Co-Processor Design ToolsSOPC BuilderSOPC Builder DSP BuilderDSP Builder

Proceeding of the SDR 03 Technical Conference and Product Exposition. Copyright © 2003 SDR Forum. All Rights Reserved

Page 20: FPGA Co-Processors in SDR Signal Processing · Processor Post-Processor Control Data Data Input Processor Co-Processor Control ... Co-Processing on FPGAs Processor on FPGAProcessor

20© 2003 Altera

®

Datapath/Co-processor Design using DSP Builder

Creates HDL Code

Creates Simulation Testbench

Download Design to DSP Development Kits

Place and Route

HDL Synthesis

Integrates Co-processor into System

SOPC Builder

Proceeding of the SDR 03 Technical Conference and Product Exposition. Copyright © 2003 SDR Forum. All Rights Reserved

Page 21: FPGA Co-Processors in SDR Signal Processing · Processor Post-Processor Control Data Data Input Processor Co-Processor Control ... Co-Processing on FPGAs Processor on FPGAProcessor

21© 2003 Altera

®

Library ComponentsLibrary ComponentsAltera LibraryArithmeticBus ManipulationComplex Signals DSP BoardLogical ComponentsMegaCore IPRate ChangeSOPC PortsState MachineStorage

Proceeding of the SDR 03 Technical Conference and Product Exposition. Copyright © 2003 SDR Forum. All Rights Reserved

Page 22: FPGA Co-Processors in SDR Signal Processing · Processor Post-Processor Control Data Data Input Processor Co-Processor Control ... Co-Processing on FPGAs Processor on FPGAProcessor

22© 2003 Altera

®

IP MegaCore FunctionsIP MegaCore Functions

DSP Builder MegaCoresFIRReed SolomonViterbiFFTNCO

DSP Builder MegaCoresFIRReed SolomonViterbiFFTNCO

Proceeding of the SDR 03 Technical Conference and Product Exposition. Copyright © 2003 SDR Forum. All Rights Reserved

Page 23: FPGA Co-Processors in SDR Signal Processing · Processor Post-Processor Control Data Data Input Processor Co-Processor Control ... Co-Processing on FPGAs Processor on FPGAProcessor

23© 2003 Altera

®

FIR MegaCore FunctionFIR MegaCore Function

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Page 24: FPGA Co-Processors in SDR Signal Processing · Processor Post-Processor Control Data Data Input Processor Co-Processor Control ... Co-Processing on FPGAs Processor on FPGAProcessor

24© 2003 Altera

®

NCO MegaCore FunctionNCO MegaCore Function

Proceeding of the SDR 03 Technical Conference and Product Exposition. Copyright © 2003 SDR Forum. All Rights Reserved

Page 25: FPGA Co-Processors in SDR Signal Processing · Processor Post-Processor Control Data Data Input Processor Co-Processor Control ... Co-Processing on FPGAs Processor on FPGAProcessor

25© 2003 Altera

®

State Machine BuilderState Machine Builder

Proceeding of the SDR 03 Technical Conference and Product Exposition. Copyright © 2003 SDR Forum. All Rights Reserved

Page 26: FPGA Co-Processors in SDR Signal Processing · Processor Post-Processor Control Data Data Input Processor Co-Processor Control ... Co-Processing on FPGAs Processor on FPGAProcessor

26© 2003 Altera

®

SignalCompilerSignalCompilerGenerates VHDL Design FilesGenerates Tool Command Language(TCL) ScriptsGenerates TestbenchEnables

Parameterizationof IP BlocksLaunch HardwareCompilation from theSimulink Cockpit

Proceeding of the SDR 03 Technical Conference and Product Exposition. Copyright © 2003 SDR Forum. All Rights Reserved

Page 27: FPGA Co-Processors in SDR Signal Processing · Processor Post-Processor Control Data Data Input Processor Co-Processor Control ... Co-Processing on FPGAs Processor on FPGAProcessor

27© 2003 Altera

®

SignalTap II Logic AnalyzerSignalTap II Logic AnalyzerBuilt-In SignalTap II Interface to DSP BuilderCaptures Signal Activity from Internal Device NodesDisplays Captured Data in MATLAB/Simulink

Proceeding of the SDR 03 Technical Conference and Product Exposition. Copyright © 2003 SDR Forum. All Rights Reserved

Page 28: FPGA Co-Processors in SDR Signal Processing · Processor Post-Processor Control Data Data Input Processor Co-Processor Control ... Co-Processing on FPGAs Processor on FPGAProcessor

28© 2003 Altera

®

Automated Link to RTL SimulatorAutomated Link to RTL SimulatorSIMULINK Domain ModelSim Domain

Compare

Proceeding of the SDR 03 Technical Conference and Product Exposition. Copyright © 2003 SDR Forum. All Rights Reserved

Page 29: FPGA Co-Processors in SDR Signal Processing · Processor Post-Processor Control Data Data Input Processor Co-Processor Control ... Co-Processing on FPGAs Processor on FPGAProcessor

29© 2003 Altera

®

Sub-System BuilderSub-System BuilderImport Existing VHDL Design into SimulinkSimulink Simulation Options− Convert into DSP Builder Blocks or MATLAB Functions− Treat VHDL Design as Black Box

Proceeding of the SDR 03 Technical Conference and Product Exposition. Copyright © 2003 SDR Forum. All Rights Reserved

Page 30: FPGA Co-Processors in SDR Signal Processing · Processor Post-Processor Control Data Data Input Processor Co-Processor Control ... Co-Processing on FPGAs Processor on FPGAProcessor

30© 2003 Altera

®

Stratix 1S25/1S80 DSP Development BoardStratix 1S25/1S80 DSP Development Board

Prototyping Area

Push Button Switches

9-pin RS232 Connector

LEDs

Altera Nios ExpansionPrototype Connector

14-bit, 165 Mhz D/A

12-bit, 125 Mhz A/D

5V Power Supply

SMA Connector

80-pin I/O Connector

Texas Instruments Connectors can be found on the underside of the board

40-pin Connector For Analog DevicesEvaluation Boards

Proceeding of the SDR 03 Technical Conference and Product Exposition. Copyright © 2003 SDR Forum. All Rights Reserved

Page 31: FPGA Co-Processors in SDR Signal Processing · Processor Post-Processor Control Data Data Input Processor Co-Processor Control ... Co-Processing on FPGAs Processor on FPGAProcessor

© 2003 Altera

®

FPGA Co-processor Reference DesignFPGA Co-processor Reference Design

Turbo Encoder for HSDPATurbo Encoder for HSDPA

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Page 32: FPGA Co-Processors in SDR Signal Processing · Processor Post-Processor Control Data Data Input Processor Co-Processor Control ... Co-Processing on FPGAs Processor on FPGAProcessor

32© 2003 Altera

®

Turbo Encoder Co-processor Reference Design (TI Solution)Turbo Encoder Co-processor Reference Design (TI Solution)

Interface to TI DSP EMIF (External Memory Interface)− Other processor interfaces in development

Uses DSP Processor’s on-chip DMAWrapper for Turbo Encoder MegaCore− Can select a different configuration (e.g. block

size) for each data packet/blockSoftware Libraries

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Page 33: FPGA Co-Processors in SDR Signal Processing · Processor Post-Processor Control Data Data Input Processor Co-Processor Control ... Co-Processing on FPGAs Processor on FPGAProcessor

33© 2003 Altera

®

Turbo Co-processor Block Diagram (TI Solution)Turbo Co-processor Block Diagram (TI Solution)

Atlantic S

lave Sink

Atlantic M

aster S

ourceTurbo

Encoder

Core

FIFO

Serializer

De-serializer

Control Registers

EMIF Interface

TI DSP EMIF DMA Controller

Turbo Core Wrapper

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Page 34: FPGA Co-Processors in SDR Signal Processing · Processor Post-Processor Control Data Data Input Processor Co-Processor Control ... Co-Processing on FPGAs Processor on FPGAProcessor

34© 2003 Altera

®

Turbo Co-processor Block Diagram (ADI Solution)Turbo Co-processor Block Diagram (ADI Solution)

Atlantic S

lave Sink

Atlantic M

aster S

ource

FIFO

Serializer

De-serializer

Control Registers

Link Port Rx

ADI DSP DMA Controller

Turbo Core Wrapper

Link Port TxSlave

Turbo

Encoder

Core

Proceeding of the SDR 03 Technical Conference and Product Exposition. Copyright © 2003 SDR Forum. All Rights Reserved

Page 35: FPGA Co-Processors in SDR Signal Processing · Processor Post-Processor Control Data Data Input Processor Co-Processor Control ... Co-Processing on FPGAs Processor on FPGAProcessor

35© 2003 Altera

®

Data BufferingData BufferingFIFOs in Atlantic slave sink store EMIF 64 byte bursts whilst being serialised into coreSlave sink in receive converter has similar FIFOFIFOs introduce latency but− throughput is maintained− System bus not tied up during

serialization/deserialization

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Page 36: FPGA Co-Processors in SDR Signal Processing · Processor Post-Processor Control Data Data Input Processor Co-Processor Control ... Co-Processing on FPGAs Processor on FPGAProcessor

36© 2003 Altera

®

TI Development EnvironmentTI Development Environment

Stratix DSP Development Board plugs into EMIF slots of TI 6713 DSK (DSP Starter Kit)Limited to Asynchronous EMIF interface due to design of TI card− Customer designs may use synchronous

Interface

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Page 37: FPGA Co-Processors in SDR Signal Processing · Processor Post-Processor Control Data Data Input Processor Co-Processor Control ... Co-Processing on FPGAs Processor on FPGAProcessor

37© 2003 Altera

®

TI Development HardwareTI Development Hardware

Proceeding of the SDR 03 Technical Conference and Product Exposition. Copyright © 2003 SDR Forum. All Rights Reserved

Page 38: FPGA Co-Processors in SDR Signal Processing · Processor Post-Processor Control Data Data Input Processor Co-Processor Control ... Co-Processing on FPGAs Processor on FPGAProcessor

38© 2003 Altera

®

Software EnvironmentSoftware Environment

Running on TI DSPUses EDMA controller to transfer data− To and from accelerator

Asynchronous, streaming, interface− Callback when packet is complete− Can submit 2nd packet before 1st is done

Callbacks occur in order

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Page 39: FPGA Co-Processors in SDR Signal Processing · Processor Post-Processor Control Data Data Input Processor Co-Processor Control ... Co-Processing on FPGAs Processor on FPGAProcessor

39© 2003 Altera

®

Header fileHeader filetypedef void (* TXCALLBACK)(

void * handle);typedef void (* RXCALLBACK)(

uchar * data,void * handle);

void turbo_encode(const uchar * data,uchar * output,uint bits,TXCALLBACK txcallback,RXCALLBACK rxcallback,void * handle);

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Page 40: FPGA Co-Processors in SDR Signal Processing · Processor Post-Processor Control Data Data Input Processor Co-Processor Control ... Co-Processing on FPGAs Processor on FPGAProcessor

40© 2003 Altera

®

Using the acceleratorUsing the accelerator

Call function for each packet− Packets can have any block size

Data is sent to encoder− Queued if accelerator is already busy

txcallback called when data has been sent rxcallback is called once results availableInterface can be changed if desired

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Page 41: FPGA Co-Processors in SDR Signal Processing · Processor Post-Processor Control Data Data Input Processor Co-Processor Control ... Co-Processing on FPGAs Processor on FPGAProcessor

41© 2003 Altera

®

Cost Analysis Example (1)Cost Analysis Example (1)

TI C64 DSP: $33.00

136/600 MHz based on 9.7cycles/bit (Source: TI) C6416/600MHz @ $145 1kunit pricing (Source: TI)

14.4Mbits/s Turbo Encoder

Cyclone: $10.75

2600 LE equivalent cost Based on EP1C3T100C8 1k units (July 2003)

Proceeding of the SDR 03 Technical Conference and Product Exposition. Copyright © 2003 SDR Forum. All Rights Reserved

Page 42: FPGA Co-Processors in SDR Signal Processing · Processor Post-Processor Control Data Data Input Processor Co-Processor Control ... Co-Processing on FPGAs Processor on FPGAProcessor

42© 2003 Altera

®

Cost Analysis Example (2)Cost Analysis Example (2)

TI C64 DSP: $136.00

563/600 MHz based on 9.7cycles/bit (Source: TI) C6416/600MHz @ $145 1kunit pricing (Source: TI)

58Mbits/s Turbo Encoder

Cyclone: $21.58

2600 LE equivalent cost Based on EP1C3T100C6 1k units (July 2003)

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Page 43: FPGA Co-Processors in SDR Signal Processing · Processor Post-Processor Control Data Data Input Processor Co-Processor Control ... Co-Processing on FPGAs Processor on FPGAProcessor

43© 2003 Altera

®

TI Reference Design SummaryTI Reference Design Summary

Contents− Turbo Encoder MegaCore (OpenCore)− TI EMIF Interface− Wrapper− DSP Software Libraries

Expected Availability− September 2003

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Page 44: FPGA Co-Processors in SDR Signal Processing · Processor Post-Processor Control Data Data Input Processor Co-Processor Control ... Co-Processing on FPGAs Processor on FPGAProcessor

44© 2003 Altera

®

ADI Reference Design SummaryADI Reference Design SummaryContents− Turbo Encoder MegaCore (OpenCore)− ADI Link Port Interface− Wrapper− DSP Software Libraries

Expected Availability− Q1 2004

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Page 45: FPGA Co-Processors in SDR Signal Processing · Processor Post-Processor Control Data Data Input Processor Co-Processor Control ... Co-Processing on FPGAs Processor on FPGAProcessor

45© 2003 Altera

®

Future HSDPA FunctionalityFuture HSDPA Functionality

Currently implemented:•Channel coding

Future additions:•CRC attachment•Rate Matching •DTX generation•Interleaving

PhCH

#1

PhCH

#2

TrCH Multiplexing

iiGiii gggg ,,,, 321 Κ

iiDiii hhhh ,,,, 321 Κ

iiViii ffff ,,,, 321 Κ

Sssss ,,,, 321 Κ

Rwwww ,,,, 321 Κ

pUppp vvvv ,,,, 321 Κ

iiEiii cccc ,,,, 321 Κ

iimBimimim bbbb ,,,, 321 Κ

iimAimimim aaaa ,,,, 321 Κ

CRC attachment

Rate matchingRate

matching

1st insertion of DTXindication

iiQiii qqqq ,,,, 321 Κ

1st interleaving

Radio frame segmentation

2nd insertion of DTXindication

pUppp uuuu ,,,, 321 Κ2nd interleaving

Physical channelsegmentation

Physical channel mapping

iirKiririr oooo ,,,, 321 Κ

TrBk concatenation /Code block segmentation

Channel coding

CCTrCH

Source: 3GPP TS 25.212 V5.3.0 (2002-12), page 12, figure 2

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Page 46: FPGA Co-Processors in SDR Signal Processing · Processor Post-Processor Control Data Data Input Processor Co-Processor Control ... Co-Processing on FPGAs Processor on FPGAProcessor

© 2003 Altera

®

QAM Modulator Co-Processor Design Example

QAM Modulator Co-Processor Design Example

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Page 47: FPGA Co-Processors in SDR Signal Processing · Processor Post-Processor Control Data Data Input Processor Co-Processor Control ... Co-Processing on FPGAs Processor on FPGAProcessor

47© 2003 Altera

®

Modem Reference DesignModem Reference DesignInstalled with Code Composer Studio As a Tutorial

− C:\ti\tutorial\dsk6711\modemUsed to DemonstrateCCS Functionality16 QAM TX Modem

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48© 2003 Altera

®

Main

Initialize Add Noise Signal

Modem Transmitter

Sine Lookup

Cosine Lookup

Shaping Filter

Modulation

Modem Design OverviewModem Design Overview

Proceeding of the SDR 03 Technical Conference and Product Exposition. Copyright © 2003 SDR Forum. All Rights Reserved

Page 49: FPGA Co-Processors in SDR Signal Processing · Processor Post-Processor Control Data Data Input Processor Co-Processor Control ... Co-Processing on FPGAs Processor on FPGAProcessor

49© 2003 Altera

®

Modem Design Code ProfileModem Design Code ProfileTI Code Composer Studio Profiling Output

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Page 50: FPGA Co-Processors in SDR Signal Processing · Processor Post-Processor Control Data Data Input Processor Co-Processor Control ... Co-Processing on FPGAs Processor on FPGAProcessor

50© 2003 Altera

®

Main100%

Initialize3%

Add Noise Signal0.5%

Modem Transmitter

96.5%Sine Lookup

3.0%Cosine Lookup

3.5%

Shaping Filter82%

Modulation8%

Modem Design Code ProfileModem Design Code Profile

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Page 51: FPGA Co-Processors in SDR Signal Processing · Processor Post-Processor Control Data Data Input Processor Co-Processor Control ... Co-Processing on FPGAs Processor on FPGAProcessor

51© 2003 Altera

®

Main100%

Initialize3%

Add Noise Signal0.5%

Shaping Filter 82%

Modulation 8%

Sine Lookup 3.0%

Cosine Lookup 3.5%

HardwareAccelerator

Modem Design Hardware/ Software PetitionModem Design Hardware/ Software Petition

Modem Transmitter

96.5%

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Page 52: FPGA Co-Processors in SDR Signal Processing · Processor Post-Processor Control Data Data Input Processor Co-Processor Control ... Co-Processing on FPGAs Processor on FPGAProcessor

52© 2003 Altera

®

Modulator Co-ProcessorModulator Co-ProcessorDSP Builder Used to Build Hardware DSP Data Path

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Page 53: FPGA Co-Processors in SDR Signal Processing · Processor Post-Processor Control Data Data Input Processor Co-Processor Control ... Co-Processing on FPGAs Processor on FPGAProcessor

53© 2003 Altera

®

Avalon™ Interface in SOPC BuilderAvalon™ Interface in SOPC Builder

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Page 54: FPGA Co-Processors in SDR Signal Processing · Processor Post-Processor Control Data Data Input Processor Co-Processor Control ... Co-Processing on FPGAs Processor on FPGAProcessor

54© 2003 Altera

®

Import DSP Builder Generated Co-Processorinto SOPC Builder

DSP Builder— SOPC Builder ImportDSP Builder— SOPC Builder Import

Proceeding of the SDR 03 Technical Conference and Product Exposition. Copyright © 2003 SDR Forum. All Rights Reserved

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55© 2003 Altera

®

Modem Co-Processor (fir_comp) Integrated with TI EMIF I/F (TIMaster)

SOPC Builder IntegrationSOPC Builder Integration

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FIR Filter Co-Processor Design ExampleFIR Filter Co-Processor Design Example

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DSPMemoryMemory

FPGAFPGA

Digital Signal Processor + FPGA Co-Processor

Digital Signal Processor + FPGA Co-Processor

FIRFIR

Multi-ProcessingDSP

DSP DSPDSP DSPDSP DSPDSP DSP

Driving Down System CostsDriving Down System Costs

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FIR Co-Processor Design ExampleFIR Co-Processor Design Example

FIR Parameters− 128-Tap− 16-Bit Data, 14-Bit Coefficients

Four FIR Implementations for Comparison− TI C6711-Optimized TI DSPLib Function− TI C6416-Optimized TI DSPLib Function− Altera Eight-Cycle FIR Co-Processor− Altera One-Cycle FIR Co-Processor

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TI Filtering Library (DSPLib)TI Filtering Library (DSPLib)C-Callable Optimized Assembly RoutinesTI C67x DSPLib: FIR Filter (Radix 8)− Formula: Nh * Nr /2 + 13

Nh = Number of CoefficientsNr = Number of Samples

− ~1 Sample/ 64 Cycles (128 Tap Filter)TI C64x DSPLib: FIR Filter (Radix 8)− Formula: Nh * Nr/4 + 17− ~ 1 Sample/ 32 Cycles (128 Tap Filter)

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Filter Co-Processor Design ExampleFilter Co-Processor Design Example

Current Implementation− 100 MHz, 32-Bit, Asynchronous EMIF on DSK− TI Writes 300 Samples to Co-Processor (Input Data)− Filter & Send Output to TI

C6000 Digital Signal Processor

External M

emory I/F

FPGA Co-Processor

TI I/F Core

QD

MA

Input FIFO

FIR

Com

piler

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FIR Filter Example* – 16X Cost/Performance ImprovementFIR Filter Example* – 16X Cost/Performance Improvement

1-Cycle***at 170 MHz

7-Cycles***at 197 MHz

32-Cycles**at 600 MHz

64-Cycles**at 200 MHz

Solution

$84

$14

$160

$24.59

Device Cost****

170

28

18.75

3.125

FIR Performance(MHz)

Altera EP1C12-8

Altera EP1C3-8

TI C6416-600

TI C6713-200

Device

$0.50

$0.49

$8.53

$7.87

Cost perFIR MHz

* FIR 128 Tap, 16-Bit Data, 14-Bit Coefficients** DSPLib Optimized Assembly Libraries from Texas Instruments*** Optimized MegaCore FIR Compiler from Altera**** Pricing in Quantity of 100 at Arrow 6/25/03

* FIR 128 Tap, 16-Bit Data, 14-Bit Coefficients** DSPLib Optimized Assembly Libraries from Texas Instruments*** Optimized MegaCore FIR Compiler from Altera**** Pricing in Quantity of 100 at Arrow 6/25/03

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14X Reduction in System Costs14X Reduction in System Costs

DSPMemoryMemory

FPGAFPGA

FIRFIR

173

167

Total FIR Performance

(MHz)

$84 + $25

9 * $160

Device Costs

$110

$1,440

Total Cost

170 + 3

9 * 18.75

FIR Performance

(MHz)

Altera EP1C12-8 + 1 TI C6713-200

9 * TI C6416-600

Architecture

DSPDSPDSPDSPDSPDSPDSPDSPDSP

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SummarySummaryFPGA Co-Processors for DSP Offer Many Advantages− 10X Performance Boost

More ChannelsMore Complex AlgorithmsIncreased System Throughput

− 10X Cost Reduction Fewer Components

− Complementary to DSP-Based SystemsOffloads Existing DSPIntegrates Into Existing DSP IDEEvolution Not Revolution

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Altera Code: DSP SolutionsAltera Code: DSP SolutionsFPGAs− Stratix, Stratix GX, Cyclone

Development Tools− DSP Builder, SOPC Builder

Intellectual Property− FIR, FFT, Viterbi, Turbo, Reed Solomon, NCO− AMPP Third-Party Partners

Development Kits− Altera− Third-Parties

Design Services− ACAP Third-Party Partners

Training

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