computer-aided modeling and simulation of switching …
TRANSCRIPT
COMPUTER-AIDED MODELING AND SIMULATION OF SWITCHING
REGULATORS
by
SEONG JOONG KIM
THESIS submitted to the Faculty of the
Virginia Polytechnic Institute and State University
in partial fulfillment of the requirements for the degree of
MASTER OF SCIENCE
in
ELECTRICAL ENGINEERING
APPROVED:
F. C. Lee, Chairman
V. Vorperian
June, 1986
Blacksburg, Virginia
D. Y. Chen
B. H. Cho
COMPUTER-AIDED MODELING AND SIMULATION OF SWITCHING REGU-
LATORS
by
SEONG JOONG KIM
F. C. Lee, Chairman
ELECTRICAL ENGINEERING
(ABSTRACT)
Switching regulators are modeled as an unterminated two-
port circuit to provide flexibility in system model building.
Each functional block of switching regulators is modeled as
an independent module so that an arbitrary regulator can be
configured.
Unified models for large-signal and small-signal analysis
are developed in user friendly manner. Analysis capabilities
of switching regulator model are demonstrated using EASYS
software program.
ACKNOWLEDGEMENTS
I wish to express my gratitude to Dr. Fred C. Lee for pro-
viding the opportunity to investigate and research the topic
discussed in this thesis. The encouragement and suggestions
Dr. Lee has provided is greatly appreciated.
I wish to express my appreciation to my committee members,
Dr. D. Y. Chen and Dr. V. Vorperian for their support.
A special thanks to Dr. B. H. Cho for providing many use-
ful advices and guidance throughout the research.
With much love and gratitude, I thank my parents for their
support for my academic pursuits.
Acknowledgements iii
CONTENTS
CHAPTER 1. INTRODUCTION • • • • • • • • • • • • • • • • • • • • •
1. 1 Overview • • • • • • • •
1.2 Software System 'EASY5'
CHAPTER 2. POWER STAGE MODELING • • • • • • • • • • • · · • ·
2 .1 Power circuit description • • • • • • • • • • ·
2.2 EASY5 Large-Signal Model for Power Stage · · ·
2.3 EASY5 Small-Signal Model for Power Stage • • •
CHAPTER 3. ANALOG FEEDBACK CONTROLLER MODELING •
3. 1 Introduction • · • • • • • • · • • • • • • • • •
3.2 EASY5 Model for Analog Feedack Controller
3.2.1 Voltage-Feedack Compensator Model • • ·
3.2.2 Current-Feedack Loop Model• • • • • • · · • · • · ·
CHAPTER 4. DIGITAL SIGNAL PROCESSOR MODELING · • ·
PAGE 1
1
6
9
9
12
19
25
25
27
27
32
35
4. 1 Introduction • • • • • • • • • • • • • • • • • • • • 35
4. 2 EASY5 Model for Digital Signal Processor • • • · • • • • 37
4. 2 .1 Constant-Frequency Control • • • • • 38
4. 2. 2 Constant-OFF-Time Control • • • • • • • , • • • • • 43
4.2.3 Constant-ON-Time Control • • • • • • . • , • • • • • 46
CHAPTER 5. MODELING AND SIMULATION EXAMPLES , · · • 49
5.1 Large-Signal Similation Examples
5.2 Small-Signal Analysis Examples . . . . . . . . . . . . . 49
66
CHAPTER 6. CONCLUSION AND FUTURE WORK ••••• , ..•.•• 76
APPENDIX I. MACRO COMPONENTS LIBRARY . . 78
PROCEDURE OF EASY5 PROGRAMMING • 118 APPENDIX 11.
REFERENCES • • • • • • • • • • • • • • • • • • • • • • • • • • • • . 12 7
iv
Chapter 1
INTRODUCTION
1 . 1 Overview
The ever increasing demand on spacecraft power systems for
improved efficiency and reliability, smaller size and lighter
weight, coupled with continuous growth in dimension and com-
plexity of the spacecraft's payloads, has focused attention
on a major deficiency - the ability to design, test, and
trouble-shoot large-scale power systems. Switching regulator
which is primary power processing circuit of spacecraft power
system is one of the most difficult part to model.
During the past several decades, numerous efforts have
been m.ade to develop new and more powerful techniques for
modeling and analysis of switching regulator. However, when
the switching regulator and other subsystems are intercon-
nected to form a complex system, it is quite difficult to
predict the total system response even though the behavior
of individual switching regulator may be well underptood and
documented. This is due to many undesired interactions that
exist among highly nonlinear components. The need of a com-
prehensive power system modeling tool is, therefore, most
critical since the elaborate design verification through in-
tegrated systems hardware testing is prohibitively expensive
1
2
il POWER STAGE jL_
0 • vl v2 I
I I
d ¥ ;+,
PWM
dl;itat s1;na1 i:,rocessor
thresnold detector
Figure 1.1
current
feedback loop
voltage loop
compensator
Switching regulator model
i2
3
or often impossible. Therefore, a comprehensive computer
model that can actually predict a system's local and global
behaviors is most critical. One way to develop a model with
such attributes is to modularize each functional block as
independent module.
Switching regulators can be characterized, as shown in
Fig.1.1, by the three basic functional blocks: power stage,
analog feedback controller, and digital signal processor.
The power stage consists of energy storage elements and
switches. Transfer of the input power to the load is con-
trolled by the duty ratio of the switch (transistor). The
analog feedback controller usually contains an error ampli-
fier and a compensation network. For a single-loop control
it senses the output voltage, and for a multiple-loop control
it senses the output voltage and inductor current or switch
current. The digital signal processor includes a ramp gen-
era tor, a comparator, and latches. It takes the control
voltage from the analog feedback and converts it to the
pulse-width-modulated (PWM) signal which controls the
switches in the power stage_[l][Z]
Switching regulators are often used a part of the power
processing circuits with their source and load not prede-
fined. Thus, as shown in Fig.1.1, converter power stage is
modeled without specific source and load. This unterminated
4
model provides versatility for system simulation and analy-
sis.
Since there exist many different types of power stage
topologies and control methods, the behaviors of a regulator
depend largely on the type of power circuit topology and
control. Thus, for maximum flexibility, it is advantageous
to develop models for each functional block as independent
modules.[ 2 ] In this thesis, each functional block is modeled
seperately as an EASYS MACRO MODULE and stored in macro mod-
ule library. A regulator can then be configured by connect-
ing appropriate pre-defined modules for each functional
block.
In Chapter 2, various power circuit topologies are modeled
for both small-signal and large-signal with unterminated
two-po~t model. Some commonly used compensators and stand-
ardized control module ( SCM) and current-injected control
(CIC) schemes are modeled in Chapter 3. In Chapter 4, the
digital signal processor is modeled according to its control
law such as constant-frequency control, constant on-time
control, and constant off-time control. Time-domain simu-
lation and small-signal analysis examples for complete
switching regulator system are presented in Chapter 5.
Finally, Chapter 6 presents the conclusion and suggestion for
future work.
5
Generated EASYS Macro Components Library is presented in
Appendix I. It includes circuits, major equations, and pro-
gram lists for each macro component. In Appendix II, the
general procedures for EASYS modeling and analysis program-
ming are explained.
6
1.2 The Software System 'EASYS'
The program EASYS developed by Boeing Computer Service is
the general purpose large scale system modeling and analysis
program. The EASYS software[ 3 l provides a modular approach
to dynamic system model building and analysis. It was chosen
particularly for its effective means of assembling complex
component modules into a system. The EASYS program is capa-
ble of incorporating state equations, transfer functions and
empirical data for various modeling needs. Predefined com-
ponent modules can be stored in the EASYS component tibrary.
The component modules can have several input and output ports
and, in each port, information can flow into and out of the
port. All detailed connections of signal paths between com-
ponent blocks are programmed with minimal user intervention.
One~ all the necessary components are modeled, they are
stored in EASYS macro component library. The EASYS system
consists of two subprograms, and a library of predefined
Standard Components. Predefined Standard component models
include many of the common effects found in dynamic systems
such as standard analog and discrete controllers (propor-
tional, integral, differential, etc. ) transfer functions,
nonlinearities (relay, saturation, hysteresis and switches),
linear state equation model, etc. A block diagram of system
model generation and analysis with the EASYS is shown in
Fig.1.2.
7
USER DEFINED CRO COMPONEN 11-------
LI BRARY
MODEL DESCR I PT! ON DATA
ANALYSIS DATA
MODEL GENERATION PROGRAM
SYSTEM MODEL SUBROUTINE
ANALYSIS PROGRAM
Figure l .2 EASY5 system
STANDARD FUNCTION LIBRARY
INPUT-OUTPUT LISTINGS
ANALYSIS RESULTS
8
Model generation: The EASYS Model Generation Program uses
a block diagram type of approach for constructing various
system models. All interconnections between the component
models are accomplished by the Model Generation Program ac-
cording to the user specified Model Description Data. This
is accomplished by matching the input and output port quan-
tities of each interconnection, The program also produces a
complete list of input data that is required by each compo-
nent to complete the model description. The scalar and vec-
tor parameters and tabular data required for the analysis are
included in this list.
Analvsis: Once a system model has been constructed, the
Analysis Program performs various dynamics analyses according
to the user provided Analysis Data. The Analysis Data in-
eludes parameter values, initia~ conditions of states, vari-
ous analysis controls and analysis commands. A list of the
analysis techniques available through the Analysis program
are given as follows.
•
•
•
•
Time history generation - nonlinear simulation
Linear model generation
Frequency response analysis
Root locus calculation
Chapter 2
POWER STAGE MODELING
2. 1 Power Circuit Operation
The de-de voltage conversion is achieved by repetitive
switching between a number of linear networks. The number
of linear networks in one switching cycle is determined by
the mode of operation of the energy-storage inductor current.
If the inductor current is continuous as shown in Fig.2.l(a),
the power stage model has two linear networks corresponding
to the continuous-conduction mode (CCM). For a
discontinuous-conduction mode (DCM) operation as shown in
Fig.2.l(b), the power stage model is ~omposed of three linear
networks. Each linear circuit model is described by a set of
linear. state equations. Thus, to make a converter in both
modes of operations, following three sets of state equations
should be used during a switching cycle.
( 2. 1)
x = A2 x + B2u
y = c2x + E2u, for interval-TFl (2.2)
9
INDUCTOR CURRENT
INDUCTOR CURRENT
10
TON -111.-.t--- TFl POWER SWITCH ON, POWER SWITCH OFF,
DIODE OFF DIODE ON
(a) continuous-conduction mode
TON~~..- TFl ~TF2
POWER POWER SWITCH OFF, SWITCH ON, I DIODE OFF DIODE ON DIODE OFF
(b) discontinuous-conduction mode
Figure 2.1 Inductor Current Waveforms
t
t
11
(2.3)
Here xis the state vector, u the input vector and T the . s switching period. Ai and Bi (i=l,2,3) are square matrices
which describe the three circuit topologies and the effects
of the input vector, u.
12
2. 2 EASY5 large signal model for converter power stages
As described in Chapter 1, converter power stage is mod-
eled as an unterminated two-port network. Hybrid g-parameters
are selected as a interconnection law because it provides
information flow in both direction_[ 4 l The terminal charac-
teristics are described by the matrix equation in Eq.(2.4).
r 1 I vl I I I I i 2 I L J
( 2. 4)
Input vectors are u = [v 1 i 2 ], where v 1 is the input voltage
and i 2 is the load current, and outpu~ vectors are y = [i 1
v 2 ], where v 2 is the output voltage and i 1 is the source
current.
When the unterminated power stage model is connected with
source and load modules, interconnection mechanism is shown
in Fig.2.2. The converter module sends output voltage, v 2 ,
to the load module and source current, i 1 , to the source
module. It also receives input voltage, v 1 , from the source
module and load current, i 2 , from the load module.
13
i2 il i2 il --+ --+ - .. - -+ + +- +
SOURCE v2 vl CONVERTER v~ vl LOAD L.
- - - -- -- -
Figure 2.2 Interconnection of modules
14
As described in the previous section, power stage, in gen-
eral, has three sets of equations. These three se.ts of ma-
trices coefficients are stored in the power stage module and
appropriate sets of matrices are selected according to the
status of d(t) which is determined by the digital signal
processor module. As illustrated in Fig.2.3, when d(t) is
equal to one, (interval T0N), the first matrix set, A1 , B1 ,
c 1 ,and D1 , is used to calculate state equations, the second
matrix set is used when d(t) is zero (interval TF1 ). For the
DCM the third matrix set is used when both inductor current
and d(t) are equal to zero (interval TF2 ).
The state variables are x = [ iL v C] where iL is the
energy-storage inductor current and vc is the output-filter
capacitor voltage. For the buck/boost (flyback) converter,
x = [ ¢ vc] where ¢ is the flux in the two-winding energy-
storage inductor.
Al 1 switches (transistors and diodes) are regarded as
ideal switches, and the winding resistance (R 1 ) of the
inductor and ESR (R) of the capacitor are included in the C
power stage mod~l.
As an example, The buck converter power stage modeling is
described as follows.
15
• X = A. X + B. u 1 l.
y = C. x + E. u 1 l.
Figure 2.3 Power stage model
16
For the buck power stage denoted as [BC], the three, lin-
ear equivalent-circuit models can be generated according to
the time intervals TON' TFl' and TF2 ' which are illustrated
in Figs.2.4. The power stage is then described by the
piecewise linear equations for each subinterval as following:
For
u =
during the interval TON'
Rl+Rc - 1 1 R C
A = L L B = L L 1 1 1 - 1 0 0
C C
[ R 1
] [ 0 - R
] (2.5)
C = C E = C 1 1
1 0 0 0
for the interval TFl'
Rl+Rc - 1 0 R C
A = L L B = L 2 1 2 - 1 0 0
C C
[ R 1 ] I 0 - R ]
(2.6) C = C E = C
2 2 0 0 0 0
0 +
17
R iL i2 --+
Ri 0 +
vl v2 C V C
Figure 2.4 (a) Buck converter power stage
Ri ~iL -i2 o-:-1--.J'"1i;11.;.,~,i,-..--J-""'ITl""'-V~-v,r,, _R_c_l __ ----,j::
o----------c_J_._ __ o interval TON
+
C
interval TFl interval TF2
Figure 2.4(b) Three switched equivalent circuits
for the interval TFZ'
0
0
0
0
0
0
1
0
I ]
18
B = 3
E 3
I 0 0 I - 1 0 C
[ 0 - R ] (2.7)
C
0 0
For the following converter topologies, EASYS macro mod-
ules are also generated. Detailed macro-model descriptions
are giyen in the Appendix I.
• [BT] ----- boost-converter power stage
• [FB] ----- buckjboost (flyback) converter power stage
• [FW] ----- forward-converter power stage
19
2.3 EASY5 small-signal model for converter power stages
The state-space averaging technique [ 5 ] is used to derive
a linear model for the power stage. The small-signal model-
ing in this study is carried out for the case of the
continuous-conduction mode.
• Averaging
The principle· of the average model is to replace the
state-space description. of the two linear equations by a
single state-space description which represents the small-
signal behavior of the system for a given operating condi-
tion .. Taking the average of Eqs. ( 2. 1) and ( 2. 2) for both
intervals results the following linear time-varying contin-
uous system:
• x = d (A1x + B1u) + d'(A 2x + B2u) (2.8)
y = d (C1x + E1u) + d'(C 2x + E2u)
d = TON/Ts, d'= TFl/Ts = 1-d
where Ts is the period of the switching cycle.
Equation (2.8) can be rewritten in the following form:
20
• x =Ax+ Bu
y =ex+ Eu (2.9)
where A= dA + d'A 1 2 C = dC + d'C 1 2 B = dB + d'B 1 2 E = d~l + d'E 2
• perturbation
To study the small-signal behavior, the linear time-varying
Eqs.(2.9) are perturbed.
d=D+d, d'=D-d
x=X+x, u=U+u, y=Y+y
Substituting these into the averaged equation (2.9),
it becomes
• ... X =
(2.10)
21
where
The perturbed state-space description is nonlinear owing
to the presence of the product of the two time dependent
quantities x and d.
• Linearization
Using small-signal assumptions, the nonlinear second order
terms in Eq. (2.10) can be neglected, and the following linear
time invariant system is obtained:
• A A A x =Ax+ Bu+ Pd
A A A ;,.
y = ex + Eu + Qd ( 2. 11)
where p = (Al - A2 )X + (Bl - B )U 2
Q = (Cl - c2 )X + (El - E )U 2
By selecting the de terms from Eq. (2 .10), the steady-state
solutions are
(2.12)
22
The small-signal solutions can be obtained by taking the
Laplace transform of Eq.(2.11).
,. A A
X = H u + Hdx d ux
A A ,..
y = H u + Hdy d (2.13) uy where
" X A)-1 H - = (sI - B ux ... ,,.
u d=O
" X A)-1 Hdx - = (sI - p
I\ ,\ d u=O
,. y
H - = C Hux + E (2.14) uy ... ,. u d=O I\
y Hdy - = C Hdx + Q
I\
u=O d
Equation (2.14) describes the power stage of switching con-
verters with unterminated inputs and outputs.
Since EASYS can generate transfer function from state
equations, EASYS small-signal models are modeled using
Eqs.(2.11) and (2.12).
As an example, the buck converter power stage small-signal
modeling is described as follows.
23
For the buck converter power stage denoted as [UK], the
linearized small-signal state equations become:
The
• ,. X =
,. ... ,.. Ax+ Bu+ Pd
where P = (A1
Q = (Cl
A2 ) X + ( B 1
c2 )X + (E 1
averaged coefficient matrices
Rl+Rc - 1 A = L L
1 0 C
C [ R 1
1 = C
D 0
are D
B = L
0
E [ 0 = 0
Using Eq.(2.12) the steady-state solution is
R _£_ L
- 1 C
- R ] C
0
24
The control coefficient matrices using Eq.(2.11) becomes
p = [ 0 ]
Q = [ 0 ]
From these small-signal model, frequency responses of any /
converter open-loop transfer functions, Eq. ( 2. 14), can · be
achieved using EASYS transfer function analysis.
For the following converter topologies, EASYS macro
small-signal modules are also generated. Detailed macro
module descriptions are given in the Appendix I.
• [ST] ----- boost-converter power stage
• [BB] ----- buck/boost (flyback) converter power stage
• [WD] ----- forward-converter power stage
Chapter 3
ANALOG FEEDBACK CONTROLLER MODELING
3. 1 Introduction
The analog feedback controller is a feedback compensation
network. It processes input signals sensed from the power
stage, and delivers the control voltage to the pulse
modulator.
For a single-loop control, output voltage of the power stage
is compared ·with reference voltage, and the error voltage is
amplified and compensated through the compensation network.
Since the compensation network is linear for normal mode of
operation, it can be modeled by either transfer functions or
state ~quations.
The transfer function model provides more design insight be-
cause loca:tions of the poles and zeros are directly imple-
mented.
For the multiple-loop controller, both the inductor current
(or switch current) and output voltage are sensed. The cur-
rent information have two functions. The first function is
to transform the current into a voltage signal and the volt-
age signal is used for determining the switching logic. The
second function is to derive the error signal for additional
25
26
loop compensation. How the current information provides
those functions are discussed in later sections for Stand-
ardized Control Module ( SCM) and Current-Injected Control
(CIC).
27
3.2 EASY5 Model For Analog Feedback Controller
The EASYS model for the analog feedback controller is
characterized generally by the voltage-feedback module and
current-feedback module. When a single-loop feedback control
is used, the current feedback module is omitted.
3.2. 1 Voltage-feedback compensator
Since transfer function model can be used for both the
large-signal and small-signal model, the following two com-
monly used compensators are modeled with transfer functions.
• [MP] --- two-pole one-zero compensation
. V = E
s(l + s/w ) p
v 0 : switching regulator output voltage
K: voltage dividing factor
eR reference voltage of op.amp.
VE compensator output voltage
w gain m w frequency of zero z w frequency p of pole
( 3. 1)
28
One possible circuit implementation of the above transfer
function is shown Fig.3.l(a) and its gain characteristic is
shown in Fig.3.l(b). The transfer function of the
compensator circuit shown in Fig.3.l(a) is
F(s) = (3.2)
By comparing Eqs. ( 3. 1) and ( 3. 2) one can determine the
circuit parameter values for resistors and capacitors in
Eq. ( 3. 2) from its design parameter values, w , w , and w or m z p
vice versa. For EASYS modeling, the transfer function in
Eq. (3.1) is converted to following state equations.
ERR = Kv ER 0 •
X = ERR (x + ERR/w )w z p
VE = w (x + ERR/w )w m z p where X is intermediate variable.
V
29
C
(a) circuit implementation
I I I I I I I I
1 1
(b) gain characteristic
Figure 3.1 Two-pole one-zero compensator
• [PZ]
30
Two-pole two-zero compensation
s(l + s/w ) p ( 3. 3)
Figure 3. 2 shows one possible circuit implementation of
the two-pole two-zero compensator and its gain character-
istic. The transfer function of the circuit is
F(s) = ( 3. 4)
The transfer function in Eq.(3.3) are converted into fol-
lowing state equations.
z = wmwp/(wzl""z2>
ERR = kv ER 0
VE = y + z ERR
• X = ERRw w mp • y = X + z(wz 1+wz2 )ERR - wpvE
where x, y, z are intermediate variables.
31
R3 c2 R2
II V
0
VE Rl
--(a) circuit implementation
J I I I I 1
C2(Rl+R2) R3Cl R2C2
(b) gain characteristic
Figure 3.2 Two-pole two-zero compensator
32
3.2.2 Current-feedback module
Two current feedback schemes are modeled; one is referred
to as standardized control module (SCM), the other is
current-injected control (CIC).
• [SM] --- Standardized control module(S.C.M)[ 5 l
In SCM, as shown in Fig.3.3(a), voltage vL across the
energy-storage inductor is sensed through a transformer and
is integrated, so that the integrated voltage (vI) has the
same shape as the ac component of the inductor current. That
is, the transfer function from the inductor current to the
output voltage of the current-feedback loop (vI) is a simple
gain. These relations are shown in the following:
vac = n L diL/dt
Taking the Laplace transform of Eq.(3.5)
Since
v (s) = n Ls iL(s) ac
from Eqs.(3.6) and (3.7)
(3.5)
(3.6)
(3.7)
(3.8)
33
.-iL- - - _N ___ - -- - - --,
-- : J L v ac l I ----- I 1 C R4 l I 1 I I ----- f,-- I 1 I
I I I I Ve I
--
I I I I I I
L.. .... - - - - - ......... - - - ..... - - - __ I
( a) SCM
cc , .... - --------------7 I ul 1 I l I I l I I l I I I 1 z I I I l J ~1 - VI + I V I R I w I I ·- - ---- - --- _J
(b) CIC --Figure 3.3 Current-feedback module
V 0
--
34
As illustrated in Fig.3.3(a), the op-amp and capacitor Cl are
common to both the current loop and the voltage loop. Thus, )
the control voltage (vc) represents the total error voltage
derived from both the current loop and the voltage loop.
• [CC] --- Current-injected control module(C.I.C)[ 7 l
In CIC, as shown in Fig.3.3(b), the switch current is
sensed through a current trans£ ormer. The voltage drop
across the current-sensing resistor (R) is proportional to w the switch current as described in following equations.
i. = i /n 1 S
= i. R l. w
n
(3.9)
Thus, the control voltage after summing the output voltages
of both the current-loop and the voltage-loop becomes
= - V - V E I (3.10)
Chapter 4
DIGITAL SIGNAL PROCESSOR MODELING
4.1 Introduction
The digital signal processor (DSP) converts the control sig-
nal ve from the analog feedback controller into discrete-time
pulses to control the ON-OFF of the power switch. The DSP
includes the threshold detector (comparator), the ramp func-
tion and the latch circuit.
The threshold detector compares the control signal, ve,
and the reference signal (either de or a ramp) to generate
the trigger signal for the switch command. For the multiple
loop control, the control signal, ve, is the sum of the out-
puts f~om all feedback loops. In this case, the ve waveform
already includes a ramp function (proportional to the
inductor current or the switch current). The external ramp
function is optional, it is needed to stabilize the system
operating at a constant frequency and a duty ratio greater
than fifty percent. Figure 4.1 illustrates the PWM model for
a constant-frequency control. For each different duty-
ratio-control law, such as constant frequency, constant TON
and const~nt TOFF' the PWM model is different. These dif-
f erent ,JR'odules are stored in the component module library,
as in the case of power stage models.
35
PROTECTION
dU:l CSP
·o· LIMIT
36
COMPARATOR
-.
Figure 4.1 Pulse-width-modulator (PWM)
37
4.2 EASY5 Model For Digital Signal Processor
The digital signal processor is modeled according to its
control law such as constant-frequency control--[WM], con-
stant on-time control-- [NN], and constant off-time
control--[FF].
The protection functions are also included in the model,
such as the peak-current limiter for power components and the
converter shut-down in the event of sensed abnormalities such
as over-voltage, under-voltage, or over-current beyond a
predetermined level. Nonlinearities, such as op-amp satu-
ration and duty-cycle limiter, are also included in this
module.
For the small-signal model, the transfer function from the
control signal, vc, to the duty cycle modulation, d, becomes
the simple gain , FM, which is determined according to its
control law[ 6 ].
d = FM Ve
38
4.2. 1 Constant-frequency control [WM]
For a single-loop control model, as shown Fig.4.2(a), an ex-
ternal ramp is used to implement the duty-cycle signal. The
frequency of the external ramp function is identical to the
switching frequency. For two-loop control, as shown in
Figs.4.2(b) and (c), the inductor-current or switch-current
information determines the point at which the control voltage
(vc) intersects the reference voltage (vR). The reference
voltage (vR) is a fixed threshold voltage (vTH) when an ex-
ternal ramp is not used. If an external ramp is used to
overcome the instability problem, which occurred when the
duty ratio exceeds fifty percent[ 6 l, the. reference voltage
becomes the sum of the threshold voltage and ramp voltage.
The FORTRAN implementation of this module is shown in the
flow diagram, Fig.4.3. It consists of four basic elements:
the ramp-function generator, selection of the control method,
comparator and protection. To generate the ramp function, a
normalized time (TN) is defined by using the EASYS internal
variable TIME.
where T is the switching period. s By subtracting integer N
which is generated by the library function IDINT(TN) from TN,
the normalized ramp function(TN - N) is produced.
39
r Ts---Jj
d ( t)
I I l I TON TOFF
(a) single-loop control
·-..... --
(b) SCM
(c) CIC
Figure 4.2 Constant-frequency control
40
TN = (TIHE + T )/T s s N NP N = IDINT( TN)
VR = vp(TN - N)
two loo
single loop
no VR = VR + V th V = VE ,:.
yes
VR = vth VR = VR + vth V = VE - V V = VE -VI C C
no
no
SW= OFF no
no
SW= OFF
- SW = OFF
es
RETURN SW= ON
E'Iqure 4. 3 Flow-chart for constant-frequency control
41
Then the ramp function (V ) is generated by multiplying ramp the desired amplitude. These waveforms are shown in Fig.4.4.
Since this module can handle the single-loop control and
multi-loop control (with or without external ramp function),
one of these options is selected and the appropriate refer-
ence voltage(vR) and control voltage(vc) are assigned. The
reference voltage and the control voltage are compared to
determine the status of the switch according to the switching
logic illustrated in Fig.4.2. Whenever one switching period
ends, the switch is reset to the ON position and the process
is repeated for the next cycle. Duty-cycle limiter and
overcurrent-protection logic are included in this module.
If any aforementioned abnormalities are sensed, the shut-down
command will turn off the switch. The switch status (ON or
OFF) determined in these processes, d(t), is transferred to .
the power stage to execute the corresponding state equations.
T 3 N
2
3 N
2
T s
la-------
T -N N 1
T s
T s
T s
Figure 4. 4
42
2T s
2T s
2T s
2T s
3T s
3T s
3T s
3T s
Ramp function generation
43
4.2.2 Constant-OFF-time control [FF]
In the constant-OFF-time control, regulation is achieved by
controlling ON-time interval T0N. When the two-loop control
is implemented, as shown in Fig.4.S(b), the intersection of
the descending control voltage (vc) with the threshold level
determines the end of the ON-time interval. For the single-
loop control, however, additional elements are required be-
cause the control voltage has only the output voltage
information. One possible implementation is illustrated in
Fig.4.S(a). An external ramp function is initiated at the
end of the constant-off-time interval. The intersection of
the control voltage with the ramp function determines the end
of the ON-time interval.
In the EASYS model, as shown in Fig. 4. 6, the control
voltag~, vc, and the reference voltage, vR, are determined
according to the choice of the control technique, single-loop
or two-loop control. If the switch is ON, those two volt-
ages, vc and vR, are compared to determine the instant of
turn off (Tc). Once the switch is tur~ed OFF, it will remain
for a pre-determined OFF-tirqe interval (TOFF). At the end
of the TOFF' the switch is turned ON and the on-time instant
(TR) is reset.
d(t)
d(t)
variable ON time
constant OFF time
variable TOFF ON time constant
I I variable ON time
OFF time
't
constant
44
(a) single loop control
(b) SCM
OFF time ( c) CIC
Figure 4.5 Constant OFF-time control
I
[
[
T = R SW=
45
FF --- CONSTANT OFF TIME CONTROL
two loop
slope = 0
V = V - VI C E
no
yes
TIME ON
yes
V = C
SW= OFF
RETURN
- VE
T = OFF time C
T = R ON time
yes
no SW OFF
T = TIME C
Figure 4. 6 Flow-chart for constant OFF-time control
instant
instant
46
4.3 Constant-ON-time control [NN]
In constant-ON-time control, the output regulation is
achieved by controlling the OFF-time interval. For two-loop
control, as shown Fig. 4. 7 (b), the intersection of the as-
cending control voltage with the threshold level marks the
end of OFF-time interval TOFF' For single-loop control, as
shown in Fig. 4. 7 (a), the intersection between the control
voltage and descending ramp signal decides the turn-on in-
stance. Figure 4.8 shows the flow chart of constant ON-time
control module. In this module, control logic is basically
the reverse of the constant-OFF-time control. Comparison
between vc and vR occurs during OFF-time interval, and after
a predetermined ON-time interval, the switch is turned off
and the OFF-time instant (TR) is reset.
d (t)
47
TON variable TON OFF time constant
ON time
(a) single loop control
----- - - - - ·--
[
-- -- .. -
TON variable TON OFF time constant
ON time (b) SCM
Figure 4.7 Constant ON-time control
48
NN --- CONSTANT ON TIME CONTROL
SINGLE LOOP
SLOPE = 0 Ve= - VE- VI
no yes
yes no SW= ON T = TIME R
SW= OFF T = TIME C
yes
no SW= OFF
RETURN
Figure 4.8 Flow-chart for constant ON-time control
Chapter 5
MODELING AND SIMULATION EXAMPLES
5. 1 Large-Signal Simulation Examples
Since a switching regulator is modeled as an unterminated
component to give the maximum flexibility to configure a
system, it is necessary to connect a load for the simulation.
A simple LCR load model [LO] is developed, as shown in
Fig.5.1.
The state equations are
• iL = (vl - V ) / L C
• VC = (iL - vc/R) I C
iL --+
+ L
+ vl R
VC C
Figure 5. 1 LCR load
49
50
As described in Chapter 1, a complete converter circuit
can be configured by arbitrarily choosing a power stage, a
analog feedback controller and a digital signal processor.
To demonstrate the versatility of this modeling scheme, the
following two examples are given:
• Example 1 : Buck regulator employing SCM feedback and a
constant-OFF-time duty-cycle control
Following modules are selected to model a switching regulator
system as shown in Fig.5.2.
[BC] --- buck power stage (large-signal)
[MP] --- compensator (two-pole one-zero)
[SM] --- SCM (current loop)
[FF] --- PWM (constant-OFF-time control)
[LO] --- load
The EASYS Model Description Data [BUCKCF.MOD] is shown in
Fig.5.3(a). It includes the calling of each module from the
Macro-Module Library and the interconnections between the
component modules. This is accomplished by matching the
port quantities between the input port and the output port.
-. D S P
Figure 5. 2
-=-v .I_ TH
R p
51
R C
IC I I I
I. - - -
Buck regulator employing SCM
Load
I
--, I
R
I
- - - _.J
2
52
****•***~********•·~····~•**•**•~********. *** BUCK LARGE SIGNAL<MODULAR APPROACH> ****~************************************ ** REVISED 2/4/86 MACRO FILE NAME=MACROS •LIST MACRO COMPONENTS=BC,LO,FF,SM,MP MODEL DESCRIPTION LOCATION=12,BC, INPUTS=LO<IL=I2>,FF(G=IG) LOCATION=17,LO, INPUTS=BC(V2=V1> LOCATION=34,SM, INPUTS=BC(VL=VL> LOCATION=36,MP, lNPUTS=BC(V2=VO> LOCATION=43,FF, INPUTS=SM<VI=VI>,MP(VE=VE),BC<IL=IL> END OF MODEL PRINT
Figure 5.3 (a) User input model description data
[BUCKCF.MOD]
3 4 5 6 7
********** ********** * * V2 BC ,,v1 * * * BC * * LO * * 12 •<=-=-=========================,•====================,•===:::-+ 17 * * *======>============>=========================) * * ********** IL LOI =12 I l **********
A I I l l Q FF =I I I I I I I I I I l I
21 123 124 25 126 27 I I l l I lVL BC =VL l V2 BC =VO I l l V V 1 l ********** ********** l I * * * * I I * SM * * MP * 3 I I 33 * 34 * 35 * 36 * 37 I I * * * * IL BC =IL I ********** ********** I V I I I ********** VI SM =VI I I * * VE MPI =VE l <=======* FF +•.===============· =================
42 * 43 * 44 45 46 47 * * **********
52 54 55
Figure 5.3 (b) EASYS generated model configuration [BUCKCF.MGL]
56 57
LO
FF
COMPONENT
BC
LD
PARAM~lLR NAME (AND DIMENSION DATA FOR VECTOR AND MATRIX PARAMEfFRS)
Er< FF \.,F!: il"f-
11 ... LD
f.<C nc L rn; r:n 1.u
C l!C
l.O
·1·nr-f--F
( lNITif.'·,L CUNDJ"! IDl'•l'.3 {-\!'-Hi Frrnon CONTFHJLS HEGUJi={l'::T))
iJ\:· Ml-•
Figure 5. 4 Input data requirement list [BUCKCF.MGL}
\JI w
54
According to the user supplied Model Description Data, the
EASYS Model-Generation Program generates the regulator cir-
cuit configuration (Fig.5.3(b)) and input data requirement
list (Fig.5.4). Figure 5.5 shows the user's input Analysis
Program that includes the parameter values, initial condi-
tions of state variables, and various types of analysis com-
mands.
Figures 5.6(a)-(c) show the steady-state regulator re-
sponses such as the regulator output voltage, the inductor
current, and the control voltage vs. threshold voltage.
Transient responses when load resistance is increased ten
percent at lms are shown in Figs.5.7(a)-(h).
55
TITLE=BUCK,SCM CONST OFF TIME(LARGE SIGNAL) *REVISED 1/24/86 **BC (POWER STAGE> INITIAL CONDITIONS IL BC=lO,VC BC=20 PARAMETER VALUES L BC=250E-6,C BC=400E-6 RL BC=lE-2,RC BC~1E-2 Vl BC=28 **VCG LOOP COMPENSATER K MP=.3,ER MP=6 GA MP=4488,WA Mr~628,WB MP=1E5 ** CURRENT L.OOP<SCM> NV SM=.08,C SM=7.275E-9,R SM=3.44E3 ** PWM TI FF=20E-6,VP FF=O,VTHFF=. 5 ER FF=6,CICFF=O,SCMFF=1 TOFFF=10E-6,EPSFF=1E-5 ILMFF=15 ** LOAD RA L0=2,RB L0=2.2,TC LO=lOOE-3 L LO=lE-6,C LO=lE--6 INITIAL CONOilIONS VE MP=O IL LO=lO,VC L0=20 PRINTER PLOTS ONLINE PLOTS INT MODE=4 DISPLAY! V2 BC DISPLAY2 IL BC DISPLAY4(0VERPLOT> VR FF,VC FF TMAX=10E-3,TINC=5E-7 PRATE=200,0UTR~TC~20 *PRATE=100,0UTRATE=4 SIMULATE XIC-X PARAMETER VALUES RB L0=2. 2 TC L0=222E-3 DISPLAYl V2 BC DISPLAY2 IL BC DISPLAY4(0VERPLOT} VR FF,VC FF TMAX=100E-6,TINC=2E-7 PRATE=10,0UTRATE=5 SIMULATE XIC-X PARAMETER VALUES TC L0=1E-3 DISPLAY! V2 BC DISPLAY2 IL BC DISPLAY3 VL BC,VM SM DISPLAY4(0VERPLOT> VR FF,VC FF TMAX=6E-3,TINC~2E-7 PRATE=200,0UTRATL~10 SIMULATE
Figure 5. 5 User input analysis program
[BUCKCF.ANC]
56
-0
u (a) (D
0) N ->
ffl 0)
I -0.00 0.32 0.64 0.96 1.28 1.60
8 --8 0 -
( b) u
8 (D
J Cl) -8 coo.oo 0,32 0,64 0.96 1.28 1.60
SJ
8 -(c)
LL LL u 0 >
i 0 0.00 0.32 0.64 0.96 1.28 1.60
TIME $
Figure 5.6. Buck converter steady-state response (SCM, constant OFF-time control)
(a) output voltage v 2 (b) inductor current iL (c) comparator input voltages vc & vR
57
Ea------------....-------.----, N
i-1------+---+----+----t-----; N
00 J --1-----+-+----+-----+-----1r----1
N
i...,_ ________ ____,~---+------+------1 -0.00 1.20 2.«J 3.60 4.80 6.00
Uo m --+----+-1-----+---=-...oc---,f-----+------1 Nfia >
i a, ..... ---+-----+----+----t------1 -0.00 1.20 2.«J 3.60 4,80 6.00
~------.---------.---~----, • -~-+-----+------l---+-----+-----1 --
.. ~8-1----~f----·~··_··" __ ~_ .. _·_--1---"~ J CD -
~-+----+----+----+----r------, 1.20 2,«J 3.60 4.80 6.00
TIME $
(a)
(b)
(c)
Figure. 5.7 Buck converter step-load response (SCM, constant OFF-time control)
(a) load resistance R (b) output voltage v 2 (c) inductor current iL
58
• Example 2: Buckjboost (Flyback) regulator employing CIC
and a constant-frequency control
Following modules are selected to model the circuit shown in
Fig.5.8.
[FB] --- buck/boost power stage (large signal)
[MP] --- compensator (two-pole one zero)
[CC] --- CIC (current-feedback loop)
[WM] --- PWM (constant-frequency control)
[LO] --- load
The EASYS Model description data and the EASYS generated
system configuration are shown in Fig.S.9(a) and (b), re-
spectively.
Fig.5.10.
list.
The input data requirement list is shown in
Figure 5.11 is the user input Analysis Program
Figures 5.12(a)-(c) show the simulation results at steady
state. Transient responses when load resistance is decreased
ten percent at lms are shown in Figs.5.13(a)-(b)
59
Load
I L ____________ J
d
J_
'-------1 D S P
..I. /Vv1
Figure 5. 8 Flyback converter employing CIC
60
*************************************** ** FLVBACK LARGE SIGNAL(MODULAR APPROACH) ******************~~******************* ** REVISED 12/8/85 MACRO FILE NAME=MACROS *LIST MACRO COMPONENTS=FB,LO,CC,SM,MP,WM MODEL DESCRIPTION . LOCATION=12,FB, INPUTS=LO<IL=I2),WM(IG=GG> LOCATION=17,LO, INPUTS=FBCV2=V1) LOCATION=34,CC, INPUTS=FB(PHI=IL> LOCATION=36,MP, INPUTS=FB(V2=VO) LOCATION=43,WM, INPUTs~cccvI=VI),MP(VE=VE) END OF MODEL PRINT
Figure 5.9 (a) [FLYBCK.MOD]
1
11
21
31
41
51
2 3 4 5 6 7
********** ********** * * V2 FB ::Vt * * * FB * * LO * * 12 *<============================: =====================: ====>* 1 7 * * *=====::;:=============::>========== =======-=-====-====) * * ********** IL LO =12 I I ********** A I I I IQ WM =GG I I I I I I I I
21 23 124 25 126 27 I I I I PHIFB =IL I V2 FB =VO I I V V I ********** ********** I * * * * I * CC * * MP *
31 33 * 34 * 35 * 36 * 37 I * * * * I ********** ********** I I I I ********** VI CC =VI I I * * VE MPI =VE I <=======* WM *<================================
42 * 43 * 44 4 5 46 4 7 * * **********
53 54 55 56 57
Figure 5.9 (b) [FLYBCK,MGL]
0\ ......
cc
l .. Ci
, l J t,H'•! '·/Ci'!UM
IL !.U
nr: r::u l'..!f·i r,t
·re L D
\. 1i' \.,!M U(H'-H-.lt·l
!<B L 0
\_) {~l \,cj t:! DH>'.VJM
Figure 5.10 [FLYBCK.MGL]
L Ct
ANO MATRIX STATES>
' \ I\.)
63
TITLE=FI.YDACI-<., CIC<LARGE SIGNAL> *REVISED 12/8/85 **FB (POWER STAGE) INITIAL CONDITIONS PHIFB=. BE-4,VC FD~5. 2 PARAMETER VALUES RS FB=. 013,RC FB=.007,LS FB=82.6E-6 NS FB=10,C FB=330E-6,RP FB=. 02 LP FB=400E-6,NP FB=22,Vl FB=23 **VTG LOOP COMPENSATER K MP=l,ER MP~5.2 GA MP=952. 4, ~-JA ,·i,--='848. 8, ~-m MP=-'?3290 ** CURRENT LOOP(SCM) *NV SM=.08,C SM=7. 275E-9,R SM=3.44E3 ** CURRENT LOOP(CIC> RW CC=53.6,NI CC=100 NP CC=22,LP CC=400E-6 ** PWM TI WM=20E-6,VP WM=O,VG WM=5. 2 ER WM=5. 2,CICWM=l,SCMWM=O ** LOAD RA L0=1. 69,RB LO=l. 5,TC L0=100E-3 L LO=lE-6,C LQ=lE-6 INITIAL CONDITIONS VE MP=-2. !:>4 IL L0=3. 077,VC L0=5.2 PRINTER PLOTS ONLINE PLOTS INT MODE=4 DISPLAY! V2 FB,PHIFB DISPLAY2 IP FB, IS FB DISPLAY3 PHIFB DISPLAY4(0VERPLOT> VR WM,VT WM TMAX=5E-3,TINC=5E-7 PRATE=500,0UTRATE=10 *PRATE=100,0UTRATE=4 SIMULATE XIC-X PARAMETER VALUES TC L0=222E-3 DISPLAY! V2 FB DISPLAY2 IP FB, IS FB DISPLAY4(0VERPLOT) VR WM,VT WM TMAX=80E-6,TINC=2E-7 PRATE=50,0UTRATE=2 *SIMULATE XIC-X PARAMETER VALUES TC L0=1E·-3 DISPLAY! V2 FB DISPLAY2 DISPLAY3 PHIFB DISPLAY4(0VERPLOT) VR WM,VT WM TMAX=5E-3,TINC=2E-7 PRATE=200,0UTRATE=5 SIMULATE
Figure 5.11 [FLYBCK.ANC]
G4
i-.-------,-----.--------,----------, U)
~--f------;+-+--------+--i'!--------+--+--1----+-~~------I U)
.... 0 :::> -0 ID >
8 '°o.oo 0,24 0.48 0,72 0.96 1.20
ti .. 8-4--f-+---l-f--+-~~--l--+-li------,1-4-~------J'-\----I ..
X fil 3 ro--+------w-+----v----i-~'----1---\-.,__--l-'w.------+1
LL
0,72 0.96 1.20
~------------------a,
~-+--+-----+--,1-+---+--++--4---4---1--+--4--~+--+-----' U)
i-1---.--,,'-4-1-1--__...._ __ -,;<-1---'----l---.l"-1-----I--------J~---l---.c....l .,_ ID
>
8-+----+---1-----+------1---~ 1Do.oo 0.24 0.48
TIME 0.72 0,96 1.20
Figure 5.12 Flyback converter steady-state response (CIC, constant frequency control)
(a) output voltage v 2 (b) inductor current iL (c) comparator input voltages vc & vR
65
~-r----r---~----.------,.----1-;----t-----t-----+----+--~
,; .;----+-----i----+----+---~ -i -,-----t----t------+----1-------1
l .00 2.00 3.00 4.00 5.00
&l U)
,.. "Ill ' .. , . n ... ,.-r '" .. . ,. .. .... I- 8 :::::> 0 U)
"fl'•"
>
fi I
""o.oo 1.00 2.00 3.00 4.00 5.00
~-,-----,------r-----,------,,,----. U)
8 ...
l .00 2.00
TIME 3.00 4.00 5.00
Figure 5.13 Flyback converter step-load response (CIC, constant frequency control)
(a) load resistance R (b) output voltage v 2
66
5.2 Small-Signal Modeling and Analysis Example
The analytical block diagram for the complete small-signal
regulator model can be constructed using transfer functions
which are derived in previous chapters. It is shown in
Fig.5.14.
The EASYS small-signal model is generated by connecting
the power stage model, analog feedback controller model,
digital signal processor model and load model. Since EASYS
can generate the frequency response between any two vari-
ables, the regulator performance parameters such as loop-
gain, audiosuceptibility, input and output impedances etc can
be generated using TRANSFER FUNCTION command of EASYS. The
frequency response of the loop-gain is generated disconnect-
ing the loop and injecting the small-signal voltage.
The same Buck regulator which is simulated in Section 5.1
is modeled as an example of small-signal model.
Following modules are selected to model the circuit shown
in Fig.5.2.
[UK] --- buck power stage small-signal model
[MP] --- compensator (two-pole one zero)
[SM] --- SCM (current-feedback loop)
67
[PW] PWM ( constant-frequency control) small-signal
model
[LO] --- load
The EASYS Model description data and the EASYS generated
system configuration are shown in Fig. 5. 15 (a) and ( b), re-
spectively. The input data requirement list is shown in
Fig. 5 .16. Figure 3 .17 is the user input Analysis Program
list.
Gain characteristic~ of audiosuceptibility and output
impedance of converter is displayed in Fig.5.18.
To obtain the loop-gain characteristics the system path
is disconnected in the PWM small-signal module and a signal
is injected at the disconnected point. Transfer function
between disconnected points becomes loop-gain. The voltage-
loop and current-loop loop-gains are achieved by freezing the
current-loop module and voltage-loop module respectively.
The loop-gains of the voltage-loop, current-loop, and total
loop are shown in Fig.5.19, Fig.5.20 and Fig.5.21.
68
,. u
2 X 1
____ _.2x2
... .... I y ... ,. ,. u d U=O ____ _.2x2 ____ _.2x1
+
A
X
+ ,. I ,...
d .... ,. d U=O
2 X 1
Hdx
FM
___ ,..1x2 ___ _., X 2
Figure 5. 14 Small signal transfer function model of switching regulator
69
***~*****~*****~•************************ *-1:•i;o BUCK SMALL-SiGNr!>.L.'.MOnlJLAR • (CONST. OFF-TIME CONTROL, SCMI ***************************************** ** REVISED 5/4/36 MACRO FILE NAME=MACROS LIST MACRO COMPONENTS=UK,LO,MP,SM,PW MODEL DESCRIPTION LOCATION= 12, UK, I NPUTS=LO I IL= I 2), rw <DH=D I LOCATION=17, LO, INPUTS=UK I V2=\J 1 l LOCATION=36,MP, INPUTS=UKIV2=VOl LOCATION=34,SM, INPUTS=UKIIL=ILl LOCP.T I ON=43, PW, INPUTS=~1P I VE=VE >, SM I VI=VI I END OF MODEL PRJNT
Figure 5.lS(a) User Input Model Description [BUCKS.MOD]
~••******* ********** * * _V2 UK =V 1 * • • UK * * LO • * 12 •<================================================-==-=>• 17 * * •===================>=========================> * * ********** IL LO =12 I I ********** A I I
I DH PW =D I I I I I I I I
21 23 124 25 126 27 I I I 1 IL UK =IL I V2 UK =VO I I V I)
I ********** ********** I * * * * I * SM * * MP •
3 I 3::3 * 34 * 35 * 36 * 37 I * * * * I ********** ********** I I I l ********** VI SM =VI I I <:- * VE ~1P I =VE I <=======• PW *<================================
4;? * 43 * 44 45 46 '17
Figure 5.lS(b) System Configuration Diagram [BUCKS.MGL]
Phi C> r---
LO
l· M F'ltl \/ \_,J r:~ ,r,J
L '.::iM
h MP
CI 1;1,,,1
',/ l U!i.,
L LU C I U
i:-r~ MP p HM l\lM PH
(INITIAL CONDITIONS AND ERROR CONTROLS REQUIRED) f.1Tt-\TE M/'iMF U\ND DHIFN!::;JON DATf'.ii F~!JH VECTfJF{ ,!'.\MD MATRIX STl'iTES)
Jl I 0
X 1 MP
vc t [)
Figure 5.16 Input Data Reuirement List [BUCKS.MGL]
i ....
·,; I ·rt .. f.::.-::.I3t}(~{-{ ... ~3i"i/\L_!_. T ;:_::~hl/\L ;::-( CL)i\J3·r c1r=-F'w_ .. ,r I !'1lE: 1::~Cil'·1·rr~CJt_1 !~3C:t-i) <·Fz:::~\iI:3EL)-~}/l~ /f{(~. :::--J~· h:. p [)~,JE":F< s·r i1\(~[:-I NIT I AL CONDillDNS } L. i.J~.:~ .. :.-:·. J. (r. ) \)C t}t{~:-_: ~-~(). r-il\Fl\ti1f::·r1::.r-< \it::.t..tJF· :; L. t}/,, ::·;; ::-::: ~:•()' E~ ·-(.;; ,: (: l,.) t\ :.-::.·.t'} ~)(). t:: -~-•t;J f?L. Cli-'~ .. :::.-: l _ t::-····:..::, !~(: tJf.! .. ~::· 1.. ---(_"""! 1,) l tJi-~.:.::.;;_:'.;3
*** VTG FEEDBAC~ COMPENSATOR *INITIAL CONDllIONS ~· Z f\ i~---1 F1 =:= . J. 3 }~ 7· , Z !:i fr1 FJ =.~:-i~ . PARAMETER VAL_UES K MP~. 3,ER MP~6 WZ MP=628, WP MP~lES ~-~'':J r~:-=··:· ;·::;?,D(:1 J:;--r.:--r·i:" L.tJ/;I) INITIAL CONDI1I8NS IL. L.[j::."'.J.(}., ';)1.~ L.O~.:.-~_-'.(i. PARAMETER VALUrs r< 11~ i~.0=~2 .l r:: D L.o=.:-~: _ s, ·r c 1 ... £):;::. 1 L- L.Ci:.-:=tE: -~ .. c· 1 LI::·. Jf~·--7-•~:-t=: E1 c: l'-1 ~. SM=3. 44E3,NV SM~. 08 L SM~7. 28~-9,L SM=2SOE-6 1,:-ref' i,.iM f"~·tf PW::;.;_ 4, j\fN f-Jl;~::'.. j tl~-1 Fl !,~0-"0, V-J P l,J,.:: ~:i, C·/ pi,.J::c.:1, CI pt,.Jc:.j J,:;
PR It•Jl,-ER PL.!:tl-S DNLINE PLOTt3 SS Pl\F~Ar'!El.E.R;:::f.)f-1 ss START~o.ss ~;~1 POII\JTS=5; :3·r1:./;I)"Y s~r/\"TE 1·t;:· r-1;1;\11\.},;'iL. ~::;r: l'-1L.L:
r-:· F{ E>3 ;¥! i r~l:.: 6 . 2 _ r=·r~ t::,~ i'1A X:::=:J. E ~:.1 ·}f· I j\fT CfJi\rrF!CJL.S::· ~IL LG=O,VC l.O=O -ri.:.: Ii\J;=itJ-r~··\.J ·1 l)!-\1 -:·:~ O{Jl"l~lJ .. r:::::\i2 !Jt-<~ TRANSFER FUNCllON TF INPUT=IL LO,lF OUTPUT=V2 UK rR t~h1s:-:;·r-:.R r,:t._1~.:c 1·• J cJr.,-1 !_ I f\JEl\F~ t::,p~f~~L. ~l:3 I~~: PARAMETER VALUfS ;\IN Pl,J::.-c(), MM P~•J::-. ·J C I p I.or~=(.) . 7·•r::-I f .. ;p(J i ==\; .... .) r•t--;~ -~.!~ 11i . .11·F1 l . .i·1· _:.}-•!D f-4 t~J TRANSFER FUNCTlOM PARAMETER VALUES C\/ P\,J:c:c(}. , CJ r,~.J~. J. -rr-~.L\f·.ISt=EF~ FtJNCT J CJ~-! ;":, _,:.\ r~ /':., 1-/!F:-r t'.::.· f~ \/ r"-1 L 1,..1r·_ rj .--. \.' p !;..,J::-.: .• t . 'T ?f\t,1sr:c:~ ;:1Jhtc.~·1 :; C}t·:
Figure 5.17 Analysis Input Program [BUCKS.ANC]
, ... ' ..
;""""T"l ....,.I "'T""I '""!"'Tl '"T""'l'l I i~--:--r-l l'"T""! i 1-:""'!'i ! 1-----;--rl-,-i T""""I I i"T'T'li i -----;I """Tl-Ii":', i~! ! !----;-;I-,-! -:-:-11 r-r,! ! ! I i i il!ii iii il I I ii I I I !ii' i ii 11!1
j" ·1 · 'ill! ,; I .i.-+--r-t-H-M' +-0 -.!.I I I! !I !:11i,, i I 11liii
I :!, I . I: ! 8 I ! I !I -~-i---+--W-l-W+L--+-~~++--+-++~-4--+-~~,+-~TiT:Til,~J
! I Iii - 8 z . -~~-+-++~++---+-+++Hi-tt--t--+-++mH+--+--t-t-+r+Hrr-t--HTitm f§ I
8 aj-1-,,,c.+-+++++l-:+--+--H-~-tt--t--+-t-+++r+t--+--t-t-+t+ttt--t-v-t--t-tttt1 ,.
8 ! ! I'! ! i ! 'i!! ! ! I !!1!, -+-~------.----------------------r-----+---'---------"'1 1 1,E+O I .E+l 1.E•2 1,E+3 1,E+4 1.E•6
FREQ CH2l
Figure 5.18(a) Audiosuceptibility
8-,--.....,...."T"""!-~....----.---.-.-......... ..-----.-._...-,---..,..._ _ ___,...........,....,._ __ ....,..,..,... 0
I Ill! I I I i!!li 11 i 11 I ~.------~1~11~1 i ~' ~~~-==;::;;I ;;;;;;;;i !;;;;;i ! i;;;;;;;;;i ~~-'--'.;..!-..---.1------;l__.;...i ~I I 7!
, , Iii! I 11 !!I 11 -t--+--+-++-!-+1+.---t-:>'f-+-+t-+<4+--+--+-i-+i+H+---+--+-++-H.!-H----+---+-+-+++.;.;.i
- I ii I!
§ 8 i Iii i!I ... z . -~+--+-+-+-~++--+-+-+-~+l---1-~+-++4-i+---1--L.+-~4+-_µ~-4-1-1-H f§ I
8 '-t--r+--t-+-+++t-t+---+--t-+-+-1--H-++----+--+-+~H+---+---+-++++r++---+--+-++++l+I I
I I! I 111 I 11 ill ! I! i ! !!! ! ! 'I!!! I ! : ! ! !!: B I . I
I ,E+O
: I ''
1.E+l 1.E+2 I.E+3 1.E+4 1.E+6 FREQ CH2l
Figure 5.18(b) Output Impedance
VPl&SU
VPl&SU
7J
8 i I i I ii I i i I
I I
I I I
I I ! I l ! 11 1 I 1 !
i I I I I
I I ! I Ii I I I I I I ---. -. --I I I: i:
I i ! iii i i 'i
I I I
I I I I
I ! ' I I: I
8 I ': . I I I --m 0 -z 8 .....
0
8 I
I
I i I 8 I i I ii I i I i Ii ii i I I I! i i1 ! ! ! ! 1 ; ' ' I I I . I i '
1.E+O .E+I J .E+2 1.E+3 1.E+4 1.E+5 FREQ CHZ)
VPl&.SU
- I I I I i I I 11 I I !II ! I ii II! 11 II I! ~~+--+-+--H~r+----+-+-+-+-+,ioR+-~H\++++i-f-+-+-H-Hffl-~+_µ~I, 0
~~--1--T-h-++H---+-+--+--++-H-H---+-+--+-+-tt-H-~----~
Q.
! -+----l---+--+-1--+++1+---+---+-+-l-++H+---+--1---++-+-++++----+----1---+++-'--++,--+--l--!-+-!---.--'---l-l I
i I: 11 -+-- ....................................... _.__ .......... _......+-- ___ .......... __....... _____ ......... ____ ..... ' ....,·; '....-...___.__.........j 1.E+O J .E+I 1 .E+2 1.E+3 1.E+4 1.E+5
FREQ (HZ) VPl&.SU
Figure 5.19 Total Loop-Gain
74
8 _____,.......,.........11,.......,.i I i .--I......--.--.~, .,..,..,.,.1 __ .,....._..,..,.i I ......... ! 1 ---1 ......... 1 i-l 1 __,........,.........,....._..
8 1 ! I I ! Ii I I I I! Ii o+--~~...;....;..:....;____....:....__:.__;___.;._~-;.__.,.....___:__:__;__;__:_.:.;_____;_~L..;....;....;._;__:_;__~__:__:_~
ID i I' ' I I I Ii i I : ':I' I I I lj
n;.,...__..__,...-1 1 I : 8 .... ~--+-+--+-+++-+++--+-+--+-+-H-,-µ-~+4--!-~-----+---+-H--H~-+-~~
=~-t--+-r+-+-+-t++t-+-+--H-r++tt-~~+-H+---+~H+++++--+---+-++H+H 0
8 2+--+-+-+-+-+++++---+---+--++H+++-.--+--+-+++tt+----+----+-1-++-1..µ..__+--"--++++-l--l+I
I
8 i I
1,E+O
ID
.... 0~ ~·
16 a: -b: I
! I
I J.E+O
1.E+I
I
I
J.E+I
I
1.E+2 FREQ CH2)
I I' I I 11 I
I '11 !I I 11 I
I '1 'j
I I I I I I Ii I
I i i l i II I I I • I 1 !' I
J .E+2 FREQ CH2l
I I
1.E+3 1.E+4
I ii i
,,
II
·1 1 ii I iii I l i 1 ! 11
1.E+3 1.E+4
Figure 5.20 Voltage-Loop Loop-Gain
1.E+6
'
. I I'
!
'I
I , : I I ! j !
1.E+6
VPI&SU
VPl&!=:11
8 s
z 8 0
8 I
8
i
I I
1.E+0
I i I I
I I
I I I i I I
I I
'T'\ I I i I ! ! I .I I
! i I Ii Ii , Iii i;
I!!
I I I I I
I I I iii I Ii I
: I I I I I II ! I
1.E•l
75
I
. I ili l I I I I I! I 11
I . I .
I I I 1.11 I I, I I
I ; I 111
i
I ·1 I I I I
I I
Ii I I I i
i I I 'II I I I I I. I , l ! i 1 :,; I /I::.',
,!, 1 :: 1 I . iii ii ' i I i Iii! I '
1~:. 'Iii ' 'I''.
. 11 · i i i i I ',, I I
I! I I II I ~I I I
. I ii ! I ! !
11 '
I I
I i I I
....... I I I I l I Ii I i1 I 1
1 I
I I I I !I ! I I I I I I
I i Ii I ii I I I
11 I I I !i I I I I I I Ii I I! I I I I Ii I I Ii I ! I I I I
' I I• I II : ; : ; ''.I ' ' ! I I 1 1, ' I Ii I ,
l" I I 1.E+2 1.E•3 1.E+4 1,E+S
FREQ CHZ)
111 ! II I ! T 111' 'i I II 11 11., I, 111 I I 1, II 11,,
111111 ,I 11~-~ll.i! i!ll!II ii Ii ID t=t:•~,~i II ===rtli i ~,I•~;,, ~I j8\)-f,-: Ii ~,, ~i I!~,. +-I ~i~I ! : I
,_ I I I \Ii Ii i i i Iii I Iii i 8~-t-,_-+-,H1!~:!~i!t--+,-+-++l4i 1~,-1-+1 +!~1~41~ll-+-W,1l4:.w:!4[!!~~1-U-~!!~il I i iii ilii I I ii 1i1i i i Iii t+ , ! : 1 i !:i: ! 1 1 I 1 Ii!
~~,_ 71_r1·HiJ~i:m1i~l--+'717j+lrri'mi'ii_~j+j+i~li41~1;J-+____;_li~·1~1 :*iiL1'-+---+-+,~!~ii!
' I ! il'lill i ,111 1
11,i i ! ! ! Ill ! i I iii '!'' l-t----+-t-H+t+++-+-+--++H+H--1-++++++-ii~ II -+1-+---ii41.wl4I iLI __j__u_~I
I II I'· I I 11 TI 11111
11 I 11., I, I I, 1,: I
I 1'1 I , I I 1'! . .111·1 ll, 1', I! II, II! i, [!!!, I I I '2 I i ! i 11 I ! i I I I Ii I j I i Ii Ii 1 ! i i ! !
~-r--•---~1•~,~··r,·----•~·~·~·~"~·~-~'-·-'~''~"·~;----__...... .......... ~,.-----'~·~··' 1.E•0 1.E•l 1.E•2 1.E•3 1.E+4 I.E•S
FREQ {HZ)
Figure 5.21 Current-Loop Loop-Gain
VP[&SU
VP[&SU
Chapter 6
CONCLUSION AND FUTURE WORK
This thesis introduces the modular approach for the mod-
eling of the switching regulator using EASYS software pro-
gram. The switching regulator is divided into the power
stage, analog feedback controller, and digital signal
processor according to its function. Each functional block
is modeled as a independent module and a regulator is con-
figured by collecting appropriated pre-defined modules which
are stored in macro library.
The converter power stage was modeled with unterminated
two-port model using hybrid-g parameters. The large-signal
model of power stage has three sets of matrices coefficients
and appropriate sets of matrices are selected according to
the status of duty cycle which is determined by the digital
signal processor module.
state equations are used.
For small-signal model, averaged
Four power circuit topologies,
buck, boost, buck-boost(flyback) and forward converter, are
modeled.
The analog feedback controller was modeled with two
seperated modules, voltage feedback compensator module and
current feedback module. Transfer function model was chosen
so that it can be used for both the small-signal and large-
76
77
signal model. For the voltage feedback compensator, three
commonly used compensators were modeled. For the current
feedback module, SCM and CIC schemes were modeled.
Three different control law, constant frequency control,
constant ON-time control and constant OFF-time control were
modeled for the digital signal processor block.
Switching regulator large-signal model performed time-
domain simulations for the cases of steady-state and step-
load transients. It was demonstrated that EASYS small-signal
model can be used for the transfer function analysis of
switching regulator such as audiosuceptibility and input
output impedance. Frequency response of system loop-gain was
also presented for stability analysis. Other analyses are
possible using the EASYS Analysis capabilities such as Root-
locus, Steady-state analysis, Linear model generation, opti-
mal controller synthesis, and etc.
Possible future work includes the improvement of numerical
integration method. In this time-domain simulation, ineffi-
cient fixed step integrator and very small step sizes are
used because switching waveform has very steep rate at the
switching instant.
APPENDIX I
Macro Component Descriptions
This section describes a set of EASYS macro components
developed in this study. Major equations, a circuit model
and a program listing are provided for each macro component.
The macro components are listed in the following table.
Macro Component Name
BC
BT
FB
FW
UK
ST
BB
WD
TABLE OF MACRO COMPONENTS
Description
- 'CONVERTER POWER STAGE LARGE-SIGNAL MODELS -
Buck Converter Power Stage
Boost Converter Power Stage
Buck/Boost Converter Power Stage
Foward Converter Power Stage
- CONVERTER POWER STAGE SMALL-SIGNAL MODELS -
Buck Converter Power Stage
Boost Converter Power Stage
Buck/Boost Converter Power Stage
Foward Converter Power Stage
78
Macro Component Name
DG
MP
PZ
SM
cc
WM
FF
NN
PW
LO
PT
79
Description
- COMPENSATOR MODELS -
Lead-lag Compensator
Two-pole One-zero Compensator
Two-pole Two-zero Compensator
- CURRENT-FEEDBACK LOOP -
SCM Current Loop
CIC Current Loop
- PWM MODELS LARGE-SIGNAL -
PWM (Constant Frequency Control)
PWM (Constant Off-Time Control)
PWM {Constant On-Time Control)
- PWM MODELS SMALL-SIGNAL -
PWM
- LOAD MODELS -
LCR Load
Constant Power Load
V
I
IQ
Vl
12
IQ
C
L
RC
RL
V2
Il
IL
vc
IS
VL
80
BC BUCK CONVERTER POWER STAGE
(LARGE-SIGNAL)
INPUT
variable
variable
variable
parameter
parameter
parameter
parameter
OUTPUT
variable
variable
state variable
state variable
variable
variable
R C
C
input
input
V
I
voltage
current from
switching function
load
(if switch is on, IQ=l) (if switch is off, IQ=O)
capacitance
inductance
capacitor effective resistance
inductor effective resistance
output voltage
output current to source
inductor current
capacitor voltage
switch current
inductor voltage
Volts
Amps
Farads
Henries
Ohms
Ohms
Volts
Amps
Amps
Volts
Amps
Volts
EQUATIONS
For IQ= 1:
[ -(RL+RC)/L
1/C
RC
1
For IQ= 0, IL> 0:
• [ I: 1 = r-(RL+RC)/L
VC 1/C
RC
0
For IQ= O, IL= 0
81
-RC/L] [ Vl ] -1/C 12
-1/C
82
***************•R**R~~R*****~•**~* ** LARGE SIGN~L MODEL OF BUCK(W/0 LOAD> POWER STAG~ ONLY
**************************************** ** REVISED 1?./3/85 MACRO FILE NAME~MACROS DEF I NE M1\CRO=:ftC MACRO INPUTS:,
C L RL RC IG Vl 12 * IG SWITCHING FUNCTION * IQ=l (SWITCH;ON) * IQ=O <SWITCH;OrF)
* V1 INPUT VOLTAGE * 12; INPUT CURkENT<r-ROM LOAD) MACRO OUTPUTS:: IS IL ILL VL VC V2 11
* IL; INDUCTOR CURRENT<STATE> * VC; CAPACITOR VOLTAGE<STATE> IS; SWITCH CURRENT * ILL; INDUClOR CURRENT(DUMMY> * VL TRANSF-ORMER VOLTAGE * V2 OUTPUT VOLTAGE * 11; OUTPUT CURRENT<TO SOURCE)
MACRO CODE MACRO STOP SORT *i:--1:·*
IF(DABS(IG BC--). LT. 1. E-10)THEN IF ( IL BC--. L.E. 0. ) THEN
MACRO ILLBC --= 0.
DERIVATIVE, IL BC--=O.
****
*
GOTO H· .. 77 ~LSE=.
TOFF ***** A11=-CRL BC--+RC BC--)/L BC--A12=-l/L iiC·• · A21=1/C BC--A2~!==0. Bl 1=0 B 12=RC BC:··-/L BC --B21=0. B22=-1/C BC--C11=RC IiC·--C12=1 C21=0 C22=0 DlJ=O D12=-RC BC--D21=0 D22=0 IS BC--::.00
END IF ELSE
TON*** All=-<Rl. A12:::-1/L A21=1/C
HC·-·-+RC BC--> /l i!C ---
HC ·•·-
BC--
A;!;'= 0 B 1 l = t / l Ji(: ···· B 12=HC I<C - · /I I•C: ·-82 J :=O 822=-1 /C -C11=RC HC --C12=1 C21=-1 C22=0 D11=O D12=-RC BC-·-D21=O D22=0 IS BC--= 0 JL BC--END IF
** OUTPUT EO. * *-- -*l V2 C11 C12 IL l
83
*: = : + *: Il C21 C22 VC If,
*
D11 D12 D21 D22
BC--~CJ1 *IL DC--i-C12*VC nc--+ D11*V1 BC-- +D12*12 BC--BC--=:..C21*IL BC·--
Vl 12
V2 :!<
11 VL BC--~<All*IL BC--+A12*VC BC--+B11*V1 BC--+
812*12 BC-->*L BC--
*
EG.
dIL/dt dVC/dt
A11 A12 A?l A22
IL
vc :1'11 B12
• I :B21 B22
MACRO DERIVAllVE, IL BC--=VL BC--/L BC--+++77 CONTINUE MACRO DERIVATIVE, VC I3C-·-=A21*IL BC--+f',22*VC BC--i-
& B21*V1 BC--+B22*I2 BC--ILLBC ··-=-IL BC--IF< IL.LBC··-. LE. 0. > ILLBC--=O.
MACRO RESUME SORT END OF MACRO MODEL DESCRIPTION LOCATION= 22, BC END OF MODEL
Vl 12
84
BT BOOST CONVERTER POWER STAGE
(LARGE-SIGNAL)
v2
Vl Il R
C
12 IL CI IQ VL 0 0
INPUT
Vl variable input voltage Volts
I2 variable input current from load Amps
IQ variable switching function (if switch is on, IQ=l) (if switch is off, IQ=O)
C parameter capacitance Farads
L parameter inductance Henries
RC parameter capacitor effective resistance Ohms
RL parameter inductor effective resistance Ohms
OUTPUT
V2 variable output voltage Volts
Il variable output current to source Amps
IL state variable inductor current Amps
vc state variable capacitor voltage Volts
IS variable switch current Amps
VL variable inductor voltage Volts
EQUATIONS
For IQ= 1 :
RL/L
0
0
1
For IQ= 0, IL> 0:
-(RL+RC)/L
1/C
RC
0
For IQ= 0, IL= 0
85
1
0
+
+
1/L
-1/C
1/L
86 *·**********~****•*************~~« i. * LAt•u.,;E SI GNl'.L l'lrlDEL OF DIJOST ( W/Cl UJf'\IJ) * POWER S I l\Gl:. ONI. Y * REVISED 11/19/8~ ******************************************* MACHO FILE NAM~=MACROS DEFINE M/'>.CRO= HT MACRO INPUTS=-
C L RL RC Vt 12
MACRO OUTPUTS:.: IS IL ILL VC V2 11
MACRO CODE MACRO STOP SORT **** IJ:(DABS( IG BT-->. LT. 1. E-5>THEN
IF ( IL BT--. LE. 0. > THEN ILLBT--=-0.
MACRO DERIVATIVE, IL BT--=O. GOTO t-t-t•77 ELSE
**** TOFF *****
*
All=-<RL Bl--+RC BT--)/L BT--A1~=-1/L rn--A21=-11c BT--A22=0. Bll=l/L Bl-·-B12=RC 1·fr--/L BT --B21=0. B22==-1/C BT--C ! 1::-.;RC In - -C12=1 C21=1 C22=0 D11=0 D12=-RC BT--0~1=0 D22=-0
IS BT---= (l ~ND Jr·
ELSE ***TON***
A11=-<RL 81--)/L BT--A12=0 A21=0 A22=0 Bll=-1/L rn --B12=0 B21=0 B22=-1/C BT--C11=0 C12=1 C21=1 C22=0 D11=0 D12=-RC BT--D21=0
D22=-:0 IS tn - ·= ll H I • -END JF G Bl--= JG
i:·* OUTPUT EO. * *-•-- -*: V2 C11 Cl~ *: = *: I 1 C21 C~2 * ... -
87
IL vc
I· D11 D12 D21 D22
V2 BT--=C11 ~IL RT--+C12*VC BT--+ D1 J il-V 1 RT-- +D12*12 BT--
Il BT--==C~l*IL BT --VL=<A11*IL BT--+A12*VC BT--+B11*V1
& B12*12 BT-->*L BT- -** STATE EG. * * dIL/dt A11 A12 IL :n11 i:· + I
I
* dVC/dt A2! A;:,2 vc 1821 * * MACRO DERIVATIVE. IL BT--=-VL/L BT--t-++77 CONTINUE
Bl--+
812 B22
V1 12
MACRO DERIVATIVF,VC BT--=A21*IL BT--+A22*VC BT--+ & B21*V1 BT--+B22*I2 BT--
ILLBT -•-:: IL BT --IF< ILL BT--. LE. 0. ) ILLBl ··-=-0.
* MACRO RESUME SORl END OF MACRO MODEL DESCRIPTION LOCATION~ 22, RT END OF MODEL
Vl 12
88
FB BUCK/BOOST(FLYBACK) CONVERTER POWER STAGE
(LARGE-SIGNAL) v2
Vl R p I p 12
PHI • C IQ
0 VL
INPUT
Vl variable input voltage Volts
12 variable input current from load Amps
IQ variable switching function (if switch is on, IQ=l) (if switch is off, IQ=O)
C parameter capacitance Farads
LP parameter primary inductance Henries
LS parameter secondary inductance Henries
RC parameter capacitor effective resistance Ohms
RP parameter inductor effective resistance Ohms (primary)
NP pa:t:'ameter no. of turn of primary
NS parameter no. of turn of secondary
OUTPUT
V2 variable output voltage Volts
IP variable output current to source Amps
PHI state variable flux
vc state variable capacitor voltage Volts
IS variable secondary current Amps
VL variable inductor voltage Volts
EQUATIONS
For IQ = 1
•
I IL l [ -~/NP = • vc
( :: ] [ 0 =
NP/LP
For IQ = 0, PHI > 0 :
•
[ ~:] r-(RS+RC)/LS =
NS/C/LS
[ :: l = [ NS*R:/LS
For IQ= 0, PHI= 0
[ [
0
0
0
0
89
0 l [ :: ] [ 1/NP +
0 0
1 l [ :: ] [ 0 +
0 0
-1/: l [ :: J
-R:] I:: l
90
-!:'.·** ***.;.;•-t:·-lc-l'<·* ~*.-.;-*~fr* * Ii-** l'-1<--f':--i:•-;,:--1!-~-*·r•l· R-1.-r.·* Lf>.RGE SIC-:Ntil MODfL OF FLYHf.1LK(t..J/D LOt:D) * POWER STAGF ONLY **************••~**************•*********** ** REVISED 12/7/85 MACRO FILE NAM[~MACROS DEFINE MACRO=FB MACRO INPUTS=-·
C LP LS NS NP RP RS RC OG V1 12 * V1 INPUT VOLTACE * 12 INPUT CURRENT<FROM LOAD) * LP PRIMARY INOUClANCE * LS SECONDARY INDUCTANCE * NP # OF TllRN <PRIMARY) * NS # OF TURN <SECnNOARY> * GG SWITCHING FUNCTION * GG=1 <SW:ON> * GG=O (SW:OFF>
MACRO OUTPUTS~ PHI 11 IP IS VL VC V2 * PHI; FLUX(STATE) * VC; CPACITOR VCLTAGE(STATE> * IP; PRIMARY CURRE:NT * IS; SECONDARY CURRENT
MACRO CODE MACRO STOP SORT **** IF(DABS<GG FB-->. LT. l. ~-5)THEN
IFCPHIFB---. LF. 0. >THEN MACRO DER IVA1 IVE:., PHI FB--=O.
GOTO H· t-'/7 ELSf
**** TOFF ***** A11=-CRS FD---RC FB-->ltS FB--Al2=-1/NS F-D--A21=NS FB--/(C FB--*LS FB--> A22=0. Bl 1=0 B12=RC FD--/NS fB--B21=0. B22=-1 IC FH·- -C11=NS FB--*RC FB--/LS FB--C12-1 C21=0 C22=0 D11=0 D12=-RC FP. ---D21=0 D22=0 SE=1
END lF ELSE
~**TON*** A11=-RP F~--/LP FB--Al2=0 A21=O
fl ;., .. '°' () B11=-=1/MI' l·ll · · D 1 ;:1==0 D21==0 B22=-1/C r..:i~---Cll=O C12=-1 C21=NP FB--/LP FR--C22=0 D11=0 D12=-RC FB--D21=O D22=O SE=O END IF
91
** OUTPUT EG. * *-- -*I V2 *I II-: I 1 * -
V2 &
- C 11 C12 PHI I D11 I + I
C21 C22 vc I D21 I I I
FB--=C11 *PHIFB--+C12*VC FB--
D12 Vl D22 12
I 1 VL
+ D11*V1 FB-- +D12*12 FB--FB--::.:C?l*PHIFB--FB--=A11*PHIFB--+A12*VC FB--+Bll*Vl FB--+
r~
B12i:·I2 FB--FB--=11 Fl< --FB--=SE*NS FB--*PHIFB--/LS ~B--EG.
* * * * *
dPHI/dt I All 1\12 PHI: lB11 Bl? : =-
dVC/dt I A21 A22 I I
vc :
MACRO DERIVATIVE,PHlFB--=VL FB--++¼-77 CONTINUE
I- : :821 I I
B22
M~CRO DERIVA11V~.vc FB--=A21*PHJFB--+A22*VC FB--+ 821*V1 FB--+B2?*I2 FR--
* MACRO RESUME SORl END OF MACRO MODEL DESCRIPlION LOCATION= 22, FB END OF MODEL
Vl 12
IQ
Vl
I2
IQ
C
L
RC
RL
N
V2
IP
IL
vc
IS
VL
92
FW FORWARD CONVERTER POWER STAGE
(LARGE-SIGNAL}
o---
INPUT
variable
variable
variable
parameter
parameter
parameter
parameter
parameter
OUTPUT
variable
variable
state variable
state variable
variable
variable
I p
input voltage
input current from load
switching function (if switch is on, IQ=l) (if switch is off, IQ=O)
capacitance
inductance
capacitor effective resistance
inductor effective resistance
turns ratio(N=NS/NP)
output voltage
output current to source
inductor current
capacitor voltage
switch current
inductor voltage
Volts
Amps
Farads
Henries
Ohms
Ohms
Volts
Amps
Amps
Volts
Amps
Volts
EQUATIONS
For IQ= 1
•
[ ~:] [ -(RL+RC)/L =
1/C
( :: l [ RC =
1/N
For IQ= 0, IL> 0:
For IQ =
•
[ IL ] . vc
[ :: l
= [-(RL+RC)/L
1/C
0,
=
=
RC
0
IL= 0
r o L o
r 0
L 0
93
[ :~ J -:/L] [ :: l [ N~L RC/L l + -1/C
1 ] [ :: ] ( 0 -RC
J ( :~ J + 0 0 0
+
: ] [ :: ] + [ : -1/:] [ ::] : ] [ :: ] + [ : -R:] [ :~ J
94
*****************~****f*******~************ -t:-* LARGE SIGN/'.L l'IOl>E.L LlF FDf<Wl\HD CONVERl EH · * POWER STAGf ONLY *****************************~************* ** REVISED 12/20/B~ MACRO FI LE NAME=-MACROS DEFINE MACRO.,FW MACRO INPUTS=-=
C L RL RC IG VJ 12 NS NP * IG SWITCHINR FUNCTION * I G= 1 < SW I TC H; ON > * IG=O (SWITCH;OFF> * V1 INPUT VOL.lAGE * 12; INPUT GUHRENT<FROM LOAD>
MACRO OUTPUTS:: IS IL ILL VL VC V2 IP * IL; INDUCTOR CURRENT(STATE) * VC ; CAPAC I'I OR VOL T.'\CE (STATE> * IS; SWITCH CURRENl * ILL, CURRFNT(DUMMY> * VL TRANSFORM~R VGLT~CE * V2 OUTPUT VOLTAGE * IP; PRIMARY CURRENT(TO SOURCE>
MACRO CODE MACRO STOP SORT **** XN=NS FW--/NP FW--
IF<DABS(JG FW-->. LT. 1. E-10)"JHEN IF< IL Flrl - -. U:. 0. > THEN ILLFW --=-0.
MACRO DERIVATIVE, IL FW--=O. GOTO l•·H•77 ELSE
*-S-:·** 1 OFF **-!::·i-'.·* A 11 =- ( RL. FW - - t-RC FW--) /L. f-1,J--A 1 2= - 1 /I F-i,. ·· A2l=l/C rW·--A22=0. B11=0 B12=RC FW--/L FW--1321=0. 1322:::-1/C FW--Cll=RC FW--C12=1 C21=-0 C22=-=0 D1 l=O D12=-RC FW--D21=0 D22=0 IS FW--=--0
END JF ELSE
-t:·** TON *** A11=-<Rl f·W--·t-RC FW--)/l H·J--
/\.t2~- -1/1 F·l-1 · 1\ ;:'. l :.. 1 / (: I· 1,J · · l'\~~•=·O 13 J 1 = X NL H·J · · Bl2=RC r-W-··/L r:1,J--821=0 B~2=-1 /C FW ---C 11=-RC FW --C 12=1 C21=1/XN C22=0 D11=0 D12=-RC FW--D21=O D22=O IS FW--=-1 L ,-;w--ENP IF
95
** OUTPUT EQ. -r-*-- -*I V2 *I -*I IP * -*
C11 Cl~ IL D11 ·I-
C21 C22 vc D21
FW--=-C1 l -r.-TI. Fl,l--+C12*VC FW···-+ D11*V1 FW-- +D1?.*l~ FW--FW---::a(:~ 1 *IL FW --
D12 I Vl I I I
D22 I 12 I . I
I
V2 &
IP VL FW--~ < A 11 •IL FW--+Al2*VC FW--+R11*Vl FW--+
812•12 FW-->*L FW--** !!-If-
* * * *
EG.
dIL/dt dVC/dt
Al 1 f-.12 IL : B 11 B 1 ;::, + :
A21 A22 vc :R21 822
Ml'.CRO DERIVAl IVE, IL- FW--=VL. FW--/L f-1,J--+·H·77 CONT I NUF M~CRO DERIVAllV~.vc FW--~A21•IL FW--+A22*VC FW·--+
& B21•V1 FW--+R22*I2 FW--* ILL.FW---=-IL FW--
IF( ILLFl,J--. IE. 0. > ILLFW--=-0. MACRO RESUME SORT END OF MACRO MODEL DESCRIPTION LOCATION= 22, f-'l,l f:ND OF MODF'L
Vl
12
96
LEAD/LAG COMPENSATOR DG
V 0
VO
K
ER
wz WP
(K*VO-ER)
INPUT
variable
parameter
parameter
parameter
parameter
OUTPUT
GA (l+S/WZ)
(l+S/WP)
input bus voltage
voltage dividing
op.amp.reference
frequency of zero
frequency of pole
Volts
factor
voltage Volts
rad/sec
rad/sec
VE variable ac component of control vtg. Volts
Xl state variable intermediate state variable
EQUATIONS
VE= [ Xl + (K * VO - ER) *GA/ WZ] * WP • Xl =GA* ( K * VO - ER)
97
******************************** *** COMPENSATOR(LEAD,LAG) ****************************** MACRO FILE NAME~MACROS DEFINE MACRO=DG MACRO INPUTS='
* * VO * wz * WP * K * * ER * MACRO * X1 * VE MACRO MACRO *
GA WZ WP K ER VO
;POWER STAGE OUTPUT VOLTAGE ;ZERO FREOUENCVC2*PI*F> 1POLE FREOUENCVC2•PI*F> ; OUTPUT VOi .TAGE DIVIDING RATIO
<IF VTG IVIDER NOT USED,K=1> ;REFERENCE VOLTAGE OUTPUTs~x1 VE ;DUMMY SlATE. ;OUTPUT VOLTAGE<TO PWM> CODE STOP SORT TC 1=1 /Wl DG-·-TC2=1 /WP l>G--ERR=K DG··-•VO nG-·- - ER DG·--VE DG ·- .. (X1 UG--+ERR*TC1*GA DG--)/TC2
MACRO DERIVATIVE,Xl DG--=GA DG--*ERR - VE DG ·-* MACRO RESUME ~ORT END OF MACRO MODEL DESCRIPTION LOCATION=22,DG END OF MODEL
V 0
VO
K
ER
wz WP
98
TWO-POLE ONE-ZERO COMPENSATOR
(K*VO-ER)
INPUT
variable
parameter
parameter
parameter
parameter
OUTPUT
WM (l+S/WZ)
S (l+S/WP)
input bus voltage
voltage dividing
op.amp.reference
frequency of zero
frequency of pole
MP
Volts
factor
voltage Volts
rad/sec
rad/sec
VE state variable ai::: component of control vtg. Volts
Xl state variable intermediate state variable
EQUATIONS
ERR= K * VO - ER • Xl = ERR - ( Xl +ERR/ WZ) * WP • VE= WM* ( Xl +ERR/ WZ) * WP
99
******************~************* *** COMPENSATOR(! ZER0,2 POLE> ****************************** MACRO FILE NAME=MACROS DEFINE MACRO=MP MACRO INPUTS=
WM WZ WP K ER VO
* * * * * * *
VO ;POWER STAGE OUTPUT VOLTAGE WZ ;ZERO FREGUENCY<2*PI•F> WP ;POLE FREGUENCYC2*PI*F>
K ;OUTPUT VOLTAGE DIVIDING RATIO <IF VTG IVIDER NOT USED,K=l>
ER ;REFERENCE VOLTAGE * MACRO OUTPUTs~x1 VE * X 1 ; DUMMY STATr-* VE ;OUTPUT VOLTAGE(TO PWM) MACRO CODE MACRO STOP SORT * TCl=-1/WZ MP--
TC2=1/WP MP--ERR=~ MP----i:vo MP-- - ER MP--
MACRO MACRO
DERIVATIVE. X 1 MP--=ERR - CX1 MP--+ERR*TC1)/TC2 DER IVAT 1\/E, VE MP·--=e-A-MP·--• C X 1 MP--+ERR•TC 1 > /TC2
* MACRO RESUME SORT END OF MACRO MODEL DESCRIPTION LOCATION=;;?2,MP END OF MODEL
WM
V 0
VO
K
ER
.. ,
WZ1,WZ2
WP
VE
Xl,X2
100
TWO-POLE TWO-ZERO COMPENSATOR PZ
WM( l+S/WZl) ( l+S/WZ2) VE (K*VO-ER)---------- ~---.
S (l+S/WP)
INPUT
variable input bus voltage
parameter voltage dividing factor
parameter op.amp. reference voltage
parameters frequency of zero
parameter frequency of pole
OUTPUT
variable ac component of control vtg.
state variables intermediate state variable
Volts
Volts
rad/sec
rad/sec
Volts
EQUATIONS
Z2 = WM* WP / WZl /WZ2
ERR= K * VO - ER
VE = X2 + Z2 * ERR • Xl = ERR* WM * WP • X2 = Xl +Z2 * (WZl + WZ2) * ERR - WP* VE
101
****~*~*************•*~******** *** COPZENSATORC2 ZER0,2 POLE) ****************************** MACRO FILE NAMF.~MAC~OS DEFINE MACRO=-PZ MACRO INPUTS=
WM W7.1 WZ2 WP K ER VO
* * VO ;POWER STAGF OVTPUT VOLTAGE * WZ1,WZ2 ;ZERU FREGUENCIES<2*PI*F> * WP ;POLI:; FREGUtNCY<2*PI*F> * K ;OUTPUT VOLTAGE DIVIDING RATIO * <IF VTG IVIDER NOT USED,K=1) * ER ;REFERENCE VOLTAGE * MACRO OUTPUTs~x1 X2 VE * X1, X2 ;DUMMY STAlE * VE ;OUTPUT VOLTAGE<TO PWM> MACRO CODE i"U\C RO STOP SORT * Z2=WM PZ--*WP PZ--/WZ1PZ--/WZ2P1--
ERR=K P7--*VO PZ-- - ER P7--VE PZ---::.;X2 PZ--+Z2*ERR
MACRO DERIVATIVE, Xl PZ -:;.ERR *WM PZ--*WP Pl--MACRO DERIVATIVE, X2 PZ--=X1 PZ--+Z2*0-IZ1PZ··-+WZ2PZ-->*ERR
& -WP PZ--•VE PZ--* MACRO RESUME SORT END Or- M1\CRO MODEL DESCRIPTION :lz END or- MODEL
102
S.C.M CURRENT LOOP SM
_v_L--1....___S_M _ __,--v-I_)
INPUT
VL variable input bus voltage Volts
NV parameter transformer turns ratio
C parameter current-loop capacitance Farads
R parameter current-loop resistance Ohms
OUTPUT
VI I state variable current-loop output voltage Volts
EQUATIONS
• VI= NV* VL / ( C * R)
103
***************************************** *** CURRENT LOOP <SC M> MODULE **************************************** * MACRO FILE NAME=MACROS DEFINE MACRO=-SM MACRO INPUT-S=
VL NV C R
* * * VL; TRNASFORMER VOLTAGE<FROM POWER STAGE) NV; TRANSFORMER TURNS RATIO
* MACRO OUTPUTS=VI * * *
VI; CURR~NT LOOP OUTPUT VOLTAGE <TO PWM BLOCK)
* MACRO MACRO *
CODE STOP SORT
*STATE EQUATION MACRO DERIVATIVE,VI
* MACRO RESUME SORT END OF MACRO MODEL DESCRIPTION LOCATION=22,SM END OF MODEL .
SM--=NV SM--*VL SM--/ <C SM--*R SM--)
104 cc CURRENT INJECTION CONTROL
_I_L_·--..1 .... __ c_c __ :_v_I_ ...
l°NPUT
IL variable inductor current ( if flyback, flux)
NI parameter current transformer turns ratio
NP parameter if flyback, primary# of turns ot}J.erwise NP=l
LP parameter if flyback, primary inductance otherwise LP=l
RW parameter current loop resistance
OUTPUT
VI variable current loop output voltage
EQUATIONS
For FLYBACK CONVERTER
VI= NP/ LP* IL* RW / NI
For OTHER CONVERTERS
VI= IL* RW / NI
Amps
Henriee
Ohms
Volts
105
***************************~********* *** CURRENT LOOP <C IC) MODULE *******~**************************** MACRO FILE NAME=MACROS DEFINE MACRO=CC MACRO INPUTS=
* * IL * * NI * NP * * LP * * MACRO *
IL NI RW NP LP
INDUCTOR CURRENT<FROM POWER STAGE> (FLUX IF BUCK/BOOST> CURRENT TRANSFORMER TURNS RATIO IF FLYBACK: POWER STAGE PRIMARY# OF TURNS OTHERWISE NP=1 IF FLYBACK; POWER TRANSFORMER PRIMARY INDUCTANCE OTHERWISE LP=1
OUTPUTS==VI * VI; CIC OUTPUT CONTROL VOLTAGE * MACRO CODE MACRO STOP SORT * VI CC--=NP CC- /LP CC--*
& IL CC--•RW CC--/NI CC--* MACRO RESUME SORT END OF MACRO MODEL DESCRIPTION LOCATION=22,CC END OF MODEL
VE
VI
TI
VP
VQ
ER
VR
vc IQ
106 WM PWM(CONSTANT FREQUENCY CONTROL)
(LARGE-SIGNAL)
::~~---_-_- _.-M~.,_ __ WM __ :--IQ-•
INPUT
variable voltage-loop error voltage
variable current--loop error voltage
parameter switching period
parameter amplitude of external ramp
parameter thershold voltage
parameter reference voltage of op.amp.
OUTPUT
variable reference voltage
variable total control voltage
variable switching function
EQUATIONS
VR =VP* {TN - N) + VQ
VC = - VE - VI
IF VR > VC, IQ= 0
Volts
Volts
Seconds
Volts
Volts
Volts
Volts
Volts
107 ********************•****~~******~ *• PW. M <CONSIANT F~EOUENCY)*~• ***~***************•*•**~•~~*****~** MACRO FILE Nl'.MF= M(\,CHOS r>fT I NE MACHO=- \.-JM MACRO I NPUTS 0
* * * * * * * * * * * * *
TI VP VO ~R CIC SCl-1 VE VI EPS vex VCN IL X DMN DMX VE ; VI ; CIC; SCM;
TI VP VG ER
AMPLIFIED ERROR VTG(FROM COMPENSATOR> INPUT VOLTAGE FROM CURRENT FEEDBACK MODULE IF ClC, CIC:::1 OTHERWISE CIC::.:O IF SCM, SCM=l OTHERWISE SCM=O SWICIUNG INTERVAL AMPLITUDE OF EXTERNAL RAMP ( IF EXT. RA,1P NOT USED, VP::.:O) THRESHOLD VOLTAGE REFERNCE VOLTAGE OF OP.AMP
MACRO OUTPUTS=-
* * * * I}
* i:·
VR VC TN vs VR vc IO
EXTERNAL RAMP VOLTAGE TO'I AL CONTROL VOLT AGE SWITCHING FUNCTION ( Ir- SWITCH=ON, IG=1) CIF SWITCH=OFF, IG::.:O)
MACRO CODE MACRO STOP SORT **~* *** RAMP GENERATION * TN WH--~<TIME~TI WM--)/TI WM--
NP=N N=IDINT<lN WM--~ VR l-JM--=--VP WM--i:·(lN WM-- -N>+VG WM-•-
VC WM--=. . ·-VE WM---CICWM--*V~ WM---& Srt•!~·!:0-: ~\/ 1 \.-JM ---* OP-AMP SATURATION
IFCVC WM--.GT.VCXWM--)VC WM--=VCXWM--IF(VC WM--.LT.VCNWM-->VC WM--=VCNWM--* COMPARATOR IF( IQ WM··-. GT. EP~')THEN
VS WM---:::VJ l-JM--IF CVR WM--.GT. ~C WM--)THEN IG WM --=O END JF
ELSE VS WM-·-,,.,O.
END IF IF<NP.NE.N>IO WM--=1
*PROTFCTICN
i-"
D= l N \.JM-- - ·N IF(D. Ll. UMNWM-->IG WM--~1 IF(D.GT. DMXWM--)10 WM--~o IF ( IL WM·--. Cl. 1 LXWM--) I G WM---=-O
MACRO RESUME SORT F.:ND ClF MACrrn MODEL DESCRIPTION LOCATION= 22, WM E:ND OF MODEL
108 FF PWM(CONSTANT OFF-TIME CONTROL)
(LARGE-SIGNAL)
_:_: __ ~~._ __ F_F _ ___,1--Q~
INPUT
VE variable
VI variable
TOF parameter
SLP parameter
VTH parameter
ER parameter
OUTPUT
Q variable
VR variable
vc variable
EQUATIONS
vc = - VE - VI
VR = V{RAMP) + VTH
IF VR VC, Q = 0
voltage ... loop error voltage
current-loop error voltage
constant off-time interval
slope of external ramp
threshold voltage
reference voltage of op.amp.
switching function
reference voltage
total control voltage
Volts
Volts
Seconds
Volts/sec
Volts
Volts
Volts
Volts
109
****~*******~*•~*•*~~•***~•**~~~**~~*** fJ WM (CONSlt.Nl 1,:-1- Tli'!r:. crn,r1r~C1l)
************~*t~-•~*******~~*********** MACRO FILE N1-\ML·0 -M/\Cl-<03 DE"F INE M#\CR0"-1-r-MACRO I NPU"f S=
* * * * * * • * * * * * *
VE VI TOF C:P~-.
ER CIC: IL VTH SCM
SL r-' JLM
VE ;AMPLIFIEU ERROR VTG<FROM COMPENSA10R) VI ; INPUT VTG FROM CURRENT FEEDBACK MODULE
CIC; IF CJC, CIC=l OTHERWISE CIC==O
SCM; IF SCM, SCM=l OTl-lt:Rll'Jl SE SCM:-:-0
TOF; CONSTANT OFF TIME INTERVAL SLP; SLOP OF EXTERNAL R~MP
( IF EXT.RAMP NOT USED,SLP=O) VTH; THRESHOLD VOLTAGE ER; REFERNCE VOLTAGE OF OP.AMP
MACRO OUTPUTS=-· VR VC Q
* * VR; EX1EHNAL RAMP VOLl~GE PLUS THRESHOLD VTG * VC; TOTAL CONTROL VOLTAGE * G; SWITCHING FUNCTION * <IF SWITCH=ON, 0=1> * <IF SWJTCH=OFF,O=O> * TC; OFF TIME INSTANT * TR; ON llM~ JNSTANT MACRO CODE MACRO STOP srir~T **I:·*
VC FF--~ -VE FF---CICFF--*VI FF---& SCMFF--•VI FF--
****** IF(TIME. G"I. EPS)GOTO H-t-11 T:eTJMt:: G Ff· - ·-= J GOTO t- .. :-?2
+++11 CONTINUE * *
IFCG FF--.LT.EPSFF-->THEN IF<<TIME-TC>.GE.TOFFF-->THEN Tf~:-T l Mt-Ci r-r-- -:-1
ENn lF ELSE VR FF--=SLPFF--*(TIME-TR)+VTHFF--
IF(VR FF--.GE.VC FF-->THEN G FF ---=-0 TC=-TlME l:-NJ> Jr·
END IF +++22 CONTINUt:.
IF<IL FF·•-. GE. ILMFF--)0 FF--~o MACRO RESUME sorn END OF MACRO MODEL DESCRIPTION LOC.-.\TION= 22, r-F END OF MOf>EL. *
110
PWM(CONSTANT ON-TIME CONTROL) (LARGE-SIGNAL)
NN .,
VI NN --
INPUT
VE variable
VI variable
TOF parameter
SLP parameter
VTH parameter
ER parameter
OUTPUT
Q variable
VR variable
vc variable
EQUATIONS
vc = - VE - VI
VR = V(RAMP) + VTH
IF VR < VC, Q = 1
Q -
voltage loop error voltage
current loop error voltage
constant off-time interval
slope of external ramp
threshold voltage
refernce voltage of op.amp.
switching function
reference voltage
total control voltage
Volts
Volts
Seconds
Volts/sec
Volts
Volts
Volts
Volts
111 *********•******************~****•****~ * p l,J M ( CONST fo.Nl OM l 1 ME CClN"I nm ) ***************~~********************** MACRO FILE NAM[•: M1~CROS DE.-I NE NN MACRO I NPu·r S=·
VE VJ TON FPS
ER CIC *
Il VTli SCl'l
l l M
* * * * * * * * * * * *
VE ;AMPLIFIED ERROR VTG(FROM COMPENSATOR> VI ; INPUT VTG FROM CURRENT FEEDBACK MODULE
CIC; IF CIC, CIC==l OTHERWIS~ CIC:.;Q
SCM; IF SCM, SCM=l OTHERWISE SCM=O
.TON ; CONSTANT ON TIME INTERVAL SLP; SLOP OF EXTERNAL RAMP
( IF EXT.RAMP NOT USED,SLP=O> VTH; THRESHOLD VOLTAGE ER; REFERNCE VOLTAGE OF OP.AMP
MACRO OUTPUTS:: VR VC G
* * VR; EXTERNAL RAMP VOLT~GE PLUS THRESHOLD VTG * VC; TOTAL CONTROL VOLTAGE * G; SWITCHING FUNCTION * <IF SWITCH=ON, 0=1) * (IF SWITCH=ONN,G=O) * TC; ON TIME INSTANT * TR; OFF TIME INSTANT MACRO CODE MACRO STOP SQRT **~·* * **** VC NN--= -VE NN---CICNN--*VI NN---
& SCMNN--t!-VI NN --****""* IF<TIME.GT.EPSJGOTO +-~+11
T=-TIME G NN·· -::-. J GOTO +t- c-?2
t-+-t-11 CONTINllE * *
IF<G NN--.GT. EPSNN-->THEN IF((TIME-TC>. GE. TONNN-->THEN TR=-TIME 0 NN-·-=O
END JF ELSE VR NN--=SLPNN--*(TIME-TR)+VTHNN--
IF<VR NN--. LE. VC NN--)THEN G NN--=1 TC=-TIME END If-
END IF +++22 CONTINUE
IF<IL NN--. GE. ILMNN--)G NN--=O ,i.
MACRO RESUME SORT END ClF MACRO MODEL DESCRIPTION LOCATION= 22, NN E.ND OF MODEL Ii-
112
PWM (SMALL-SIGNAL)
. . PW DH _
INPUT
VE variable voltage loop error
VI variable current loop error
FM parameter PWM gain
VJ parameter injection voltage
OUTPUT
HD variable duty ratio (dummy)
DH variable duty ratio
IQ variable switching function
EQUATIONS
HD= - FM* (CV* VE+ CI* VI)
DH= NN *HD+ MM* VJ
PVV
voltage Volts
voltage Volts
1/volts
Volts
Amps
113
0* PWM (SMALL SI~NAL) ***** ********************************** MACRO FILE NAML~MACROS l)E~f-=-I l')E: r~1/:;·:Cf-1Q::: F-' t,.J t1/\C F~' Ci I J\f;:1 ~Jl-S:~::
;vi,;\ C' r:{ tJ 1_-i t.J ··;. r1 l) _i _ ~-~1 ~_. .t.I;-1 i·tIJ
~:-\) ; I t--~ P l) T \} 7 ·-r:;: r=-F0! l] fVj C O i'1f r~ E !'.IS l'i "i C1l1 }'•·;[)I) t.J L. f"? ):~\) I j I f\!f1 t}l"" '-iT(;: i~:-r{[!}"''t c:.t}F:RE:J\}7 .. ··--L..OCtP r·t[}l)(_.J{ __ f:~ ~::-r: 1~ .. , : P t•Jt-·! (~r\ I j\J r-t.)._) j 1r·J\Jr:c·r1c1i\J l./CJL ·rt\~;r: r·I)~-f ; l)t}·ry· f-~c~'-f} Cl t:-i -:J) _\ 'f)i,)-r ~{ R l-\-f IO< I}t)rltl:-·{''{) 1\11\(:f-::CJ C:tJ-i)E i'-1/\CRlJ s-rOf 1 '.J[lf{"T fZ·
HD FH-··J:'.·(C\' pt,i-···tc\/E:. Fi/J-•-·+ :~,: C: J P !rJ----~-:~) I F1 !1J ~ .... )
DH PW--=NN PW--*HD PW--~MM PW--~V~ PW--************************ MACRO RESUME SORT END OF i'-1,\CRCJ MODEL DESCRIPTION LOCATION= 22, rw ;::ND DF MOD!.:.L
I
R-L-C LOAD
L
V
C
INPUT
Vl variable
RA parameter
RB parameter
L parameter
C parameter
TC parameter
OUTPUT
IL state variable
vc state variable
R variable
EQUATIONS
For TIME< TC
For TIME TC
R = RA
R = RB
• IL= ( Vl - VC) / L •
114
R
input bus voltage
resistance
resistance
inductance
capacitance
time for step change
inductor current
capacitor voltage
resistance
VC = ( IL - VC / R) / C
LO
I
Volts
Ohms
Ohms
Henries
Farads
seconds
Amps
Volts
Ohms
115
****************************~*** ******** LOAD MODE· L **-f.·******* ***************************** MACRO FILE NAME~MACROS DEFINE MACRO=,L.O MACRO INPUTS= V1 RA RB
* * Vt * RA * RB * TC * MACRO MACRO MACRO *
L C TC
INPUT VOLT~GECFROM POWER STAGE) RESISTOR VALUE DEFORE STEP CHANGE RESISTOR VALUE AFT~R STEP CHANGE TIME FOR SlEP CHANGE
OUTPUTS= IL VC R CODE STOP SORT R LO--: RA LO--· IFCTIME.GT.TC LO-->R LO--~RB LO--
*STATE EQUATION MACRO DERIVATIVE, IL LO--=(Vl LO-- - VC LO--)/L LO--MACRO DERIVATIVE,VC LO--~<IL LO-- - VC LO--/R LO--)/C LO--* MACRO RESUME SORT END OF MACRO MODEL DESCRIPTION LOCATION=25, LO END OF MODEL
116
CONSTANT POWER LOAD PT
... __ P_T __ : __ I_L_>
INPUT
VL variable input bus voltage Volts
PW1,PW2 parameters constant power values Watts PWO
PC parameter if PC=l, const. power if PC=O, time varying power if PC=2, time varying power
VR parameter minimum voltage to Volts maintain const.power
SW parameter slope of time varying power Watts/sec
OUTPUT
IL variable load current Amps
PW variable load power Watts
EQUATIONS
For PC = 1 : For PC = 2 :
PW = PWl ( IF TIME < TC ) PW = PWl ( SW* TIME ) PW = PW2 ( IF TIME>- TC ) PW = PW2 ( IF PW~ PW2 )
For PC = 0 :
PW = SW* TIME+ PWO
117
MACRO FILE Nf\t•ff· == MACr-.<OS ********************************~************************ T>EF INE MACRO :· fJ"I * LOAD MODl-: L * INrUT IS BUS VOLTAGE <VL) AND POWER <PW) OUTPUT IS !(LOAD> * **** FOR SlEP POWER CHANGE I PC PT= 1. **** FOR RAMP CHANGE OF POWER I PC PT ==O. OR 2. * PC PT= 0: PW= SW* TIME+- PWO * PC PT= 2: PW= PW1 - <SW* TIME) MACRO INPUTS= VL
vr~ MACRO OUTPUTS~ IL MACRO CODE MACRO STOP SORT
PO TC PW
Pl-ll SW SL
PW2
IF < PC PT -- . EG. 1. ) GO TO +H-23 IF ( PC PT--. EG. 2. >GOTO +++43 PW PT--= SW PT--*TIME PWOPl--IL PT-·· ::,;. PW Pl-- / VL p·1 -·-GOTO ++-:33
* STEP CHANGE OF POWER AT TIME= TC PT -i-++23 CONTINUE
PW P1-·-=PW1PT--IFCTIME. GE. TC PT-->PW PT--::.;.PW2PT--IL PT--~ PW p·1 -- / VL PT--
PC
+(·+33 SL PT-- =· FW PT-- /VH PT·--/VR PT--IF CVL PT--- . LT. VR PT--) IL PT-- -- SL PT--*VL PT--IF< IL PT-- . LT. 0. > IL PT -- :: 0. GO TO t-+- 1-~,3
* RAMP CHANGE Of POWER FFOM PW1PT TO PW2PT WITH THE SLOPE * OF SW PT CWJ PER SECON[ +++43 PW PT--; PWJPT-- - < SW PT--* lIME )
IF < PW PT··- . LT. P~2PT-- > PW PT--=-= PW2PT--IL PT--::.;. PW PT--/ VL PT--SL PT-- ::,;. rw Pl -- / VR f-'T -·- / VR PT-·-IF ( ILPT--.LT. 0.) JLPl--=O.
* DUMMY STATEMENT +-++53 PW PT --- =- PW Pl -·-MACRO RESUME SO:<l E.ND OF MACRO ************·~*************'**************************** MODEL DESCRIPTION LOCATION=42, Pl END OF MODEL Pf<lNT
APPENDIX II
Procedure of EASY5 Programming
In this section, one example of a switching regulator
system is modeled and simulated to show users how to apply
the macro component models. In addition, the general proce-
dures of system-level modeling and simulation are briefly
explained. The EASYS commands used in this example are the
commands used in an interactive mode.
Step 1. Write Model Description Statements
Once required component models and their interconnections
are identified, appropriate macro components and/or standard
components are collected from the macro component model li-
brary and the EASYS standard component library.
As shown in Fig.A.l, the EASYS system model[BUCKCF.MOD]
can be described with simple mnemonic statements. The LO-
CATION command phrase indicates the start of a new component
in the system model. This command must be followed by a nu-
meric value phrase that specifies the location of the compo-
nent on the model schematic. In the example of Fig.A.l, the
location number of the Buck power stage [BC] is 12 and the
load [LO] is 17, etc. The location number phrase is followed
by the name of the component at that location. A LOCATION
statement must be given only once for each statement.
118
119
*** BUCK LARGE SIGNAL(MODULAR APPROACH) ***************************************** ** REVISED 2/4/86 MACRO FILE NAME=MACHOS . ·*LI ST M,qCRD COl"IPONENTS=c 0 BC, LO, FF, SM, MP MODEL DESCRIPTION -LOCATION=12,BC, LClC,-\TJON:::: 1 7, LO, I NPUTS=BC ( V2" 0-V 1) LOCAfION=34,SM, INPUTS=BC<VL=VL) LOCATION=36,MP, INPUTS=BC(V2=VO) LOCATION=43,rF, INPUTS=SM(VI~VIl,MPCVE~VEl,BCCIL=IL> END OF MODEL PRINT
Figure A.l Model Description [BUCKCF.MOD]
120
This means that once a LOCATION statement is started for a
component, the complete description of that component must
be given. The location of each component model should be
arranged so that the interconnections among the components
can be clearly visualized in the EASYS Model Generation pro-
gram generated schematic diagram. Each component model is
described with an 'INPUTS' phrase. The input component name
must be supplemented by the name of the particular output
quantity that is to provide the input. As an example, con-
sider the load component [LO] in Fig. A. 1 Since the output
voltage (V2) of the buck-converter power stage [BC] is to be
the input voltage (Vl) to the load component, the following
statement indicates to the program that the output of [BC],
V2, is to be used as the input to the ·load component, [LO]:
LOCATION=lO, LO, INPUTS=BC(V2=Vl)
The input and output connections between the component models
are made by using the port variables shown with the right and
left side arrow of the box in the input-output list of each
component model. In model connection an 'implicit loop'
should always be avoided. The 'implicit loop' is formed
whenever the blocks are connected with all non-state vari-
ables and the connection comprises a loop. If a system con-
sists of an implicit loop, the Model Generation program will
not generate a model, instead, it will give the error message
showing where in the system an implicit loop occurs.
121
Step 2. Run the EASY5 Model Generation Program
Whenever a new macro component model is developed, the
macro model should be compiled and linked by the EASYS model
generation program using the command as follows:
EASYS BC BC.MOD
Once the macro component model is compiled and linked, the
executable file for the model is stored in the user's perma-
nent file 'MACROS. DAT' for subsequent use. After all the
component models are compiled and linked, the system model
[BUCKCF.MOD] should be also compiled and linked by the EASYS
Model Generation program. With the file 'BUCKCF. MOD' , the
EASYS Model Generation program will make all the connections
between the component blocks according to the Model De-
script~on data. The command for the EASYS Model Generation
program is as follows:
EASYS BUCKCF BUCKCF.MOD
With the above command, the EASYS program creates a new file,
'BUCKCF.MGL', which contains a FORTRAN listing of component
model programs, a schematic diagram (Fig.A.2) and input data
requirements list (Fig.A.3).
2
·k ·!c· tH-'.· * l"i-·I<· IHH~ -1:c -,-:
4 7
·IH(--1<··~ -~:-l:,•-JH-Hi-E· 1-:· t:-
li· HC +~ 1:- LO l~ 12 *<===:====·======== ·====================~==============>« 17 * *===r==>=-==========>====~===-~~==~~~==========> *
**~******* IL LOI =12 I I *******k** A l I I J G FF 11 I I J I I I l 1 l I
~? 1 I ;;i~-l I ;!4 ;:-'.~; I ;;?t-:, ;;_tJ I I I I 1 IVL BC :0 VL. :t V~? BC ::c.lJO I I I V V I I ********** ********** l I ·fr 11- -1:; , . .-l J . •t:- f;M 1~ {t· i'"iP -le
:u r~:·:( H· ~=M t;- ::: 5 i.:- :1 c-, i.• :·:r1 1 J ·I;" -r.- ~- fi-
1 l H C ::-o; l L J •f.d~ tt"«--~, 1i· *·lHHf -J(·*-!-HHHHHH,·* I V l I I ********** VJ SM =VI I I j:'" ~:- vr-:: MP 1 :.: \IL:. I ~====~==* ~F *<==~=======================~=====
l!-;;:., J;;· 4 ::1 , K· 4 4 l! ~; 4 6 .1! 7 -t: ·!f· ·/H:E--i>i I::· tf f"i:•l-, .. !-,··ls·
Figure A.2 System Configuration Diagram . [ BUCKCF . MGL]
N N
L.D
LU
NV SN C SM
0ARAMETERS REQUIRED
L BC HB L.D
R EM IA. MP SCl'IF:r: f:3L l'-'FF
BC L 0
1/ 1 BC
C LU
s·1·1\TES (INITIAL CONDITIONS AND ERROR CONTROLS REGUIRCD) SlATE NAME (AND DIMENSION DATA FOR VECTOR AND MA'l'RIX STAl'ES)
IL nc J. L.. LD
vc nc
Figure A.3 Input Data R~quirements List [BUCKCF.MGL]
,-.... N w
124
Step 3. Write and Run Analysis Program
In order to conduct a specific analysis, parameter values,
initial conditions and any other necessary data in the input
data requirements list must be supplied. Integration con-
trols, output data formats and variable names for plot are
specified as needed.
given in Fig.A.4.
The analysis program of the system is
The command for running the analysis program is
EASYS BUCKCF * BUCKCF.ANC
With this command, the EASYS creates new files such as
BUCKCF.APL, BUCKCF.PPT and BUCKCF.RPD.
~:=:-:·-if::\/:[ SE1) i /.;2.:1 /CJ{:, 0~uc (POWER SlA(~) JJ·•.1I1"I/\L_ co~\i})l .. t Il1f\J:3 !L Bc~10,vc BG~20 PARAMETER VALU~S
125
·-·- fi (: ::·2 5C)E ·-6) c: PC;:~-.,;f.(J()F- ··-•f::.., RL BC=lE-2,RC 0C~ JE-2 \i J. BC:::.:2f3 ~~0CG LOOP COMPENSATER :.~.. iv! P :-.=: • 3 , ER i\1 r-J : ... (-;;A i\:!p = 1~-A-f-38, tNi'\ f-·tfJ;::.:(• 2~3; liJB t!:r::::: :l [~ ~} ~* CURRENT 01V SM~. 08,C SM~7. 275E-9,R SM~3. 44E3 r- F i.~•t(·j :::2:1_r · r:F· ::.::() .#c \/·r: ?r-:· r=-=-. s FR F~~6,CICFF=O,SCMFF~J J L.i'TiF·::::::~: l ~l
r• ~-;. L.Clt\I) RA L0=2,RB 2,TC L_ L~Ct~~; :1. E>-6 > (~ L tJ~--l C: ... ;:; .[ i'--i I ~r 11£\l,_ C CJ!\H) I -l l CH\fS \} t-1 P ::::: () JL
· F1n Ii'-1.!.TER f'L.tJT·:; ONi ... INE PLOTS :r t-i·r rio1~;r:·:;:::L} 1~-L"'J I Sf·::, L~ t\ '( 1
r:-11. BC I) I SP i_/~ \i Lt, ( Q~./ E: f~ i:1 L_ Ci"\ )
i-:·;v'H r-~F, \JC FF TMAX=1OE-3,TINC~5E-7 PRATE=200,0UTRATE~20 *PRATE=100,0UTRAlE~4
Figure A.4 Analysis Input Program [BUCKCF.ANC]
126
Step 4. Analyze the results
The printed data of various variables and parameter values
at a specified time interval are found in BUCKCF.APL. The
plotting data for a line printer is in BUCKCF. PPT, and
BUCKCF.RPD contains a plotting data for a graphics terminal.
The simulation result are drawn from the data in BUCKCF.RPD.
REFERENCES
1. F. C. Lee, Yuan Yu, "Computer-Aided Analysis and Simu-lation of Switched DC-DC Converters," IEEE Trans. on In-dustry Appliction Vol.IA-15 No.5 Sep./0ct. 1979
2. B. H. Cho, F. C. Lee, "Modeling and Analysis of Spacecraft Power Systems," IEEE PESC Record, June 1985
3. Boeing Computer Services, 11EASY5 Dynamics Analysis System User's Guide," 1983
4. B. H. Cho, "Modeling and Analysis of Spacecraft Power Systems," Ph.D. Dissertation, 1985, VPI & SU
5. R. D. Middlebrook, S. Cuk, "A General Modified Approach to Modeli~g Switching Regulator Power Stages," IEEE PESC Record, J~•~e 1976
6. F. C. Lee, Yuan Yu, "Application Handbook for Standard-ized Control Module for . DC to DC Converters," NASA Re-port, NASA CR-165172, Vol. I, Apr. 1980
7. F. C. Lee, et al. "Modeling and Analysis of Power Proc-essing Systems," NASA Report, NASA CR-165538, Vol. I, Dec. 1980
8. S. Kim, J. Lee, B. Cho and F. C. Lee, "Computer-Aided Modeling and Analysis of Power Processing Systems," NASA Report, NAG5-518, Vol. I, May 1986
9. S. Kirn, J. Lee, B. Cho and F. C. Lee, "Computer-Aided Modeling and Analysis of Power Processing Systems," NASA Report, NAG5-519, Vol. II (User's Handbook), May 1986
127
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