computer-aided digital system design vhdlalum.sharif.ir/~rajaei/lec4.pdf · modeling styles 3...

VHDL

Ramin Rajaei

[email protected]

Computer-Aided Digital System Design

بسم اهلل الرحمن الرحیم

Iran University of Science and Technology Department of Computer Engineering

Modeling Styles

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From the level of abstraction systems can be described in there types:

1. Behavioral

2. Dataflow

3. Structural

© Dr. Ramin Rajaei, CAD

VHDL Hierarchy

Modeling Styles

3

Sequential vs. Concurrent Statements

VHDL provides two different types of execution: sequential and concurrent.

Different types of execution are useful for modeling of real hardware.

Supports various levels of abstraction.

Sequential statements view hardware from a “programmer” approach.

Concurrent statements are order-independent and asynchronous.


Examples for Architecture Declaration

4 © Dr. Ramin Rajaei, CAD

Sequential (behavioral) Style Data flow Style

Structural Style

Behavioral

© Dr. Ramin Rajaei, CAD 5

We can describe a system in terms of processing it performs on its input signals and the type of output it signals it produces.

Example :

LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY eq_comp4 is PORT( a,b : in std_logic_vector(3 downto 0); equals : out std_logic); END ; ARCHITECTURE behvioral OF eq_comp4 IS BEGIN comp: PROCESS (a,b) BEGIN IF (a=b) then equals <= '1'; Else equals <= '0'; END IF; END PROCESS comp; END behvioral;

Data Flow


Dataflow architecture specifies how data will be transferred from signal to signal and input to input without the sequential statements.

Primary difference is that behavioral uses processes while dataflow does not.

The other main difference between dataflow and behavioral architectures is that the body of the process statement contains only sequential statements.

Example: library ieee; use ieee.std_logic_1164.all; entity eq_comp4 is port ( a,b : in std_logic_vector(3 downto 0); equals : out std_logic); end eq_comp4; architecture bool of eq_comp4 is begin equals <= not (a(0) xor b(0)) and not (a(1) xor b(1)) and not (a(2) xor b(2)) and not (a(3) xor b(3)); end bool;

Structural


One way to describe a system is to describe component chips and the interconnections assuming that the user is familiar with it.

This kind of definition is the structural definition.

library ieee; use ieee.std_logic_1164.all; entity full_adder is port( a,b,ci : in std_logic; sum,co : out std_logic); end full_adder; architecture bool of full_adder is signal s1,s2,s3 : std_ulogic; begin u0: s1 <= (a xor b); u1: s2 <= (ci and s1); u2: s3 <= (a and b); u3: sum <= (s1 xor ci); u4 : co <= (s2 or s3); end bool;

Example:

What circuit this architecture means?

Standard VHDL operators

Logical - defined for type BIT

AND, NAND OR, NOR XOR, XNOR NOT

Relational - defined for types BIT, BIT_VECTOR, INTEGER = (equal to) =/ (not equal to) < (less than) <= (less than or equal to) > (greater than) >= (greater than or equal to)


Standard VHDL operators

Unary Arithmetic - defined for type INTEGER

- (arithmetic negate)

Arithmetic - defined for type INTEGER

+ (addition)

- (subtraction)

Concatenation - defined for types STRING,

BIT, BIT_VECTOR

&


Concurrency


Sequential Style Syntax


Assignments are executed sequentially inside processes.

A D-Flip Flop


CLK

D Q

DFF CLEAR

Sequential Statements

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• {Signal, Variable} assignments

• Flow control

• if <condition> then <statments>

[elsif <condition> then <statments>]

else <statements>

end if;

• for <range> loop <statments> end loop;

• while <condition> loop <statments> end loop;

• case <condition> is

when <value> => <statements>;

when <value> => <statements>;

when others => <statements>;

• Wait on <signal> until <expression> for <time>;


Data Objects

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• There are three types of data objects:

• Signals

• Can be considered as wires in a schematic.

• Can have current value and future values.

• Variables and Constants

• Used to model the behavior of a circuit.

• Used in processes, procedures and functions.


Signal Declaration and Assignment


Signals are used for communication between components.

Signals are declared outside the process.

Signals can be seen as real, physical signals.

Some delay must be incurred in a signal assignment.

A key difference between variables and signals is the assignment delay.

Variable Declaration and Assignment

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Variables are used for local storage of data.

Variables are generally not available to multiple components or processes.

All variable assignments take place immediately.

Variables are more convenient than signals for the storage of (temporary) data.


Constant Declaration


A constant can have a single value of a given type.

A constant’s value cannot be changed during the simulation.

Constants declared at the start of an architecture can be used anywhere in the architecture.

Constants declared in a process can only be used inside the specific process.

CONSTANT constant_name : type_name [ : = value]; CONSTANT rise_fall_time : TIME : = 2 ns; CONSTANT data_bus : INTEGER : = 16;

Signals vs. Variables


Variable is used when you want to create a serialized code, unlike the normal parallel code.

A variable, can exist only inside a process, and the assignment of values is not parallel. For example, the fallowing code:



entity sig_var is port (In1: in std_logic; In2: in std_logic; out1: out std_logic); end sig_var;

architecture Behavioral of sig_var is begin process(In1, In2) variable a, b: std_logic; begin a := In1 and In2; b := a and In2; out1 <= b and In2; end process; end Behavioral;




architecture Behavioral of sig_var is signal a, b: std_logic; begin process(In1, In2) begin a <= In1 and In2; b <= a and In2; out1 <= b and In2; end process; end Behavioral;




architecture Behavioral of sig_var is signal a, b: std_logic; begin a <= In1 and In2; b <= a and In2; out1 <= b and In2; end Behavioral;

Signal vs Variable: synthesis


entity sig_var is port (clk: in std_logic; Din: in std_logic_vector (3 downto 0); out1: out std_logic_vector (3 downto 0)); end sig_var;

architecture Behavioral of sig_var is signal a, b: std_logic_vector (3 downto 0); begin process(clk) begin if (rising_edge(clk)) then a <= Din; b <= a; end if; end process; out1 <= b; end Behavioral;

Signal vs Variable: synthesis


entity sig_var is port (clk: in std_logic; Din: in std_logic_vector (3 downto 0); out1: out std_logic_vector (3 downto 0)); end sig_var;

architecture Behavioral of sig_var is signal a, b: std_logic_vector (3 downto 0); begin process(clk) begin if (rising_edge(clk)) then a <= Din; b <= a; out1 <= b; end if; end process; end Behavioral;

IF – vs. CASE – statement Syntax


FOR – vs. WHILE – statement Syntax


For is considered to be a combinational circuit by some synthesis tools. Thus, it cannot have a wait statement to be synthesized.

While is considered to be an FSM by some synthesis tools. Thus, it needs a wait statement to be synthesized.

WAIT – statement Syntax


• The wait statement causes the suspension of a process statement or a procedure.

• wait [sensitivity_clause] [condition_clause] [timeout_clause];

• Sensitivity_clause ::= on signal_name

wait on CLOCK;

• Condition_clause ::= until boolean_expression

wait until Clock = ‘1’;

• Timeout_clause ::= for time_expression

wait for 150 ns;

wait until clk’event and clk= ‘1’;

wait until rising_edge(clk);

Sensitivity-lists vs Wait-on - statement


Example


entity process_example is Port ( clk : in STD_LOGIC; D1, D2: in std_logic; reset: in std_logic; out1 : out STD_LOGIC; out2 : out STD_LOGIC); end process_example; architecture Behavioral of process_example is begin process begin if reset = '1' then out1 <= '0'; else out1 <= D1; end if; if rising_edge(clk) then out2 <= D2; end if; end process; end Behavioral;

Example (cont.)


entity process_example is Port ( clk : in STD_LOGIC; D1, D2: in std_logic; reset: in std_logic; out1 : out STD_LOGIC; out2 : out STD_LOGIC); end process_example; architecture Behavioral of process_example is begin process begin wait until rising_edge (clk); if reset = '1' then out1 <= '0'; else out1 <= D1; end if; out2 <= D2; end process; end Behavioral;

Example (cont.)


Error message: line 36: Bad condition in wait statement, or only one clock per process.

Concurrent Process Equivalents


• All concurrent statements correspond to a process equivalent.

U0: q <= a xor b after 5 ns;

is short hand notation for

U0: process

begin

q <= a xor b after 5 ns;

wait on a, b;

end process;

Structural Statements


The component instantiation is one of the building blocks of structural descriptions.

The component instantiation process requires component declarations and component instantiation statements.

Component instantiation declares the interface of the components used in the architecture.

At instantiation, only the interface is visible. The internals of the component are hidden.

Component Declaration and Instantiation

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• The component declaration declares the interface of the component to the architecture.

• Necessary if the component interface is not declared elsewhere (package, library).

The instantiation statement maps the interface of the component to other objects in the architecture.


Component Instantiation Syntax

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• The instantiation has 3 key parts

• Name

• Component type

• Port map


Examples:


architecture first of add4 is begin s <= a + b; -- works with std_logic_vector or integer end; architecture second of add4 is signal c: std_logic_vector(2 downto 0); begin s(0) <= a(0) XOR b(0); c(0) <= a(0) AND b(0); s(1) <= a(1) XOR (b(1) XOR c(0)); c(1) <= ….. end add4;

Example: n-bit Comparator


library ieee;

use ieee.std_logic_1164.all

entity Comparator is

port( A: in std_logic_vector(1 downto 0);

B: in std_logic_vector(1 downto 0);

less: out std_logic;

equal: out std_logic;

greater: out std_logic );

end Comparator;

architecture behv of Comparator is Begin process(A,B) Begin if (A<B) then less <= '1'; equal <= '0'; greater <= '0'; elsif (A=B) then less <= '0'; equal <= '1'; greater <= '0'; else less <= '0'; equal <= '0'; greater <= '1'; end if; end process; end behv;

More Examples for Review


Example:


Synthesis Result


Example:


entity reg4 is port (clk, clr : in bit; d : in bit_vector(0 to 3); q : out bit_vector(0 to 3); end entity reg4; architecture struct of reg4 is component flipflop is generic (Tprop, Tsetup, Thold : delay_length); port ( clk, clr, d : in bit; q : out bit); end component flipflop; begin bit0: component flipflop generic map ( Tprop => 2 ns, Tsetup => 2ns, Thold => 1ns) port map ( clk => clk, clr => clr, d => d(0), q => q(0) ); bit1: component flipflop generic map ( Tprop => 2 ns, Tsetup => 2ns, Thold => 1ns) port map ( clk => clk, clr => clr, d => d(1), q => q(1) ); bit2: component flipflop generic map ( Tprop => 2 ns, Tsetup => 2ns, Thold => 1ns) port map ( clk => clk, clr => clr, d => d(2), q => q(2) ); bit3: component flipflop generic map ( Tprop => 2 ns, Tsetup => 2ns, Thold => 1ns) port map ( clk => clk, clr => clr, d => d(3), q => q(3) ); end architecture struct;

Example: Array of AND-gates


Next Sessions:


In Lec-5, we will have a tutorial for Modelsim.

And also

Exercise 2

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