lec4 decoder

7/31/2019 Lec4 Decoder

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Any logic circuits can be transformed to an

implementation where only NAND gates (and inverters)

are used.

The general approach to finding a NAND-gate

realization: Use DeMorgans theorem to eliminate all the

OR operations.

NAND-ONLY LOGIC CIRCUITS


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(Example)

F = A + B (C + D)

= A + B (CD)

Note that (CD) = C + D and (AX) = A + X

F = (A (B (CD)))

Now there is no OR operation in the Booleanexpression. Note that

A NAND B = (AB)

NAND-ONLY LOGIC CIRCUITS


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F= (A (B (CD)))

The logic circuit for this function is given by:

We can also use the same procedure to do NOR only gates.


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Ch2. Decoder

Dr. Bernard Chen Ph.D.

University of Central ArkansasSpring 2009


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Integrated Circuits An integrated circuit is a piece (also called

a chip) of silicon on which multiple gates or

transistors have been embedded

These silicon pieces are mounted on a plasticor ceramic package with pins along the edgesthat can be soldered onto circuit boards orinserted into appropriate sockets


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Integrated Circuits

SSI, MSI, LSI: They perform small tasks such as addition offewbits. small memories, small processors

VLSI Tasks: - Large memory - Complex microprocessors, CPUs


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An SSI chip contains

independent NAND gates


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Examples of Combinational

Circuits a) Decoders

b) Encoders

c) Multiplexers

d) Demultiplexers


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Decoder Accepts a value and decodes it

Output corresponds to value ofn inputs

Consists of:

Inputs (n)

Outputs (2n , numbered from 0 2n - 1)

Selectors / Enable (active high or active low)


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The truth table of 2-to-4

Decoder


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2-to-4 Decoder


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2-to-4 Decoder


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The truth table of 3-to-8

DecoderA2 A1 A0 D0 D1 D2 D3 D4 D5 D6 D7

0 0 0 1

0 0 1 10 1 0 1

0 1 1 1

1 0 0 1

1 0 1 1

1 1 0 1

1 1 1 1


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3-to-8 Decoder


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3-to-8 Decoder with Enable


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2-to-4 Decoder: NANDimplementation

Decoder is enabled when E=0 and an output is active ifit is 0


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2-4 Decoder with 2-input andEnable


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Decoder Expansion

Decoder expansion

Combine two or more small decoders with

enable inputs to form a larger decoder

3-to-8-line decoder constructed from two2-to-4-line decoders The MSB is connected to the enable inputs if A2=0, upper is enabled; if A2=1, lower is

enabled.


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Decoder Expansion


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Combining two 2-4 decoders to formone 3-8 decoder using enable switch

The highest bit is used for the enables


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Combinational Circuit Design withDecoders

Combinational circuit implementation withdecoders

A decoder provide 2n minterms of n inputvariables

Since any Boolean function can beexpressed as a sum of minterms, one canuse a decoder and external OR gates toimplement any combinational function.


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Combinational Circuit Design withDecoders

Example Realize F (X,Y,Z) = (1, 4, 7) with a decoder:

lec4 decoder

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