competitive solutions dx0120. nature of assignment retained by ftc counsel spring 2002 conduct...

Competitive SolutionsCompetitive Solutions

DX0120

Nature of AssignmentNature of Assignment

Retained by FTC counsel Spring 2002

Conduct economic analysis of Rambus’s alleged actions

Analyze competitive nature of Rambus’s alleged conduct

Determine competitive effects or potential effects of such conduct

Determine appropriate remedies

DX0121

Understanding of FTC AllegationsUnderstanding of FTC Allegations

Subversion of open standard process (JEDEC) through non-disclosure of IP and related misrepresentations

Industry adoption of JEDEC standards embodying claimed Rambus IP

Subsequent enforcement of Rambus IP against JEDEC-compliant DRAM

Rambus’s conduct eliminated alternative technologies that, before the standards were issued, were commercially viable

Harm to competition in / monopolization of DRAM technology markets

DX0122

Key Economic QuestionsKey Economic Questions

1. What are the relevant antitrust markets?

2. Does Rambus possess substantial market / monopoly power in such markets?

3. Did Rambus acquire market / monopoly power through exclusionary conduct?

4. Has Rambus’s conduct resulted in anticompetitive harm (actual or threatened)?

5. What remedy (if any) is needed to restore competition / alleviate the anticompetitive effects of Rambus’s conduct?

DX0123

Interviews ConductedInterviews Conducted

DRAM engineers

DRAM plant managers

JEDEC participants

DRAM users

DX0124

Materials Reviewed / Relied Upon Materials Reviewed / Relied Upon

Business records from Rambus and third parties

Minutes and presentation materials from JEDEC

meetings

Relevant deposition / trial testimony

Reports of FTC / Rambus experts

Relevant economics literature

Literature on DRAM and semiconductor industries

Publicly available trade press, analyst reports, and

company sources

DX0125

Case StudyCase Study

Methodology: Comprehensive review of public /

private reports and information Focus: evolution of DRAM standards / technologies

Time period: 1990 to present

Information sources: publicly available materials,

trade press, analyst reports, discovery materials

Purpose: assessing economic factors influencing

choices among alternative DRAM technologies /

standards

DX0126

Summary of ConclusionsSummary of Conclusions


Conclusions:

Four relevant technology markets

Each consists of commercially viable alternatives for addressing specific DRAM design issues

Each market is world-wide in scope

The four markets can be viewed together as a single “cluster market”

DX0127



Conclusions:

Rambus possesses monopoly power in each of the relevant technology markets

Rambus’s monopoly power stems from the use of its patented technologies in the dominant world-wide DRAM technology standards (i.e., JEDEC’s SDRAM and DDR-SDRAM standards)

DX0128



Conclusions:

Rambus’s challenged conduct is “exclusionary” in that it

Distorted an open competitive process by concealing (or misrepresenting) material information

Excluded equally efficient or superior alternative technologies

Entailed a conscious choice to jeopardize the enforceability of patented intellectual property

By distorting JEDEC’s standardization process, Rambus’s exclusionary conduct enabled it to obtain monopoly power

DX0129



Conclusions:

Rambus’s conduct has caused significant anticompetitive harm by

substantially increasing prices (royalties) in the relevant technology markets

creating other actual / threatened distortions to competition in those markets (e.g., harm to innovation)

threatening to increase prices in downstream DRAM product markets

undermining confidence in open standards / standards processes

DX0130



Conclusions:

Rambus should be prohibited from enforcing against JEDEC-compliant DRAMs any patents filed (or based on filings) prior to June 18, 1996

This remedy should extend both to US and foreign patents

This remedy will restore competitive pricing in the relevant technology markets and mitigate other anticompetitive effects

DX0131

DRAM Industry OverviewDRAM Industry Overview

Technology Providers(e.g., Rambus, Jazio)

Consumers

DRAM Manufacturers

(e.g., Samsung, Micron)

Manufacturers ofDRAM-Related Logic

(e.g., Intel, AMD, ATI)

PC-OEMs, Server OEMs and other firms using DRAM(e.g., Dell, Gateway, HP, Cicso)

Technology

DRAM Chipsets, Graphics Cards

DRAM Upgrades Graphics Cards Upgrades

DX0132

DRAM BuyersDRAM Buyers

Personal Computers(62%)

Memory Modules(19%)

Workstation (5%)

Other: Printers, Routers, Facsimile... (4%)

Entry-level servers (4%)

Industrial & Additional Motherboards (3%)

Supercomputer,Mainframe, Midrange

(3%)

Percentage of DRAM Purchases, By Platform

Source: Gartner Dataquest, DRAM Supply/Demand Quarterly Statistics: Second Quarter 2000 Outlook, Bates No. HR905_06733 (August 14, 2000).

DX0133

Basic Economics of DRAM IndustryBasic Economics of DRAM Industry

Large capital requirements Economies of scale Interoperability Price sensitivity Commodity nature of DRAM

DX0134

High Cost of DRAM Fabrication PlantsHigh Cost of DRAM Fabrication Plants

DX0135

DRAM Chip Manufacturers TodayDRAM Chip Manufacturers Today

DX0136

DRAM Chip Manufacturers in the PastDRAM Chip Manufacturers in the Past

DX0137

Economics of DRAM ProductionEconomics of DRAM Production

High fixed costs Volatility / cyclicality Intense price competition Maximize capacity utilization / yield Intense cost cutting

DX0138

Reducing DRAM Production Reducing DRAM Production Costs / Increasing YieldsCosts / Increasing Yields

24/7 operation Clean rooms Extended equipment life Optimized production process Die shrinks Larger wafer size

DX0139

Economics of DRAM DemandEconomics of DRAM Demand

Multiple sourcing Long lead times Backwards compatibility Minimizing cost per bit Minimizing design, testing, and qualification

costs

DX0140

Evolution of DRAM StandardsEvolution of DRAM Standards

0

20

40

60

80

100

1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005

Other FPM EDO SDRAM DDR RDRAM

Source: Cahners In-Stat “DRAM Memory Primer 2000” March 2000, Page 57 and In-Stat MDR “DRAM Market Forecast – Is there life After PCs” July 2002, Page 75 DX0141

Importance of Standards in Importance of Standards in DRAM IndustryDRAM Industry

Interoperability Diversity of use Common product design – DRAM producers Compatible design – DRAM users Facilitates price competition

DX0142

Nature of DRAM StandardsNature of DRAM Standards

Basic design specifications / protocols Focus on interface Parametrics Module standards

DX0143

How DRAM Standards Are SetHow DRAM Standards Are Set

Standard-setting organizations Private consortia Proprietary standards

DX0144

Economic Factors Influencing Success of Economic Factors Influencing Success of DRAM StandardsDRAM Standards

Open, consensus-based process Open availability of standard Royalties Implementation costs Manufacturing costs Evolutionary / revolutionary

DX0145

Economic Underpinnings of Economic Underpinnings of Evolutionary / RevolutionaryEvolutionary / Revolutionary

Reuse of existing knowledge / infrastructure Increasing marginal cost of changes Debugging / testing System-level design Risk

DX0146

JEDEC’s ProcessJEDEC’s Process

Diverse views / preferences Choice among alternatives Need for consensus Time to market Cost / performance considerations IP considerations “Satisficing”

DX0147

Problem of Hold-UpProblem of Hold-Up

“The hold-up problem arises because investmentsthat are specific to another party are vulnerable inrenegotiation – the other party can extract some or all of the value of the investments. The value of specific assets – those specific to a relationship with another party – are vulnerable to expropriation by that other party, because the assets have low or no value without the other party’s participation.”

P. McAfee. Competitive Solutions: The Strategist’s Toolkit (Princeton University Press, 2002, p. 365)

DX0148

Example of Specific InvestmentExample of Specific Investment

Potential Fuel Sources

• Coal

• Natural Gas

• Nuclear

• Solar

• Hydro

Power Plant Design

Ex Ante: Multiple Commercially Viable Fuel Sources

DX0149


Potential Fuel Sources

• Coal

• Natural Gas

• Nuclear

• Solar

• Hydro

Power Plant Design

Ex Post: One Fuel Source

DX0150


Mine 1 Mine 2

Mine 3Mine 4

Mine 5

DX0151


Mine 1 Mine 2

Mine 3Mine 4

Mine 5$17/ton

$10/ton

$15/ton

$12/ton

$20/ton

DX0152

Example of Lock-InExample of Lock-In

Power Plant Locates Near Mine 1

Mine 1$10/ton

DX0153

Example of Hold-UpExample of Hold-Up

Power Plant Signs Coal Contract After Building

Mine 1

$20/ton

$10/ton

DX0154

Avoiding Hold-UpAvoiding Hold-Up

Power Plant Signs Coal Contract Before Building

Mine 1$10/ton

DX0155

Economic Literature on Hold-UpEconomic Literature on Hold-Up

Sanford Grossman and Oliver Hart, “The Costs and Benefits of Ownership: A Theory of Vertical and Lateral Integration,” Journal of Political Economy (1986)

Oliver Williamson, Markets and Hierarchy (Free Press, 1975)

Benjamin Klein, “Hold-Up Problem,” The New Palgrave Dictionary of Economics and the Law (Stockton Press, 1998)

DX0156

Application of Hold-Up to Application of Hold-Up to Standard SettingStandard Setting

Risk of hold-up depends upon characteristics of underlying industry / standards organization

Size of specific investments Cost of changing standards Importance of IP Ease of reaching agreement

DX0157

Application of Hold-Up to Application of Hold-Up to Standard SettingStandard Setting

Mechanisms for mitigating risk of hold-up ex ante

IP disclosure commitments

IP licensing commitments (e.g., RAND)

IP searches

DX0158

JEDEC: IP DisclosureJEDEC: IP Disclosure

Preference to avoid patents Early disclosure / good faith Disclosure applies to patents / patent

applications relevant to JEDEC standards / work RAND: mandatory for JEDEC; voluntary for

members Valid technical justification

DX0159

Application of Hold-Up to DRAM Application of Hold-Up to DRAM Standard SettingStandard Setting

Size of specific investments Substantial

Cost of changing standards Switching costs

Importance of IP High

Ease of reaching agreement Difficult and time consuming

DX0160

Standard Setting ProcessStandard Setting Process

A - C = Design / Technology Options

A

B

C

Standard Setting Process

DX0161

A

B

C

D

E

F

G

H

I


Standard Setting ProcessStandard Setting Process

Feature 1

Feature 2

Feature 3

B, F, G

DX0162

A

C

Standard Setting ProcessB

DEF

Value of C

$

Standardization Confers ValueStandardization Confers Value

DX0163


plant desig

n

compatibility

interoperability

manufacturing

$ $ $

Ex Ante Ex Post

time

Industry Commitment to DRAM StandardIndustry Commitment to DRAM Standard

DX0164

Standard Setting Process $ $ $

Ex Ante Ex Post

time

Ex AnteEx Ante Disclosure of IP Disclosure of IP

DX0165

C

A

A

C

Absent Patent Disclosure With Patent Disclosure

Ex AnteEx Ante IP Disclosure Can Alter the IP Disclosure Can Alter the Standard-Setting OutcomeStandard-Setting Outcome

DX0166

A

B Standard Setting Process

C

Optimal Choice Made with Full Optimal Choice Made with Full Information Early in the ProcessInformation Early in the Process

Ex Ante Disclosure of IP Rights

DX0167

A

C

Standard Setting ProcessB

Early Disclosure Leaves “Work-Around” Early Disclosure Leaves “Work-Around” Option Open Option Open

AC

C

A

DX0168


Ex Ante Ex Post

time

Ex Post Ex Post Disclosure of IPDisclosure of IP

DX0169


Ex Ante Ex Post

C

A

B

Patented Technology Standardized Patented Technology Standardized Absent DisclosureAbsent Disclosure

DX0170







DX0123

Nature and Scope of Market DefinitionNature and Scope of Market Definition

Defines relevant scope of competitive activity Provides context to analysis of market power /

effects Common starting point for economic analysis in

antitrust-related inquiries

DX0171

Market Definition: MethodologyMarket Definition: Methodology

Analysis starts with market hypothesis Hypothesis tailored to antitrust issues presented Assume hypothetical monopolist Evaluate competitive constraints on hypothetical

monopolist Methodology is well-accepted

DX0172

Market Definition: MethodologyMarket Definition: Methodology

A

B D

C

E F

G H

DX0173

Technology MarketsTechnology Markets

Market for technology-related ideas / inventions Market definition concepts apply no differently

than in the case of physical “product” market Data on price / sales may be more limited Geographic scope is generally worldwide Well-accepted in economic analysis

DX0174

Technical FeasibilityTechnical Feasibility

Must be feasible to be in market Technical Issue

Testimony of engineers at trial Deposition testimony of engineers Testimony of Bruce Jacob Discussions with DRAM engineers

DX0175

Commercial ViabilityCommercial Viability

Commercially viable technologies are technologies that constrain prices of chosen technology

Parallel to the “SSNIP” test for markets with no price data Well-informed market participants treat as good

substitutes Serious consideration at JEDEC Qualitative judgments of knowledgeable engineers

DX0176

Commercial Viability ConsiderationsCommercial Viability Considerations

Time to market critical for JEDEC DRAM standards – “satisfice”

IP / royalties Cost of the solution to DRAM manufacturers

and others Performance benefits of the technology Strategic considerations that reflect the

competitive position of each member Every technology had problems to be solved

DX0177

Cost / Performance ConsiderationsCost / Performance Considerations

Different preferences on DRAM costs Some members more sensitive than others

Different preferences on DRAM performance Some members value performance more than others

Value of technologies depends on subsequent infrastructure AMD K-7 designed to exploit Burst Length of 8

Costs are uncertain until DRAM is manufactured commercially DDR in 1998 v. 2003

DX0178

F

E

D

C

B

A

Relevant Technology Market

Commercial Viability of TechnologiesCommercial Viability of Technologies

$ $ $ $

$ $ $

$ $

$

$

$

DX0179

Relevant TechnologiesRelevant Technologies

Programmable CAS latency Programmable burst length Dual-edge clock On-chip PLL/DLL

DX0180

Relevant Market Analysis: Relevant Market Analysis: Programmable CAS LatencyProgrammable CAS Latency

Technology used to set latency on DRAM Other “technically feasible” alternatives Some alternatives are “commercially viable” Market includes programmable CAS latency and

all commercially viable alternatives

DX0181

Technically Viable Alternatives for Technically Viable Alternatives for Programmable CAS LatencyProgrammable CAS Latency

Fixed CAS latency Set latency with pins Set latency with read command Program CAS latency by blowing fuses on the

DRAM Scale CAS latency with clock frequency

DX0182

Latency Technology MarketLatency Technology Market

Fixed CAS latency Presented at JEDEC

NEC Presentation at 42.3 Committee Meeting 76 (9/95)

Cost impact “A fixed DRAM is easier to test. Every time you add a new

feature to the DRAM, you have to test it. So, from a test cost point of view, there would have been an advantage to fixing every function in the DRAM, including programmable CAS and burst length.” Macri Trial Testimony at 4773

Potentially higher inventory costs to DRAM manufacturers – Macri Trial Testimony at 4763-64

DX0183


Programmable by pin strapping Presented at JEDEC

Micron Presentation at Special 42.3 Committee Meeting (7/00)

Cost impact “Q. So, one of the costs of these -- of this alternative would

have been to add extra pins on the DRAM? A. Yes, but if you're smart, you do it in a way where the cost is exceedingly minimal, and that's what, you know, we try to build the products on, being smart.” Macri Trial Testimony at 4767

DX0184


Programmable in read command Not presented at JEDEC

Mitsubishi Presentation at 42.3 Committee Meeting 60 (12/91) (Programming Burst Length)

Cost impact “The advantage would be that you would eliminate the mode

register and the circuitry required to decode special commands and put that information into the mode register, so it would make the part potentially smaller and simpler.” Jacob Trial Testimony at 5391-92

DX0185


Set by fuses Presented at JEDEC

Cray Presentation at 42.3 Committee Meeting 62 (5/92)

Cost impact “It would be potentially a simpler design. You would

eliminate the mode register. It would be potentially a smaller design and therefore a cheaper design. After blowing the fuse, you would only need to test one CAS latency value instead of having to test all possible CAS latency values, so it would be a cheaper alternative potentially.” Jacob Trial Testimony at 5382

DX0186

Commercially Viable Alternatives for Commercially Viable Alternatives for Programmable CAS LatencyProgrammable CAS Latency

Fixed CAS latency Set latency with pins Set latency with read command Program CAS latency by blowing fuses on the

DRAM Scale CAS latency with clock frequency

Latency Technology Market

DX0187

Relevant Market Analysis: Relevant Market Analysis: Programmable Burst LengthProgrammable Burst Length

Technology used to set amount of data read from a DRAM in response to a read request

Other “technically feasible” alternatives Some alternatives are “commercially viable” Market includes programmable burst length and

all commercially viable alternatives

DX0188

Technically Viable Alternatives for Technically Viable Alternatives for Programmable Burst LengthProgrammable Burst Length

Fixed burst length Use a separate pin or pins to set burst length Use burst-length-specific read commands to set

burst length Use a “burst terminate” command Program burst length by blowing fuses on the

DRAM

DX0189

Burst Length Technology MarketBurst Length Technology Market

Fixed burst length Presented at JEDEC

NEC Presentation at 42.3 Committee Meeting 76 (9/95) Cost impact

“A fixed DRAM is easier to test. Every time you add a new feature to the DRAM, you have to test it. So, from a test cost point of view, there would have been an advantage to fixing every function in the DRAM, including programmable CAS and burst length.” Macri Trial Testimony at 4773

DX0190


Programmable by pin strapping Not presented at JEDEC

Micron Presentation at Special 42.3 Committee Meeting (7/00) (Programming CAS latency)

Cost impact “The cost associated with each of those was relatively similar

in the large scheme of things, so I would say from a cost standpoint, that was a large factor in our decision.” Kellogg Trial Testimony at 5132

DX0191


Programmable in read command Presented at JEDEC

Mitsubishi Presentation at 42.3 Committee Meeting 60 (12/91)

Cost impact “Well, again, you would get rid of the mode register and

therefore the circuitry required to initialize it, which would make the part simpler to design and test and potentially cheaper to manufacture.” Jacob Trial Testimony at 5407-408

DX0192


Burst interrupt In SDRAM and DDR SDRAM standards and

proposed for DDR-2 Cost impact

“I mean, for DDR2, the DDR2 SDRAM standard, we do have burst interrupt, and it is fixed, and it's not a burden to the DRAM designers. The DRAM designers, if I recall their words, they said this is easy.” Macri Trial Testimony at 4775

DX0193

Commercially Viable Alternatives for Commercially Viable Alternatives for Programmable Burst LengthProgrammable Burst Length

Fixed burst length Use a separate pin or pins to set burst length Use burst-length-specific read commands to set

burst length Use a “burst terminate” command Program burst length by blowing fuses on the

DRAM

Burst Length Technology Market

DX0194

Relevant Market Analysis: Relevant Market Analysis: Dual-Edged ClockingDual-Edged Clocking

Technology used to increase the amount of data transmitted on the data bus

Other “technically feasible” alternatives Some alternatives are “commercially viable” Market includes dual-edged clocking and all

commercially viable alternatives

DX0195

Technically Feasible Alternatives for Technically Feasible Alternatives for Dual-Edge ClockDual-Edge Clock

Use two or more interleaved memory banks on-chip.

Keep each DRAM single data rate and interleave banks on the module (DIMM).

Increase the number of pins per DRAM Increase the number of pins per module Double the clock frequency Use simultaneous bidirectional I/O drivers Use toggle mode

DX0196

Data Acceleration Technology MarketData Acceleration Technology Market

Keep each DRAM single data rate and interleave banks on the module (DIMM) Presented at JEDEC

Kentron Presentation at 42.5 Committee Meeting 42 (12/99)

Cost impact More expensive due to components on module but used

cheaper DRAMs

Royalties may be a problem

DX0197


Increase the number of pins per module Not presented at JEDEC Might not be commercially viable because of

increased costs of doubling the width of the data bus But data bus has been doubled in recent years by

Nvidia.

DX0198


Double the clock frequency Presented at JEDEC

VLSI Presentation at 42.3 Committee Meeting 78 (3/96) Cost impact

“Well, a faster single edge clock has some enormous benefits in that we don't have to pay attention to this concept called duty cycle. Duty cycle -- you know, a clock has a pulse that is high and a pulse that is low, and the duty cycle is the length of the high pulse versus the length of the low pulse, and managing that is very difficult across real world conditions. It sounds simple; very complicated. Single edge clocking doesn't have that issue at all. So, that's a huge benefit to single edge clocking.” Macri Trial Testimony at 4779-4780

DX0199

Commercially Viable Alternatives for Commercially Viable Alternatives for Dual-Edge ClockDual-Edge Clock

Use two or more interleaved memory banks on-chip. Keep each DRAM single data rate and interleave banks

on the module (DIMM). Increase the number of pins per DRAM Increase the number of pins per module Double the clock frequency

Use simultaneous bidirectional I/O drivers

Use toggle mode

Data Acceleration Technology Market

DX0200

Relevant Market Analysis: Relevant Market Analysis: On-Chip DLLOn-Chip DLL

Technology used to synchronize the clock on the DRAM with the system clock

Other “technically feasible” alternatives Some alternatives are “commercially viable” Market includes on-chip DLL and all

commercially viable alternatives

DX0201

Technically Feasible Alternatives for Technically Feasible Alternatives for On-Chip PLL/DLLOn-Chip PLL/DLL

Put the DLL on the memory controller Use off-chip (on-module) DLLs Use a vernier method to account for skew Achieve high bandwidth using more DRAM pins,

not clock frequency Rely upon DQS data strobe to provide timing

DX0202

Clock Synch Technology MarketClock Synch Technology Market

Put the DLL on the memory controller Presented at JEDEC

Samsung Presentation at 42.3 Committee Meeting 78 (3/96)

Cost impact “You would eliminate the on-chip DLL, which would reduce the

power consumption of the DRAM. It would reduce the die size of the DRAM, which would reduce the manufacturing cost of the DRAM. You would reduce the testing costs of the DRAM because you don't have this PLL or, rather, this DLL that would be part of the DRAM. It would be a simpler design because it would not include a DLL and therefore cheaper, take less time. And it would cancel out more timing uncertainty than simply putting the DLL out on the DRAM itself, so you could potentially reach higher rates of speed than just using an on-chip DLL alone.” Jacob Trial Testimony at 5446-5447

DX0203


PLL/DLL on module PLL on DIMM in registered DIMMs and in Kentron

QBM DIMM Cost impact

“You eliminate the on-chip DLL from the DRAM, thereby reducing its power consumption, reducing its cost, reducing the design time. … [Y]ou then move that design complexity onto a special DLL chip that goes onto the module, so you would be trading one for the other.” Jacob Trial Testimony at 5450

DX0204


Vernier Presented at JEDEC

Synclink Presentation at 42.3 Committee Meeting 75 (5/95)

Cost impact “It's simpler to design than a DLL and it would cancel out

potentially more skew than a DLL so you could potentially achieve higher data rates using it. And burn less power.” Jacob Trial Testimony at 5452

DX0205


No DLL at all Presented at JEDEC

SGI Presentation at 42.3 Interim Committee Meeting (7/97)

Cost impact “Q. Now, what, if any, would be the advantages of relying on

a DQS data strobe to provide timing rather than using on-chip DLLs?

A. Well, you would eliminate your DLL, which would make your design simpler. It would consume less power. The design would be smaller, cheaper to manufacture, and so forth.”

Jacob Trial Testimony at 5457

DX0206

Commercially Viable Alternatives for Commercially Viable Alternatives for On-Chip PLL/DLLOn-Chip PLL/DLL

Put the DLL on the memory controller Use off-chip (on-module) DLLs Use a Vernier method to account for skew Achieve high bandwidth using more DRAM pins,

not clock frequency Rely upon DQS data strobe to provide timing

Clock Synchronization Technology Market

DX0207

Asynchronous AlternativeAsynchronous Alternative

Asynchronous DRAM designs (e.g., Burst EDO) were an alternative to synchronous DRAMs

Some JEDEC participants (e.g., Micron) preferred asynchronous designs

Evolutionary advantages Choice of synchronous DRAM diverted

resources away from asynchronous designs

DX0208

Asynchronous – Burst EDOAsynchronous – Burst EDO

Alternative to both programmable CAS latency and burst length in SDRAM

Often presented at JEDEC NEC Presentation at 42.3 Committee Meeting (3/95)

Cost impact “It would have been a simpler transition because the technology

existed at the time. This was a technology that the engineers of the time were more familiar with. Asynchronous DRAM tended to have smaller die sizes like burst EDO at the time had a smaller die size than SDRAM and had better performance at the same speeds. So asynchronous potentially had better performance and cheaper implementation.” Jacob Trial Testimony at 5395-96

DX0209

Relevant Technology MarketsRelevant Technology Markets

Four relevant technology markets in this case:

Latency technology market Burst length technology market Clock synchronization technology market Accelerating data exchange technology market

These technology markets may be treated collectively as a single “cluster market”

Synchronous DRAM Technology MarketDX0210

A

B

C

D

E

F

G

H

I


““Cluster” MarketCluster” Market

Feature 1

Feature 2

Feature 3

B, F, G

DX0211

Relevant Geographic MarketRelevant Geographic Market

For each relevant technology market, the relevant geographic market is the world

Buyers adopt technology with best value independently of geographic source

Technology licensed worldwide JEDEC-compliant DRAM produced and used

worldwide Negligible transportation costs

DX0212

Commercially Viable Alternatives for Commercially Viable Alternatives for Dual-Edge ClockDual-Edge Clock

Use two or more interleaved memory banks on-chip. Keep each DRAM single data rate and interleave banks

on the module (DIMM). Increase the number of pins per DRAM Increase the number of pins per module Double the clock frequency

Use simultaneous bidirectional I/O drivers

Use toggle mode

Data Acceleration Technology Market

DX0213


Use toggle mode Considered at JEDEC by April 1992

“I think we had five companies showing what they called their own toggle mode in their presentations on the consideration of the first-generation synchronous DRAM.” Kelley Trial Testimony at 2585-86.

DX0214


Keep each DRAM single data rate and interleave banks on the module (DIMM) Presented at JEDEC

Kentron Presentation at 42.5 Committee Meeting 42 (12/99)

Cost impact More expensive due to components on module but used

cheaper DRAMs

Royalties may be a problem

DX0215







DX0123

Market and Monopoly PowerMarket and Monopoly Power

Market power is the ability profitably to maintain prices above a competitive level

Monopoly power refers to market power that is both substantial and durable

DX0216

Indicia of Rambus’s Monopoly PowerIndicia of Rambus’s Monopoly Power

In each relevant technology market, Rambus’s technologies today are the only commercially viable alternatives

Substantial barriers to entry

Ex post pricing of Rambus’s technologies substantially exceeds their ex ante value

DX0217

Development of JEDEC’s Development of JEDEC’s SDRAM StandardsSDRAM Standards

A

R

B

R

C

D

R

E

1993SDR

1999DDR

2003-04DDR-2

RR

DX0218

Evolution of DRAM StandardsEvolution of DRAM Standards

0

20

40

60

80

100

1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005

Other FPM EDO SDRAM DDR RDRAM

Source: Cahners In-Stat “DRAM Memory Primer 2000” March 2000, Page 57 and In-Stat MDR “DRAM Market Forecast – Is there life After PCs” July 2002, Page 75

DX0141

DDRSDRAM

RDRAM Other

Types of DRAM Produced Today

DDRSDRAM

RDRAM

Types of DRAM Over Which Rambus Asserts Patents

Types of DRAM Over Which Rambus Types of DRAM Over Which Rambus Asserts PatentsAsserts Patents

Other

Source: Cahners In-Stat MDR “DRAM Market Forecast – Is there life After PCs” July 2002, Page 75 DX0219

Commercially Viable Alternatives Commercially Viable Alternatives

A

B D

C

E F

G H

Ex AnteEx Post

DX0220

Chipset

Motherboard

Mem

ory M

odule

Connectors

Gra

phics

Car

ds

Gra

phic

s Su

bsys

tem

s

Hard drive storage

CD

RO

M /

DVD

Driv

es

Modems

Net

wor

k C

ards

Sound Cards

Industry-Wide Coordination and Industry-Wide Coordination and Resource CommitmentResource Commitment

DRAM Standard

DX0221


Ex Ante Ex Post

R

A

B

Late Disclosure of Rambus Patents Late Disclosure of Rambus Patents Eliminated AlternativesEliminated Alternatives

DX0222

Costs of Changing Costs of Changing JEDEC Standards TodayJEDEC Standards Today

Develop new technology standards Difficulty of reaching consensus ex post Design, testing, and qualification of new DRAM

chips Redesign, testing, and qualification of existing

components Opportunity costs Cost of delay

DX0223

How Long Would It Take to Create a How Long Would It Take to Create a Non-Infringing Standard?Non-Infringing Standard?

19931991 1997

1995 1999 2002

1998 2003 +

SDR 2-6 years

DDR 4 years

DDR-2 5 years and counting

Volume Production

Volume Production

DX0224

Difficulty of Reaching Consensus Difficulty of Reaching Consensus Ex PostEx Post

Licensed producers have different incentives than unlicensed producers About 50% of the market has licenses

Users of specific features have distinct incentives AMD uses burst length of 8; Intel uses burst of 4

Greater disagreement ex post

DX0225

Barriers to EntryBarriers to Entry

Scale User switching costs

New product competes with existing devices Strong learning curve Sunk costs Patents

DX0226

Barriers to EntryBarriers to Entry

“The DRAM industry’s penchant for standardization combined with the Rambus marketing strategy of licensing all major vendors make it extremely unlikely that any potential competitor would be able to gain critical mass enough to challenge an already established and ubiquitous Rambus chip.”

Source: Rambus Business Plan Draft 6/26/89. CX0533, R114636

DX0227

RDRAMRDRAM Versus Versus DDRDDR Pricing Pricing

2.0

%

time

3.5

4.25

If Licensed at All

Samsung + Others

Hitachi

InfineonHynixMicron

?

DX0228







DX0123

Exclusionary ConductExclusionary Conduct

What is exclusionary conduct?

Conduct that tends to exclude equal or superior products

Effect is anticompetitive – harms consumers

No valid efficiency rationale

DX0229

Exclusionary Conduct: Exclusionary Conduct: Major AssumptionsMajor Assumptions

Rambus possessed IP relevant to JEDEC standards / work

Rambus failed to disclose relevant IP as required by JEDEC rules / process

Rambus engaged in other, related misrepresentations while a member of JEDEC

After leaving JEDEC, Rambus continued to conceal its IP Before, during, and after JEDEC participation, Rambus

planned to enforce JEDEC-related IP Rambus was aware of legal risks associated with this

conduct (i.e., equitable estoppel)

DX0230

Reasons Why Rambus’s Challenged Reasons Why Rambus’s Challenged Conduct Is ExclusionaryConduct Is Exclusionary

Distorted JEDEC’s standard setting process by concealing (or misrepresenting) material information

Excluded alternative commercially viable DRAM technologies

Entailed a conscious choice to jeopardize the enforceability of patented intellectual property

DX0231

Exclusionary Conduct: Exclusionary Conduct: Misleading InformationMisleading Information

Concealing or providing misleading information is exclusionary when equal or superior products excluded

Concealing or providing misleading information prevents competition on the merits

Raising the perceived relative cost of alternatives is exclusionary

DX0232

““But-For” World AnalysisBut-For” World Analysis

“But-For” world = suppose (hypothetically) Rambus did not engage in challenged conduct

Compare actual and “but-for” world outcomes to determine effect of challenged conduct

Standard economic methodology

DX0233

If Rambus Had Disclosed IP to JEDEC:If Rambus Had Disclosed IP to JEDEC:No RAND LetterNo RAND Letter

Rambus documents state RAND not consistent with business model

Rambus wanted flexibility to charge different royalty rates

Rambus wanted RDRAM to succeed Not issuing RAND letter could have helped RDRAM Without RAND letter, JEDEC could not include IP in

standard

DX0234

JEDEC likely would not have included Rambus IP in standards Commercially viable alternatives Strong incentive to avoid running royalties because of

price sensitivity JEDEC process requires consensus

Incentive for ex ante negotiations RAND letter does not specify royalty rate Rambus had different incentives – “pure play”

technology company

If Rambus Had Disclosed IP to JEDEC:If Rambus Had Disclosed IP to JEDEC:RAND Letter IssuedRAND Letter Issued

DX0235

R1

B

R2

C

R3

D

R4

E

Rambus’s Conduct in Actual World:Rambus’s Conduct in Actual World:Outcome of JEDEC ProcessOutcome of JEDEC Process

SDR DDRR1, R2, R3, R4R1, R2

DX0236

R1

B

R2

C

R3

D

R4

E

SDR DDRB,C,D,EB,C

Rambus’s Conduct in “But-For” World:Rambus’s Conduct in “But-For” World:Outcome of JEDEC ProcessOutcome of JEDEC Process

DX0237

Exclusionary Conduct: Exclusionary Conduct: Rambus’s Costly InvestmentRambus’s Costly Investment

By not disclosing IP ex ante, Rambus knowingly incurred risk of having patents found unenforceable

Implication is that Rambus expected compensating benefits from non-disclosure

Like predatory pricing, this conduct is irrational absent expected benefits from excluding competition

DX0238

Rambus’s Conduct Would Not Be Rational Rambus’s Conduct Would Not Be Rational Absent Its Exclusionary EffectAbsent Its Exclusionary Effect

“…the only product that Rambus has about this is intellectual property. Doing anything as stupid as putting intellectual property in jeopardy by sitting in a meeting would have been ‑‑ passively sitting in a meeting, which is my understanding of what we did, would have been the stupidest management move that I could think of.

And you know, there isn't ‑‑ there is no rational motivation that I can think of that you would jeopardize the value of your patents by participating in a process that might deprive you of the right to enforce those patents.

I mean, it's ‑‑ there was very little to be gained and everything to be lost. I mean, that's not the kind of thing that you do with a rational manager.”

Deposition of Rambus Chairman, W. Davidow, 1/21/03, p.36 DX0239







DX0123

Effects of Rambus’s ConductEffects of Rambus’s Conduct

Substantially higher, and discriminatory, prices (royalties) in the relevant technology markets

Actual (and threatened future) distortions to competition in those markets

Threat of higher DRAM prices Harm to standards setting processes

DX0240

DDRSDRAM

RDRAM Other

Types of DRAM Produced Today

DDRSDRAM

RDRAM

Types of DRAM Over Which Rambus Asserts Patents

Types of DRAM Over Which Rambus Types of DRAM Over Which Rambus Asserts PatentsAsserts Patents

Other

Source: Cahners In-Stat MDR “DRAM Market Forecast – Is there life After PCs” July 2002, Page 75 DX0219

Rambus RambusDRAM Mfrs. DRAM Mfrs.

Ex Ante Ex Post

Bargaining PowerBargaining Power

$ RAND or $0 Monopoly Royalty

DX0241

3.5%4.25%

?

SamsungOthers

Hitachi InfineonHynixMicron

Rambus’s Discriminatory DDR RoyaltiesRambus’s Discriminatory DDR Royalties

DX0242

Market Distortions Caused by Market Distortions Caused by Rambus’s ConductRambus’s Conduct

Harm to innovation Specific design investments Litigation costs Design-around costs Increased market uncertainty Potential delay in standard setting Long-run higher DRAM prices Harm to standards setting processes

DX0243

Consequence of Rambus’s Consequence of Rambus’s Changed PositionChanged Position

SDRAM / DDRRDRAM

RDRAM

.75 – 4.25% Royalty

1.5 – 2% Royalty

DX0244

Economic Analysis of RemediesEconomic Analysis of Remedies

Preferred remedy: to restore competition to the situation that would have existed absent the anticompetitive conduct

As a practical matter, in this case the preferred remedy cannot be achieved Rambus’s monopoly power is durable The “but-for” world is now unattainable Some of the damage caused by Rambus’s conduct

can no longer be reversed

DX0245

Practical LimitationsPractical Limitations

An installed base of SDRAM and DDR SDRAM devices has been developed, and investment in JEDEC-compliant technology has already been committed

The DDR-2 standard has been developed largely under the same assumptions as were used for SDRAM and DDR SDRAM

Technological development in alternatives to Rambus’s claimed technologies has been foregone

DX0246

““Second-Best” Approach to RemediesSecond-Best” Approach to Remedies

If the conduct cannot be undone, then the effects of the conduct should be undone

The appropriate remedy to Rambus’s conduct thus involves minimizing the marketplace harm associated with the anticompetitive behavior

DX0247

Undoing the Effects of Undoing the Effects of Rambus’s ConductRambus’s Conduct

Rambus should be prohibited from enforcing against JEDEC-compliant DRAMs any patents filed (or based on filings) prior to June 18, 1996

This remedy should extend both to US and foreign patents

This remedy will restore competitive pricing in the relevant technology markets and mitigate other anticompetitive effects

DX0248

competitive solutions dx0120. nature of assignment retained by ftc counsel spring 2002 conduct...

Documents

rambuss exclusionary

relevant antitrust markets

open competitive process

patented technologies

analyst reports

anticompetitive harm

economic factors

jedecs sdram