competitive semiconductor manufacturing

No Slide TitleCompetitive Semiconductor Manufacturing
Program Engineering Systems Research Center University of California at Berkeley
April 15, 2002
Agenda
Trade-offs between metrics
April 15, 2002 RCL - CSM Findings 3
CSM Program Since 1991, the largest interdisciplinary
research program at Berkeley (8 faculty, 15 students from Business, Economics and Engineering) Fab performance benchmarking Focus studies (MS and PhD projects) 52 CSM reports may be ordered on the Web at
http://euler.berkeley.edu/esrc/csm
Benchmarking fab performance
1991: Pilot phase with Intel, NEC and HP
1992-96: Studied 29 fabs in USA, Japan, Korea, Taiwan and Europe under sponsorship of Alfred P. Sloan Foundation Mostly 6-inch wafer fabs (six 5-inch, two 4-inch
fabs) operating process technologies ranging from 10 micron down to 0.4 micron line widths
Benchmarking fab performance (cont.) Most recent phase of study (1997 - 2001)
sponsored by Sematech, SIRIJ/EAIJ, TSMC, UMC, Winbond, Samsung, Micrus, Cypress, ST Microelectronics Fab lines running 8-inch wafers in 350nm and
below CMOS technologies 10 lines studied Final report on this phase issued Mar., 2002
Factory data collection Mail-Out Questionnaire (MOQ) 2-3 years of fab history (plus updates) process technologies, production volumes, yields,
cycle times equipment and facilities headcount and HR data
We compute technical metrics from these data. Identities of fabs are kept confidential.
Studying practices: the site visit
Team of 8 faculty and graduate students for a 2 or 3 day visit
Tour fab (focus on evidence of self- measurement, communication, problem- solving activity
Interview cross-section of organization (managers, engineers, technicians, operators)
Site visit (cont.) Sessions to review approaches to problem
areas (yield improvement, equipment efficiency improvement, cycle time reduction, on-time delivery improvement, new process introductions) Sessions to review problem-solving
resources (CIM and information systems, process control, work teams, human resource development)
Technical metrics
Line yield metric Line yield of a fabrication process accounts for all wafer
losses occurring up through E-Test LY = (wafer outs in month) / (wafer outs + wafer scraps in
month) Line yield per twenty layers for a fabrication process: LY20 = LY20/N, where N is the number of photo exposure
steps in the process LY20 for the fab is the weighted average of LY20 scores
for the process flows in the fab:
∑
∑ =
Die yield and defect density metrics Die yield of a device accounts for all wafer and die losses
occurring after E-Test. DY is reported by the participants for the highest-volume device in each process flow.
Defect density D of a device is the equivalent Murphy- model defect density that would account for all die yield losses: 2
1
AD
where A is the device area and DY is the reported die yield. We classify defect densities by memory vs. logic and by line width category.
Integrated yield metric
The integrated yield of a fab process accounts for all line yield and die yield losses for a hypothetical 20-layer, 0.5 sq cm device:
( )[ ]0.5)(20 == ADYLYIY
where LY20 is the line yield per twenty layers, DY(A=0.5) is the Murphy-model die yield of a 0.5 sq cm device for the calculated defect density of the process.
Integrated yield scores also are categorized by product type and line width.
The “Berkeley metrics” Line yield per 20 mask layers (LY20) Defect density (die yield plugged into Murphy Model) (D) Integrated yield (line yield times die yield) (IY) Throughput of photo equipment (wafers processed per stepper
per day) (STP) Integrated stepper throughput (ISTP = IY*STP) Direct labor productivity (wafer layers per operator per day)
(DLP) and total labor productivity (wafer layers per headcount per day) (TLP)
Process development and qualification time (VT) Time to ramp to mature die yield (RT) Cycle time per mask layer (CTPL)
Line Yield
Li ne
y ie
ld p
er 2
0 la
ye rs
(p er
ce nt
M1 M2 M3 M4 M5 M6 M7 M8 M9 M10
5
CMOS Logic Device Defect Density 0.45 - 0.6 micron CMOS process flows
0.01
0.10
1.00
10.00
Time
CMOS Logic Device Defect Density 0.35 - 0.4 micron CMOS process flows
0.1
1
10
D ef
CMOS Logic Device Defect Density 0.25 micron CMOS process flows
0.1
1
10
D ef
Memory Device Defect Density (after repair) 0.45 - 0.5 micron CMOS process flows
0.1
1
10
D ef
0.01
0.1
1
10
D ef
0.01
0.1
1
10
D ef
CMOS Logic Device integrated Yield 0.45 - 0.6 micronCMOS process flows
30
40
50
60
70
80
90
100
In te
gr at
ed Y
ie ld
CMOS Logic Device Integrated Yield 0.35 - 0.4 micron CMOS process flows
20
30
40
50
60
70
80
90
100
In te
gr at
ed Y
ie ld
CMOS Logic Device Integrated Yield 0.25 micron CMOS process flows
20
30
40
50
60
70
80
90
100
In te
gr at
ed Y
ie ld
Memory Device Integrated Yield 0.45 - 0.5 micron CMOS process flows
20
30
40
50
60
70
80
90
100
In te
gr at
ed Y
ie ld
(a fte
20
30
40
50
60
70
80
90
100
In te
gr at
ed Y
ie ld
(a fte
20
30
40
50
60
70
80
90
100
In te
gr at
ed Y
ie ld
(a fte
I-Line 5X Stepper Productivity
Time
M7 M8 M9 M10
DUV Stepper Productivity
W af
er o
pe ra
tio ns
p er
s te
pp er
p er
d ay
Stepper Productivity (all types of steppers)
0
100
200
300
400
500
600
700
800
900
1000
1100
Time
M1 M2 M3 M4 M5 M6 M7 M8 M9 M10
Integrated Stepper Throughput
Eq ui
v. fu
ll w
af er
o pe
ra tio
ns p
er s
te pp
er p
er d
ay M1 M2 M3 M4 M5 M6 M7 M8 M9 M10
Space Productivity
M as
k la
ye rs
p er
s q
ft pe
Direct Labor Productivity
M as
k la
ye rs
p er
d ire
ct la
ay
M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 5
Total Labor Productivity
Time
M1 M2 M3 M4 M5 M6 M7 M8 M9 M10
Cycle Time Per Layer
C yc
le ti
m e
M1 M2 M3 M4 M5 M6 M7 M8 M9 M10
Performance benchmarks (8-inch) LY20 = 98% for both logic and memory D = 0.05 per sq cm for memory (after repair), 0.20 per sq cm
for logic IY = 93% for memory, 89% for logic (assuming a 0.5 sq cm
device area) STP = 1,000 for logic, 900 for memory ISTP = 800 for logic, 600 for memory DLP = 85 for memory, 55 for logic TLP = 50 for memory, 37 for logic CTPL = 1.4 for both logic and memory (at high volume) VT = 4 months for similar process, 7 months for very new one RT = 4 months
Benchmark vs. average scores for speed metrics Process development time = 4 months vs. 7 months for
similar process, 7 months vs. 12 months for very new
process
technology introduced 1 year after leader introduced it)
Manufacturing cycle time per mask layer (CTPL) = 1.4
days vs. 2.3 days for both logic and memory (at high
volume)
Yield trends Contamination (defects) is a major yield
limiter for multi-level metal products
Systematic losses are larger than defect losses
for many products, especially memory devices
Ill-formed structures (leakage, overlay, etc.)
Edge losses
Example Die Loss Pareto (SRAM)
P+ S/D into N+ base
Core leakage
M2 defects
Performance trends With some important exceptions, we find more
closure in mature yields achieved by the
participants than in previous phases of CSM
The speed-related metrics, i.e., process
development time, yield ramp time, cycle time, are
major discriminators of performance
discriminators
Trade-offs between metrics It seems increasingly difficult to sustain a
stable process in advanced digital technologies
Process engineers face many trade-offs between yield, wafer throughput and cycle time
Trade-offs (cont.)
alignment is quite difficult
Alternative photo strategies
Fab M4: must use exactly same stepper at all three critical layers
Fab M2: no restriction on stepper selection
Fab M1: given the selection of stepper at first layer, restrict choice of stepper at layers 5 and 9 to three particular machines
3-D performance plots Yield axis: we plot integrated yield, IYD =
(LY20)(Murphy die yield for 0.5 sq cm device)
Wafer throughput axis: we plot a normalized
stepper throughput, STP = (daily t-put)/1000
Cycle time axis: we plot a normalized reciprocal
of cycle time, CT = 1.2/(CTPL)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
Economic interpretation
models to compute changes in wafer cost and
revenue per wafer as a function of changes in
manufacturing speed or efficiency
web site: http://euler.berkeley.edu/esrc/csm
Economic interpretation (cont.) Analyze performance differences in the speed metrics
(process development time, yield ramp time,
manufacturing cycle time) and in OEE
Apply average and benchmark scores to greenfield
fab running the Sematech 250nm 5-metal logic
process at 25,000 wafers per month over 5 years
Assume revenue per 100%-yielding wafer is $10,000
at time 0 and going down 25% per year
Economic interpretation (cont.)
Metric Average Benchmark Development time 360 days 210 days Yield ramp time 360 days 210 days Cycle time per layer 2.2 days 1.5 days DUV OEE 42% 58% I Line OEE 67% 85% Dry etch OEE 43% 80% HE Implant OEE 48% 69%
Economic comparison Average Benchmark Diff.
performance performance
Differences in manufacturing speed seem twice as significant economically as differences in manufacturing efficiency
Six basic themes for best practices
Automate information handling and make manufacturing mistake-proof
Collect detailed process, equipment and test data, integrate the data and analyze it statistically
Wisely manage development and introduction of new process technology
Six key practices (cont.)
Reduce lost time and process time on steppers and other bottleneck equipment
Implement intelligent scheduling and WIP management
Reduce division of labor, up-skill the workforce, develop a problem-solving organization
Automation of information handling
Automated process control
Automated process control
photo CDs
Data integration and analysis
equipment in one database
Analysis carried through to identify root cause and prove out the fix
Extensive in-line defect monitoring correlate with die yield, classify signatures
Effective yield management techniques
Use both electrical and optical in-line monitoring
Plot yield vs. area and vs. position of die on wafer to sort out systematic vs. random losses
Set defect budget (e.g., defective die per layer) Track high-yielding lots to establish equipment
capability
Managing process development and transfer
Control the number of simultaneous
engineering variables:
wafer sizes
modules in each generation
Managing process development and transfer (cont.) Minimize complexity of hand-off
“Copy exactly” policy:
identical CIM systems
for development
Equipment efficiency improvement
losses in machine cycles SPC-type alarms for inferior equipment speed
TPM teams for improved machine operation and maintenance
Scheduling and WIP management
Intelligent detailed, on-line scheduling based on analysis of downstream WIP situation and intelligent targets
Fab-out targets and fab-in control according to capacity and current WIP
WIP
Diffusion Photo Fab In Fab Out
Input control •Control fab in according to out schedule, WIP and capy
Non-bottleneck schedulers •Schedule equipment to complete targets and prevent steppers from starving
Bottleneck scheduler •Schedule steppers to complete targets and to maximize utilization
Output planner •Identify bottlenecks and schedule target fab out according to WIP level and stepper capacity
Planning and Scheduling Target setting • Target cycle times, target WIP, target production
Up-skilling the work force
technicians supported by engineers
Upgrade operator into “Self-sustaining
technician” or “Self-help lady”
or “Key man”
Reduced division of labor
maintenance groups
engineering groups
Yield analysis carried out by process engineers, or
root-cause determination by yield engineers
Some conclusions We find major differences in technical
performance.
Trade-offs between various metrics are optimized differently among the participants.
Nonetheless, fast ramp-up of production processes to high yield and high throughput while driving down cycle time are basic aims for everyone.
Some conclusions (cont.) Fast improvement depends on rapid
problem identification, characterization and solution by a large, diverse organization Common themes of successful approaches: Leadership and development of personnel Organizational participation, communication,
accountability and responsibility for improvement Information strategy and analytical techniques that
accelerate improvement
How to get in touch
• To order any of the 52 CSM reports, visit our web site at
http://euler.berkeley.edu/esrc/csm
[email protected]
Site visit (cont.)
Integrated yield metric
The “Berkeley metrics”
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Performance benchmarks (8-inch)
Yield trends
Performance trends
Six key practices (cont.)
Automation of information handling
Managing process development and transfer (cont.)
Equipment efficiency improvement

competitive semiconductor manufacturing

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