compe 460 real-time and embedded systems

CompE 460Real-Time and Embedded Systems

Lecture 5 – Hardware Fundamentals

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Agenda

• Prayer/Thoughts• Team Presentation - Brandon• Some Hardware Fundamentals

• Open Collector outputs• Tri-state outputs• Signal Overloading• Circuit Timing Parameters• Buses

• Address Maps• Attaching multiple things on a bus

– Wait states– Wait Signals– No Handshake

• PAL’s/FPGA’s• Watchdog Timer


Team Presentation

• Schematics


Future Memory Technologies

• DVRAM (Deja-Vue RAM)• the CPU thinks it has the data before it actually does

• PVRAM (Presque-Vue RAM)• the CPU only has to pretend to access RAM to get the data

• ODRAM (Oracle at Delphi RAM)• returns data the CPU plans to access next (first data access has to be a

NOP).• HRAM (Hearsay RAM)

• CPU talks to other CPUs and uses what they all think the data is, instead of accessing the data (which may be different)

• 711RAM (Seven-Eleven RAM)• always available, but may be held up during the night shift

• ARAM (Audio RAM)• like video RAM, but describes the image verbally instead

• MRAM (Mumble RAM)• gumb dortle vrmrgish tord summblum sart groff tuldard snangle gnig


What wrong with this?

CD G

AB

F

E


PC Systems

• What is an interrupt (in computer terms)?• On PC Systems, what are some sources of interrupts?

• USB• Keyboard• Disk Drive• Mouse• Network Card• Graphics Card• etc

• Now, a big dilemma. On many processors, there is only one low asserted interrupt pin.

• How can we hook up multiple interrupts to this one pin?

CD G

A

B

F

E


Multiple Interrupts on Same Line

Open Collector Outputs - Standard parts drive signals either high or low. Some devices (called open collector devices) drive their signals low or let them float.

uprocIC 2

IC 1

Vcc

INT’

Why do we need the pull-up resistor?


Data Bus

With this configuration, what will happen if the SRAM tries to send data to the uproc at the same time as the Flash?

Flash

SRAMuproc

Data Bus [d31:d0]

How can we fix this?


Tri-State Outputs

• Standard parts drive signals either high or low. • Open collector devices drive their signals low or let them

float.

• Tri-State devices can drive output high, low, or let them float.

• Used when you want more than one device to drive an input

• The outputs are enabled when the CS lines are true• Sometimes need pullup/down resistor on tristate lines – Why?

• Figure 2.16 in text


Data Bus

CS (or sometime called OE lines) will allow only 1 device to drive the bus at a time.

Flash

SRAMuproc

Data Bus [d31:d0]

CS1

CS0


Buses

• Simple processor example• Microprocessor – A0 to A15, D0 to D7• ROM – 32k (15 address lines), 8 bit data• RAM – 32k (15 address lines), 8 bit data


Block Diagram

CPU

Clock

D0D1D2D3

D7

::

A0A1A2

A15

::

D0D1D2D3

D7

::

A0A1A2

A14

::

ROM

D0D1D2D3

D7

::

A0A1A2

A14

::

RAM

RD/WR/

OE

/

CE

/

A15

A15

OE

/

CE

/W

E/

What would the memory map look like for this?


Memory Map

• ROM• 0x00 to 0x7fff

• RAM• 0x8000 to 0xffff

0x0000

0x7FFF0x8000

0xFFFF

ROM

RAM


How about other devices???

• What about attaching keyboards, LCD’s, network chips, etc.• How can we attach these types of

devices to the microprocessor?• What types of IO are available?

Memory Mapped IOMemory Mapped IOIsolated I/O spaceIsolated I/O space


8088 MPU

74F373 (2)

Address Latch

74F245 Data Bus

Transceiver

74F138 IO

Address Decoder

74F374 Port 0

MN/MX’Vcc

CLKALE

AD0-AD7,A8-A15

AD0-AD7

DT/R’

DEN’

A0L-A15L

A1L-A3L

CBA

IO/M’G2b’G2a’

G1

CLK

WR’

D0-D7

A0L

A15L

74F374 Port 1

CLK

74F374 Port 7

CLK

O0

O1

O7

O0

O1

O7

O0

O1

O7

P0

P1

P7

Isolated IO Space has separate spaces for IO and memory

Isolated IO


BF533

74F245 Data Bus

Transceiver

IO Address Decoder

74F374 Port 0

MN/MX’Vcc

A0-A15

D0-D7

DT/R’

DEN’

A0-A15

A1-A3

CBA

G2b’G2a’

G1

CLK

WR’

D0-D7

A0

A15

74F374 Port 1

CLK

74F374 Port 7

CLK

O0

O1

O7

O0

O1

O7

O0

O1

O7

P0

P1

P7

Memory Mapped IO uses the same space for IO and memory

Memory Mapped IO


PLD/FPGA

…UProc RAM Flash UART

Data, Address, Cntrl

FPGA or

CPLD

A13A14A15

Clk

RAMCEFlashCEUARTCE


Signal Overloading

• What is signal overloading?• Caused by connecting too many input circuits to a

single output• Also called Fan-out or loading problem

• How can you tell if you have a loading problem?• Data Sheets specify the current a device is able to drive on

its output lines• Data Sheets also specify the current a device will typically

source on its input lines

• How can you solve this?• Figure 2.19 in text


There is no such thing as Digital!!!

• All signals are really analog• It takes a finite amount of time for a signal to

travel from one point to another. High speed digital designers need to understand this

• Timing diagrams show actual AC timings including propagation delay.

http://emp.byui.edu/FISHERR/All_Classes/Digital/74ls00.pdf

http://emp.byui.edu/FISHERR/All_Classes/Digital/74ls00.pdf


Digital Circuit Timing

• There is a finite amount of time it takes for digital circuits to actually change state

• Ex. 74LS04 Propagation Delay is 15ns (max)

A A’

A

A’

Something to think about - 800 MHz front side bus has clock period of 1.25 ns - 7404 Inverter gate has

propagation delay of 15ns


Digital Circuit Timing

• There are several key timing characteristics associated with digital circuits• Propagation Delay• Setup Time• Hold Time• Max Clock Frequency• Clock pulse high and low times


Propagation Delay

• Propagation Delay is the time it takes for the output of the circuit to change after the input has changed.

• Depending on technologies (TTL, CMOS, ECL, etc), propagation delay’s of modern IC’s range from <1ns to ~100ns.


Setup Time

• The setup time is the time interval immediately preceding the active transition of the CLK signal during which the control input must be maintained at the proper level.

• If this time is not met, the FF may not respond to the CLK appropriately


Hold Time

• Hold Time is the time interval immediately following the active transition of the CLK signal during which the synchronous control input must be maintained at the proper level.

• If this time is not met, the FF may not respond to the CLK appropriately


Clock Frequency Spec’s

• Max Frequency (Fmax) - This is the highest frequency that may be applied to the CLK input and still have it trigger reliability

• Clock Pulse High (Twh) and Clock Pulse Low (Twl) Times – These are the minimum time duration that the clock signal must remain low before it goes high (Twl) and high before it returns low (Twh)


Timings

• How can we ensure each device can talk to the microprocessor?

• 3 Methods• Wait states – figure 3.6 and 3.7• Wait signal – figure 3.5• Buy fast enough parts - $$$


Timings

Typical Bus Read Cycle

A0-An

RD’

D0-Dn

Clock

uP drives Address bus to start bus cycle

uP drives RD low

Memory drives data busuP reads data from bus

End of bus cycle

T1 T2 T3


Timings

2-Wait State Bus Cycle

A0-An

RD’

D0-Dn

Clock

uP drives Address bus to start bus cycle

uP drives RD low

Memory drives data busuP reads data from bus

End of bus cycle

T1 T2 T3Tw Tw


Timings

Wait Signal Bus Cycle

A0-An

RD’

D0-Dn

Clock

The slow device can assert WAIT as long as it needs, and the uP will

wait

T1 T2 T3

WAIT

Backup


Watchdog Timer

CPU

WatchDog

Data, Address Bus and Cntrl

Reset

RSTGlue logic

Restart

What kind of glue logic is this?


DMA’s

• Direct Memory Access (DMA)• Circuitry that can read/write data

to/from an IO device and memory• Independent from processor

• Need to have arbitration between DMA and processor


DMA

RAM

IO

CPU

DMA

Address Bus (rd/ wr/)

Data Bus

DMAREQ

Bus ACKBus REQ


DMA Timing

A0-An

D0-Dn

Read

DMA Request

Bus Request

Bus Ack

WriteIO Device drives

the data busDMA drives the data bus

DMA drives IO device address on

the bus

DMA drives memory device address on the

bus

compe 460 real-time and embedded systems

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