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1126 IEEE TRANSACTIONS ON CONTROL SYSTEMS TECHNOLOGY, VOL. 18, NO. 5, SEPTEMBER 2010

Comparison of Hybrid Control Techniques for Buckand Boost DC-DC Converters

Sébastien Mariéthoz , Member, IEEE , Stefan Almér, Mihai Bâja, Andrea Giovanni Beccuti, Diego Patino,Andreas Wernrud, Jean Buisson, Hervé Cormerais, Tobias Geyer , Member, IEEE , Hisaya Fujioka , Member, IEEE ,

Ulf T. Jönsson , Member, IEEE , Chung-Yao Kao , Member, IEEE , Manfred Morari , Fellow, IEEE ,Georgios Papafotiou , Member, IEEE , Anders Rantzer , Fellow, IEEE , and Pierre Riedinger

Abstract—Five recent techniques from hybrid and optimal con-trol are evaluated on two power electronics benchmark problems.The benchmarks involve a number of practically interesting oper-ating scenarios for fixed-frequency synchronous dc-dc converters.The specifications are defined such that goodperformance can onlybe obtained if the switched and nonlinear nature of the problem isaccounted for during the design phase. A nonlinear action is fea-tured in all methods either intrinsically or as external logic. The de-signs are evaluated and compared on the same experimental plat-form. Experiments show that the proposed methods display highperformances, while respecting circuit constraints, thus protectingthe semiconductor devices. Moreover, the complexity of the con-trollers is compatible with the high-frequency requirements of theconsidered application.

Index Terms—DC-DC, hybrid control, model predictive control(MPC), robust control, sampled data control.

I. INTRODUCTION

THIS PAPER presents an investigation of new hybridtechniques for the synthesis of high performance con-

trollers for the fixed-frequency buck (step-down) and boost(step-up) dc-dc converters. The proposed circuits present anumber of challenges, starting with the switched nature of the system dynamics, which directly accounts for their hybrid

Manuscript received March28, 2008; revised January 20, 2009; accepted Au-gust 05, 2009. Manuscript received in final form October 19, 2009. First pub-lished December 15, 2009; current version published August 25, 2010. Recom-mendedby AssociateEditor F. Vasca. This work wassupported by theEuropeanCommission Research Project FP6-IST-511368 Hybrid Control (HYCON).

S. Mariéthoz, S. Almér, and M. Morari are with the Automatic Control Lab-oratory, ETH Zürich, Physikstrasse 3, CH-8092 Zürich, Switzerland (e-mail:[email protected])

U. Jönsson is with the Optimization and Systems Theory, Royal Institute of Technology, 10044 Stockholm, Sweden.

M.Bâja,J. Buisson, andH. Cormeraisare with theSUPELEC/IETR,F-35576Cesson-Sévigné Cedex, France.

D. Patino and P. Riedinger are with the CNRS-CRAN, Nancy Université,54516 Vandoeuvre les Nancy, France.

A. Wernrud and A. Rantzer are with the Department of Automatic Control,Lund University, SE 221 00 Lund, Sweden.

H. Fujioka is with the Graduate School of Informatics, Kyoto University,Kyoto 606-8501, Japan.

C.-Y. Kao is with the Department of Electrical Engineering, National SunYat-Sen University, Kaohsiung 80424, Taiwan.

T. Geyer is with the Department of Electrical and Computer Engineering,University of Auckland, Auckland 1502, New Zealand.

A. G. Beccuti and G. Papafotiou are with the ABB Schweiz Corporate Re-search, Segelhofstrasse 1K, Baden 5 Daettwil, Switzerland.

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TCST.2009.2035306

characteristics. Even if the classic averaging approach [1] wereto be applied, the resulting model of the boost converter wouldstill be nonlinear, and the non-minimum phase behavior andinput/state constraints additionally complicate the controllerdesign process. In classical approaches, the non-minimumphase behavior of the boost converter and the maximum admis-sible current constraint of both buck and boost converters havebeen successfully dealt with by reducing the feedback gain or

by employing cascaded voltage and current control [2]. Theformer solution reduces the controller dynamic performance,while both voltage and current transducers are necessary forthe indirect control approach. The recent past has seen theemergence of digital control [3]–[11] as an increasingly viableoption for power electronics. The corresponding availability of computational power has created interest in the investigation of alternative and innovative control methods that could overcomethe limitations of classical approaches.

In the context of this work, five different design methods havebeen derived and evaluated on the same experimental platformsunder a variety of operating conditions by considering response

times and disturbance rejection capabilities. In particular, threeof the five design methods are applied to both the buck and boosttopologies, while one method is applied only to the buck and oneonly to the boost topology. The benchmark examples investi-gated in this paper were first defined in [12] and [13] whereto theinterested reader is referred for a comprehensive survey of re-lated works in the power electronics area. The main objective of this paper is to introduceandcompare new control approaches tothe power electronics field that allow systematic controller syn-thesis. All relevant parameters, test scenario and correspondingMATLAB simulation scripts are available for comparison withother approaches at the following URL [14].

The various control methodologies that are summarized

in Table I are presented by five research groups, identifiedaccording to their affiliations (CRAN, ETH, KTH, LTH, SUP-ELEC). CRAN considers a new approach for model predictivecontrol (MPC) where a one-step Newton algorithm is used totrack a reference trajectory. The reference trajectory is updatedby an adaptive loop. ETH utilizes (hybrid) piecewise affine(PWA) approximations of the converter dynamics within anexplicit model predictive control framework inclusive of dutycycle and inductor current constraints. The KTH team uses anextension of sampled data -control theory to pulse widthmodulated systems. An outer feedback loop takes care of stateand control constraints and averaged sampling is used in order

to achieve robust tracking. LTH employs the relaxed dynamic1063-6536/$26.00 © 2009 IEEE



MARIÉTHOZ et al.: COMPARISON OF HYBRID CONTROL TECHNIQUES FOR BUCK AND BOOST DC-DC CONVERTERS 1127

TABLE ISUMMARY OF ASSOCIATIONS BETWEEN GROUPS, METHODS, AND BENCHMARK

PROBLEMS; DPWM INDICATES DISCRETE-TIME APPROACHES BASED

ON PWM, CD CONTINUOUS-TIME APPROACHES BASED ON

DIRECT SWITCH CONTROL

programming formulation from [15], where it is possible totake state and control constraints into account. The approxi-mate optimal controller provides guaranteed robustness andstability margins. SUPELEC employs a stabilizing approachusing a Lyapunov function deduced from energetic considera-tions to obtain the Boolean value of the control variable. Fourapproaches are of discrete-time nature (CRAN, ETH, KTH,LTH), where the converter switches are controlled throughthe duty cycle of a pulse width modulator (PWM), while theSUPELEC approach is of continuous-time nature, where theswitches are directly controlled through a binary variable.

This paper is organized as follows. Section II presents thebuck and boost converters, whereas Section III formally de-fines the associated control problem. The approaches proposedby the different groups are detailed in Section IV. Implemen-tation issues are addressed in Section V. Experimental resultsare displayed in Section VI and finally conclusions are drawn inSection VII.

II. CONVERTER DESCRIPTION

A. Topologies

The system schematics are shown in Fig. 1. The convertersare supplied by an unregulated dc voltage source and theyprovide a regulated dc voltage to a variable ohmic load. Theconverters comprise each an inductor , a capacitor , anda switching cell. The synchronous buck converter under in-vestigation is composed by two MOSFET switches and

which are operated synchronously. The boost converter iscomposed by the MOSFET and the diode . The coilvalue and the minimum load current are such that the coil cur-

rent does not reach zero in normal operation and the converteralways operates in continuous conduction. The switching cellstherefore only present two modes of operation for both cases.

B. Physical System Phenomena

The converter behavior during the switching is complex anda model reproducing precisely the system behavior would com-prise several stray inductors associated to the connecting tracksand cables and also the parasitic capacitors mainly associated tothe semiconductor devices. The coil is highly nonlinear and dis-plays hysteretic behavior due to the magnetic cycle of its core.In normal operation, these phenomena are however mostly neg-

ligible at the control level and therefore not taken into accountin the following.

Fig. 1. Converter system.

Fig. 2. Lumped parameter circuit used for control synthesis.

C. Lumped Parameter Model

The coil nonlinearities are neglected as in normal operationthe control scheme must prevent entering the saturation region.The switches are also considered as ideal. At each switching

instant, the stray inductors and parasitic capacitors cause an os-cillation that typically cannot be captured by the control schemeor that simply appears as noise. These phenomena are thereforealso neglected. The circuit models that are obtained after thesesimplifications are the lumped parameter switched models rep-resented in Fig. 2: represents thelinear inductance value asso-ciated to the coil , whose losses are accounted for by , andand , respectively, represent thecapacitance andequivalent se-ries resistor (ESR) of . The circuits are thus lumped in that thelosses have been concentrated in the parasitic values and .Additionally, denotes the output load resistor. The switchingstages of the converters are formalized through the switchrepresenting the dually operated semiconductor components.

By defining as the state vector, whereis the inductor current and the capacitor voltage, and




with a given duty cycle for the th period, the systemsare described by the following pair of affine continuous-timestate-space equations:

.(1)

where the first equation holds when is in the position (re-spectively, ) for the buck (respectively, boost) and the secondwhen it is in the position (respectively, ) for the buck (re-spectively, boost). The matrices , , , and are given forthe buck by

(2)

(3)

and for the boost by

(4a)

(4b)

(5)

The output voltage across the load is expressed as afunction of the states through

.(6)

where

(7)

for the buck and

(8a)

(8b)

for the boost.

D. Modulation Scheme

The converter switch control signal must be driven by a pulse

sequence in order to maintain the output voltage average value.PWM is employed for most control schemes (CRAN, ETH,KTH, LTH). In that case, the converter operation is charac-terized by the constant switching frequency , (switching pe-

riod ) of the PWM, which is equal to the controller samplingfrequency (sampling period ). The dc component of theoutput voltage is then regulated through the duty cycle ,which is defined by , where repre-sents the interval within the th switching period during which

is in the position for the buck converter, respectively, forthe boost.

The approach presented by SUPELEC directly controls theswitches through a Boolean variable, thus the sampling fre-

quency and the switching frequency are in general notequal.

III. CONTROL PROBLEM

The main control objective is to steer the dc component of theoutput voltage to its reference value . The output voltagemust be maintained in the face of measurable voltage sourcevariations and immeasurable load changes. This objective issubject to hard constraints that must be enforced by the con-

trol as follows:1) a limit is imposed on the inductor current as a safety

measure to avoid saturation and semiconductor damages;2) when the control input is a PWM duty cycle , it must

satisfy the physical constraint .1

There are also other constraints, which restrain the controllerstructure as follows.

1) The switching frequency has an upper bound in order to re-spect the converter maximum rating (such as thermal lim-itations) and a lower bound to respect the output voltageripple bound ( in our case):• for the approaches relying on PWM this constraint is

inherently enforced;• for the other approaches the switching criterion mustenforce this frequency constraint.

2) The quantities that can be measured and used for controlfeedback are the source and output voltages and the currentof the inductor.

3) The design must be robust to variations in the voltagesource and load and to parametric uncertainty.

4) The controller must be simple to implement and should notrequire excessive computation times.

The five design methods presented in Section IV will be de-rived and assessed on the basis of the above specifications inSections VI-A–VI-E.

IV. CONTROL METHODS

Analysis and design of dc-dc converters are normally doneusing small signal approximations of averaged models [1]. Theaveraging technique is convenient to use but it offers only alow frequency approximation of the true dynamics where thediscontinuous effect introduced by the switching is ignored.A number of alternative modeling techniques summarized inTable I will be discussed in this section including several typesof PWA models and a sampled data model.

A. Adaptive-Predictive Control Approach (CRAN)

MPC offers attractive solutions for the regulation of such hy-brid systems. This control methodology has reached a certainmaturity which is witnessed by its successful implementationin industry and by the development of a theoretical foundationin many books and articles, see, for example, [16]–[18] and thereferences therein. We consider the MPC scheme presented inFig. 3, where the control law is implemented using PWM asdiscussed in Section II-D and where all other blocks will be de-scribed below.

The method presented in this subsection is applied to the buckconverter, thus as mentioned in Section II-C ,

, and we will only use and to simplify

1In practice the interval is even smaller in some case to maintain proper gatedriver operation and avoid narrow pulses




Fig. 3. CRAN predictive control scheme overview.

notations. The approach can however be extended to the boostcase using an average model obtained from the convex hull of all vector fields, i.e.,

, The operating points of theconverter are then determined as the equilibrium points of [19].

1) Generation of the Reference Trajectories: Starting from

initial state, the goal being totrack the outputreference ,the first objective is to generate a feasible reference trajectory

from the identified system (1), which will be used as thereference to track in the predictive control part. This indirectapproach is motivated by the fact that it is easier to tune thecontroller to track a feasible precomputed response (i.e., to filterreference trajectories that are not feasible, such as steps, in orderto improve the system response) than to respond to an infeasible

step.Assuming that the state of the buck converter is periodic at

steady state, its average value over a switching-period can beconsidered constant [20]. The duty cycle in the steady-state

can therefore be computed from the average model

(9)

At steady state, and for a given average reference, the duty cycle is deduced from (9) by

(10)

The corresponding state value at the beginning of the period iscomputed from (1)

(11)

From and , a reference trajectory can be defined.Using the notation and ,

the state at the instant can be computed as

(12)In order to obtain the duty cycle , a one step recedinghorizon procedure is used. Thus, we minimize the followingquadratic error:

(13)

with respect to the duty cycle variations. Here is a quadratic norm, is a

positive-definite matrix, and is a positive constant.The optimization problem (13) can be solved either analyti-

cally from the necessary condition

(14)

or using a Newton algorithm.The constraint is checked a-posteriori.

When is not satisfied, a new duty cycle mustbe computed as

(15)

The optimal duty cycle is the result of the optimizationshown before. is only used to compute the trajectory

. This state will be used as a reference for the predic-tive control.

2) Predictive Control: Oncethe reference trajectory

is available, a classical tracking problem should be solved.We consider a prediction–correction structure as the control

strategy for the buck converter. The control is determined byminimizing a quadratic function of the prediction error betweenthe reference trajectory and a predicted state .A correction using past measurements is used to reduce the sen-sitivity to the noise and the unmodeled parameters. The functionto be minimized is

(16)

and the minimization is done with respect to the duty cycle vari-

ations . In the definition of , is a pos-itive constant and is a positive definite matrix. The predictedstate is obtained at from as

(17)

where is the measurement from the real system, indicatesthe future states without correction

(18)and is a correction term of the form

(19)

where is the observer gain. Although the systemswitches, its dynamics does not change , which im-plies that can be easily computed using a pole placement.

The minimization of can be done analytically fromor numerically using the Newton algorithm

with only one iteration. This control is applied to the identifiedsystem and the real system in order to obtain , andfor the next period.

3) Load Observer: Load estimation should be done in order

to ensurerobustness of thecontrol law. Besides, in the predictivecontrol, the values of the identified parameters should be near




Fig. 4. ETH explicit model predictive control scheme overview.

the values of the real parameters in order to obtain an accurateprediction.

The identification process can be written as a least-squaresoptimization problem of a quadratic function

(20)

We can use a simple gradient algorithm to obtain the value of

the load.

B. Concept Overview

1) Explicit Model Predictive Control: The major advantageof MPC is its straightforward design procedure. Given a dis-crete-time control model of the system, including constraints,one only needs to set up an objective function that incorpo-rates the control objectives [21]. The control action at each timestep is then obtained by measuring the current state and min-imizing the objective function over a finite prediction horizonsubject to the equations and constraints of the model. The firstvalue stemming from the predicted optimal sequence of con-

trol inputs is then applied to the system and the procedure isrepeated at the successive sampling instant. Depending on themodel and on the length of the prediction horizon used in the ob-

jective function, this minimization problem varies considerablyin complexity. For PWA linearly constrained systems with costfunctions based on one or infinity norms, this optimal value isPWA and it can equivalently be obtained through an explicit so-lution approach, through which the optimization problem is pre-solved offline for every possible instance, rendering a look-uptable which is searched online to directly yield the desired op-timal input [22]. This bears the advantage of avoiding the needto perform any online optimization, thus making the MPC par-adigm applicable also for systems with shorter sampling times

or with limited computational power.2) Constrained Finite Time Optimal Control (CFTOC) for

DC-DC Converters: The proposed MPC scheme implies theformulation of a CFTOC problem to be solved with a recedinghorizon policy. Assuming that a discrete-time control model of the dc-dc converter is available (see Sections IV-B3 and IV-B4,respectively, for the buck and boost topologies), in the followingthe derivation of a cost function capturing the required objec-tives is presented and the explicit solution procedure of the re-sulting optimization problem is briefly presented.

The control objectives are to regulate the output voltage toits reference as fast and with as little overshoot as possible,

or equivalently, to minimize the absolute scaled output voltageerror , where and

: the scaling of the values over will bemade clear in Sections IV-B3 and IV-B4. Let

indicate the absolute value of the difference betweentwo consecutive duty cycles. This term is introduced in order toreduce the presence of unwanted chattering in the input whenthe system has almost reached stationary conditions by penal-

izing any additional variations in the duty cycle. Define thepenalty matrix with and thevector . Consider the objective func-tion

(21)

penalizing the predicted evolution of from over thehorizon using the 1-norm. The control input at time-instant

is then obtained by minimizing the objective function (21)over the sequence of duty cycles

subject to the model equations and constraints featured inSections IV-B3 and IV-B4 and the current limitation

, where ; the resulting problem isreferred to as the CFTOC problem.

Multi-parametric programming is employed to solve thisoptimization problem offline for a range of parameters. In[23] it is shown how to reformulate and solve a discrete-timeCFTOC problem as a multi-parametric program featuring thestate vector as a parameter, yielding an explicit state-feedbackcontroller. Note that the CFTOC problem is not only a functionof , but also of the last control move ; furthermore,as it is necessary to solve the CFTOC problem for all possiblevalues of and , the scaled output voltage reference

and inductor current maximum limit also enter the augmentedstate vector, which therefore is 5-D. As proven in [23] theoptimal state-feedback control law is a PWA function of the (augmented) state vector defined on a polyhedral partitionof the feasible (augmented) state space, commonly referredto as a lookup table. As mentioned in Section IV-B1, such alookup table facilitates implementation, since computing thecontrol input amounts to determining the polyhedron in whichthe measured state lies and then simply evaluating the corre-sponding affine control law. Additionally, the derived feedbackcontroller allows deriving an explicit representation of theclosed-loop system, for which a Lyapunov function certifying

exponential stability can be sought a posteriori through themethod presented in [24].In order to avoid introducing additional complexity into the

CFTOC problem posed above, load variations are dealt with byusing the state-feedback controller (derived for a time-invariantand nominal load), to which a loop comprising a Kalman filterthat features a correcting integral action [25], [26] is added. Forthis, the reformulated (nominal) continuous-time model is aug-mented by a third state that tracks the output voltage error, andthe Kalman filter is used to estimate it. In a last step, the outputvoltage reference is adjusted by the tracked voltage error.The overall control structure is shown in Fig. 4.

3) Control Model Derivation for the Buck Converter: Poly-

hedral PWA systems are defined by partitioning the state-spaceinto polyhedra and associating with each polyhedron an affine




state-update and output function [27]. In previous publications[8], [28]–[30] the notion of the -resolution model was intro-duced as an effective way to describe the switched hybrid dy-namics of the buck converter. This modeling approach leads toa discrete-time PWA converter model that is valid for the wholeoperating regime of the system and provides a direct tradeoff

between the accuracy of the obtained model and its related com-plexity through the choice of the resolution . As shown in[26], the converter PWA model uses a transformed converterstate vector comprising theinductor current and the output voltage, both scaled over thevoltage source: since appears as a linear term in the systemequations, it is effectively removed from there so that it does notshow up in the control model and therefore does not have to beincluded as a separate parameter in the explicit state-feedbackcontroller.

For , the discrete-time PWA state-update map of the-resolution model amounts to

(22)

(23)

with , and . Since(22) refers to the transformed state vector, the matrix and vector

and are different from the ones in (1) and (2); see [26] forexact expressions. The discrete-time control model of the buckconverter employed in Section IV-B2 for the derivation of the

associated CFTOC problem is thus represented by (22) and (23).4) Control Model Derivation for the Boost Converter:

From an implementation point of view, it is preferableif all the states used in the prediction model are directlymeasurable. Thus, the capacitor voltage is replaced by theoutput voltage in the state vector which leads to setting

by correspondingly reformulating(1). Additionally, to obviate the requirement of accountingexplicitly for voltage source variations, is removed fromthe model equations by redefining the scaled state vector

, similarlyas in Section IV-B3.

Next, a discrete-time model is formulated by employing asampling interval equal to the switching period . The em-ployed method considers a direct least squares fitting (LSF) ap-proximation over several regions of the control input of the exactsystem update equations, yielding a PWA description of the as-sociated nonlinear expressions. These can be written as

(24)

where and are matrices that depend nonlinearlyon the duty cycle , calculated by integrating the converterequations from to . Expression(24) is approx-imated by determining the matrices , , and that de-scribe the system in terms of

(25a)

(25b)

(25c)

and that minimize the sum of quadratic error terms

(26)

over a gridded series of points in the state space

, where are the intervals

, and , are thelimit values of the scaled inductor current and output voltageover the considered range. The discrete-time control model of the boost converter employed in Section IV-B2 for the deriva-tion of the associated CFTOC problem is thus represented by(25a)–(25c).

It should be highlighted that because of the nonminimumphase behavior of the boost converter a considerably longerhorizon length is chosen than for the buck to capture the in-

verse step response and account for it within the optimizationhorizon. As this would increase the complexity of the problemconsiderably, a simple move-blocking scheme is used whereby

throughout the horizon.

C. Sampled Data Control for Robust Tracking (KTH)

Discrete time models of dc-dc converters have an advantageover conventional averaged models since they take the switchednature of the plant into account and therefore have potentialfor better performance. However, the discrete time model hasa drawback since it only describes the state at the switching in-stants. Since the inter sampling behavior is not accounted for,

control design based on the discrete time model may lead to sub-harmonic oscillations, where the period of the (periodic) steady-state solution is larger than the switch period (see [31] for an ex-ample in the model class considered in this paper).

1) Sampled Data (SD) Model: The fact that a subharmonicsolution may appear suggests that the discrete-time model is in-sufficient. We therefore consider design based on a SD model.The SD model gives a precise description of the state at theswitching instants, but also includes a lifted signal which de-scribes the inter sampling behavior. Thus, the SD model allowsthe effect of continuous time disturbances and model uncer-tainty to be represented exactly in an equivalent discrete-timemodel.

Within the SD framework we consider synthesis and wetherefore include an external disturbance in the system dy-namics. The disturbance is chosen as an independent currentsource at the output to model uncertainty in the load.

The SD model is of the form

(27)

where is the system state, and

are lifted versions of the performance output and the distur-bance signal (see Fig. 5). Several operators that appear in




Fig. 5. (Left) Sampled signal x [ k ] and (right) lifted signal ^x [ k ] ( ) .

the lifting representation are mappings between function spaces.We have

where the dependence on is nonlinear.The signal is the input to the controller available at

time . The input to the controller consists of two parts.is obtained by sampling the state andis obtained by sampling the output voltage

using a so-called average sampler which is defined as

The average sampler is introduced to ensure that the outputvoltage tracks the voltage reference . Without the averagesampler it is not possible to make the tracking robust againstparameter variations, see [32] for a discussion. At steady statewhen the duty cycle is constant, the state of a dc-dc converter

will attain a periodic solution such that the average of thevoltage equals . The control objective is to ensure asymp-totic convergence to this nominal -periodic solution (andcorresponding stationary duty cycle) which satisfiesthe tracking condition

(28)

where is the periodic output voltage corresponding to . Wewant to satisfy (28) robustly against, e.g., parameter uncertain-ties and the disturbance . This motivates us to introduce theintegrator state

and consider the objective of satisfying

(29)for all and for all solutions to the converter dynamics.The chosen performance output defines the cost function andis used to tune the controller.

The criterion (29) can be equivalently stated as a dis-crete-time optimization problem by using the lifted system

representation (27). However, the problem is highly nonlinearand in general intractable for optimization. In the sequel, we

Fig. 6. Sampled data feedback control configuration.

therefore consider a linearization of (27) together with a linearquadratic approximation of (29). This results in a new type of sampled data control problem which was solved in [32].Depending on the measurements available, the solution yieldseither a state feedback vector or a dynamic output feedback con-troller.

2) State and Input Constraints: The sampled data controlleris surrounded by an outer loop which, if necessary, will adjustthe duty cycle and system state. The outer loop is motivated bya number of reasons. First, the SD controller has integral ac-tion and we therefore add an anti-windup structure. If the linearfeedback saturates, then the term

is used to modify the integrator state in a linear fashion

where . Second, the state constraint is not con-sidered in the SD synthesis and needs to be dealt with by someadditional control structure. We add a one-time step MPC algo-

rithm which (if necessary) adjusts the duty cycle and which canbe implemented as a nonlinearity, see [13] for details. Finally,the SD controller is designed for a fixed nominal input voltage.Changes in the input voltage are handled by the integrator state,but the response is made faster by using measurements of theinput voltage in a feed forward fashion. We note that the outerloop remains inactive under normal operation.

3) Application to the Buck Converter: For the buckconverter,we assume we have access to the full state and consider the(approximate) sampled data problem discussed above. Thesolution yields a linearfeedback vector which is implementedwith the integrator as illustrated in Fig. 6. We note that if the full

state were not available, the problem formulation wouldyield a dynamic output feedback controller.4) Application to the Boost Converter: The output voltage of

the boost converter is non-minimum phase with respect to theduty cycle. This problem and the problem of multiple steady-state equilibriums can be bypassed by formulating a current(rather than voltage) regulation problem. However, in the cur-rent regulation approach one must choose an inductor currentreference that necessarily depends on the load which must beestimated.

Our goal is to achieve robustness to uncertainty and distur-bances in the load and we also want to be able to deal with morecomplex loads than purely resistive. We therefore prefer voltage

regulation. The nonminimum phase behavior of the boost canbe made less pronounced by including both the inductor current




and the output voltage in the output signal which enters in theperformance index (29).

D. Relaxed Dynamic Programming (LTH)

Except for special cases, the computations required to solvea synthesis problem by means of exact dynamic programmingare prohibitive. The only possibility is to resort to approxima-tions. The approximation algorithms that we present in this sec-tion were developed in [33], where the reader can find more de-tails. More information on relaxed dynamic programming tech-niques can also be found in [34] and [35]. The choice of algo-rithms was made for several reasons. First, an important designcriterion for the problem considered in this paper is constraintson system variables. This can be accounted for in the methodwe use. Moreover, the controller we design will approximatea stationary optimal controller. As such, it will inherit robust-ness margins from the optimal controller. Since the algorithmsin [33] require that the system dynamics is affine, we need to

approximate the converter dynamics(1) with such systems. Themodeling technique presented below, which may be referred toas a robust affine approximation, is proposed in order to takeinto account, already at the modeling stage, the switched natureof the converter and the fact that the converter is parameterizedby unknown parameters.

1) Robust Affine Model Approximation: The exactstate prop-agation between time and is given by

(30)

which can easily be found by integrating the switched dynamicsover one period. The load parameter has been appended toemphasize that the matrices depend on the load. We need toapproximate this nonlinear system with an affine system

(31)

When the model (30) is approximated with the model(31), thelargest pointwise error can be expressed as

(32)

where the supremum is taken over , whereand is the set of

states on which the model should be approximated. is the setof values that the load can assume. Naturally, we would like tominimize . The robust approximation problem is to compute

(33)

over . Our ability to solve this problem depends onthe choice of norm and the description of the set .The candidates are those that correspond to a finite dimensionalconvex optimization problem. For the purpose of this paper weshall consider a simple choice. Define a finite grid of points

, for each define

(34)

where denotes the Kronecker product of two matrices. If wealso define , i.e., the decision variables arestacked in the vector , the approximation problem becomes

(35)

which is the same as

If the norm is either or this is an LP. If the norm isthe problem is a second-order cone problem. In any case,

it is an easily solvable finite dimensional convex optimizationproblem. See [36] for a discussion on convex optimization.

2) Control Design: To simplify notation, we define. Our goal is to synthesize a feedback controller

such that the total cost is approx-imately minimized, under an additional constraint on the in-ductor current, and also . Thefollowing stage cost was used:

where and are positive weights. The penalty on consecu-tive control values was introduced to force the duty cycle to be-come constant when has reached the output reference. Thus,an extra state was introduced. We used relaxed

value iteration to solve for a stationary approximate value func-tion satisfying

where are constants and is the optimal total costfunction. The parameters and can, just as the step-cost func-tion parameters, be regarded as control design parameters. Asdecreases or increases the controller complexity decreases.Thus, the choice of these parameters is a compromise betweencomplexity and performance.

The approximate value function is given by a max of linear

functions , where is a set of vectors.The corresponding explicit PWA feedback controller is givenby , where . Tocompute the controller value at a state , we need to takethe following steps:

1) find such that is maximal;2) set .

Thus, we have to do a linear search over the table . Conse-quently, it is important to keep the table as small as possible,and for this purpose a reduction algorithm has been outlined in[33].

Finally, the errors introduced by the model approximationwere handled by an outer integrator loop that adjusts the voltage

reference. The integrator was activated only when the voltagewas sufficiently close to its reference.




Fig. 7. LTH control structure overview: an explicit control law is found from alookup table.

The complete closed-loop system is depicted in Fig. 7.

E. Stabilizing Control Approach (SUPELEC)

Unlike the previously presented methods, the stabilizing con-trol, which is a continuous time approach directly computes the

Boolean control variable (without PWM), using a common Lya-punov function candidate, such that the system is asymptoticallystable. A port control Hamiltonian (PCH) formulation which ac-counts for the system energy is used. For switching systems, thePCH formulation is written as follows:

(36)

where is the state vector containing the energy vari-ables (fluxes in the inductors and charges in the capacitors).

is the Boolean control variable. The matrix isskew-symmetric, (i.e., ) it describes the power inter-

connections of the model, is nonnegative and corresponds tothe dissipating part of the system, is the power input matrix,and represents the power sources present in the system.represents the energy stored in the system. This is also calledthe Hamiltonian of the system. If the constitutive relations of the storage elements are linear, which is most often the case inpower converters, they can be represented by the matrix andthe Hamiltonian of the system is such that

(37)

The matrix satisfies and in the simple cases,

it is also diagonal. The vector represents the costatevariables (currents in the inductors and voltages on the capaci-tors).

In the case of power converters, the state equation is affinewith respect to the Boolean variables [37]. Thus, the matrices

, , and can be written as

(38)

where are the components of the control vector and is itsdimension.

The approaches in the literature which are based on Lyapunovfunctions consider, in general, linear systems with a commonequilibrium point [38], [39]. In the case of power converters,each configuration may or may not have a different equilibrium

point and physical considerations enable establishing a commonLyapunov function. This function depends on the control objec-tive, which has to be defined first. It is obtained using the sameapproach as with an average model. Thus the control variable isno more Boolean but continuous and bounded .The control objective corresponds to an admissible reference forthe system which is defined by solving (36) for . It is avalue for the costate variable which must satisfy theconstraint

(39)

if there is a . According to the properties

of this equation and the respective dimension or and , for one, the equilibrium point can be unique or not, and for any

point of the state space can be an equilibrium point or not [40].For a function to be a Lyapunov function for a system in a

point it mustbe positive anywhereexcept in and its deriva-tive must always be negative. If such a control law is applied,then will converge asymptotically toward . The candidateLyapunov function has the form

(40)

Because the matrix is unique for all the modes of thesystem, is positive and continuous for every and it is nilonly in . Its derivative depends on the control variable andusing (36) and (38) it can be expressed as

(41a)

(41b)

Due to the fact that is a non-negative matrix, the first termis always negative. Because the sum can be madenegative by choosing an appropriate value for each Booleansuch that each product is negative. Multiple state feedbackcontrol strategies can be envisaged for attaining this goal [40].In the following a maximum descent strategy is used as it yieldsbetter results in terms of computation time due to a simpler ex-pression of the commutation surfaces. It consists in choosing, ateach time, the value of such that all the terms in the sum arenegative or zero. Commutation surfaces are then hyperplanesdefined by

(42)

In the case of the boost converter, as there is only one controlvariable, the sum from expression (41) has only one term ,which, according to (42) becomes

(43)




Fig. 8. Discrete-time implementation of SUPELEC control scheme. Controlinput is evaluated when block w 0 triggers the control law. Reference blockadjust reference trajectory for robustness to disturbance and improved transientperformance.

where the admissible reference is computed by solving (39) forthe nominal value of the output voltage .

Because this strategy requires an infinite bandwidth a dead-zone is created with the help of a parameter . This way thederivative of the Lyapunov function may take positive valuesfor a limited amount of time. The new commutation surfaces

are thus defined by . The period and the amplitude of theoscillations around the reference depend on this parameter.To ensure the robustness with regard to the parameter vari-

ations and to improve the startup performance, the admissiblereference is modified online. A new value for the current refer-ence is computed under the form

(44)

where is a parameter. is bounded between 0 and the max-imal admissible value for the current in the inductor. The dis-crete-time implementation of the control scheme is depicted in

Fig. 8.V. IMPLEMENTATION

A. Power Converters

A buck and a boost converter have been realized in order toevaluate the different control methods. Each converter is com-posed of a MOSFET power module that provides a converter legwith a low parasitic inductor. A filtering capacitor placed at theconverter supply input reduces the supply voltage fluctuations.Additionally, a small fast capacitor is placed right next to thepower module terminals in order to have a good switching cellwith a low parasitic inductor.

B. Gate Drivers

The gate drivers are used to amplify the control signalsin order to apply the appropriate voltage and current to theMOSFET gates. The driver of the transistor —the transistorconnected to the supply’s positive terminal—uses a boosttrap circuit to draw power from the auxiliary supply. As theboost trap capacitor is charged when the low transistor is on,the duty cycle has to be limited to 95% in order to ensure asufficient energy transfer. At the duty cycle lower bound, it isnot desirable to have duty cycles smaller than approximately1% as they only produce narrow pulses and converter losses.

As the two transistors are complementary an interlock time isnecessary to avoid short circuit of the leg during the transition

Fig. 9. Time diagram of the control process events.

TABLE IICONTROL ALGORITHM COMPUTATION TIME

between the two switches. This is ensured by the appropriatelogic at the cost of a small distortion in the voltage pattern.

C. Controller Hardware and Software Setup

Two DSP control boards were made available for the imple-mentation:

1) a 32 bit 225 MHz floating point DSP from Texas Instru-

ment TMS320C6713;2) a 16 bit 600 MHz fixed point DSP from Analog Device

Blackfin.The floating point platform is most convenient since it allowsfor easy translation of algorithms in C into floating point arith-metics. This limits the programming effort and reduces the riskof numerical saturation and overflow. This platform is oftenused in academia because of the above reasons. The fixed pointplatform requires more development effort in order to avoidsaturations and overflows. However it provides more compu-tation power—which was the reason to have this second plat-form—and the code can directly be used on a simple industrial

controller that does not support floating point arithmetic.On both platforms, the same C code template has been used.This template initializes the DSP and all its devices and setsup an interrupt at the sampling frequency which acquires thedata from the AD converters, runs the control algorithm andapplies the calculated duty cycle to the converter. To ensure amore consistent implementation of thevarious methods, the taskrelated to the controller synthesis thus only pertains to the partbetween the acquisition of the digitalized measurement and theapplication of the duty cycle.

D. Delay Issues

The sampling frequency is equal to the switching frequency,

20 kHz. A four channel AD converter is used to acquire andconvert the output voltage, supply voltage and coil current. The




Fig. 10. Buck converter; startup transient, and response to a step in the load resistance from r = 50 to r = 100 and back again. The experiment isperformed for three different values of the reference output voltage v . The values are 20 (black), 25 (gray), and 30 V (light gray). The experiments of the fourgroups are presented side-by-side.

duration of the analog-to-digital converter sampling and conver-

sion process is 5 s. As the 50 s sampling time is short consid-ering the computation power available for this kind of applica-tions, the duration of all control steps is crucial and representedin Fig. 9. There are four important instants which are: , thebeginning of the PWM voltage pattern; the sampling instant;

the instant when the sampled measurement is available andwhen consequently thecontrol algorithmcanstart; thenew inputis available in but is only updated in . This last aspect needssome clarification. The PWM logic would become more com-plex if the input is permitted to safely change during the periodand this would lead to a variable sampling and to phenomenawhich are difficult to tackle. This means that we must ensure

that the new input is available before (i.e., ) in orderto avoid introducing an additional delay in the control.The sampling instant and the beginning of the voltage pat-

tern are very often simultaneous, which introduces a delayof exactly one period in the control. This leaves less than onesampling period for the control algorithm to compute the nextduty ratio. This common practice was selected for all methodsin order to show that they can be implemented using a controllerof limited computation power.

E. Implementation Complexity and Computation Time

1) Qualitative Complexity Analysis: From the point of view

of the implementation, the form and complexity of the differentcontrol laws vary as follows.

1) (CRAN) The control law was obtained analytically and

features matrix exponentials. As the matrix exponentialscannot practically be used for the targeted application, theyare approximated using a second-degree Taylor series. Theapproximated control law then amounts to compute a fewmatrix and vector multiplications. The implementation of the load estimation uses a basic gradient descent algorithm.

2) (ETH) The control law amounts toevaluating affinefunctions that are 5-D, being the depth of the searchtree (5–12 in this case).

3) (KTH) The main part of the control law consists of a 2-Dstate feedback. An outer loop performs a simple test and if necessary adjusts the control to maintain the limit on the

peak current.4) (LTH) The control law amounts to evaluating affinefunctions that are 4-D, being the number of linear func-tions used to represent the approximate cost function.

5) (SUPELEC) The control law amounts to evaluating asecond order polynomial in the state variables and controlinput. As described in Section IV-E, the reference is ad-

justed online in order to increase the dynamic performanceand ensure robustness to load variations.

In addition to these specific aspects ETH, KTH, and LTH usean external integrator loop.

2) Quantitative Comparison: Four methods have been im-plemented using the 32-bit floating point DSP (CRAN, ETH,

KTH, SUPELEC) as it was more convenient. As LTH systemati-cally evaluate all regions, more computation powerwas required




Fig. 11. Buck converter; startup transient for three different values of the capacitance x (Robustness evaluation). The values are x = 0 : 5 x (black),x = x (gray), and x = 2 x (light gray), where x = 100 F is the nominal value. v = 50 V, v = 25 V, r = 50 . The group resultsare presented side-by-side.

Fig. 12. Buck converter; startup transient and response to a step in the source voltage from v = 50 V to v = 35 V and back again. v = 25 V, r = 50 .




Fig. 13. Buck converter: simulation results selected for comparison with experiments. The CRAN simulation illustrates the robustness evaluation where x =

50 F, x = 100 F, and x = 200 F. The ETH and LTH simulations shows the startup experiment with line transients from v = 50 V to v = 35 V and backagain. Finally, the KTH simulation shows the startup transient and response to a step in the load resistance from r = 50 to r = 100 and back again.

and it has been implemented on the 16-bit fixed point DSP. Fi-nally one of the four former methods (ETH) has been ported on

the fixed point DSP in order to check that the results are equiv-alent on both platforms. Table II summarizes the computationtimes defined as . These times reflects the observation of the qualitative analysis performed in Section V-E1.

VI. EXPERIMENTAL RESULTS

Definition of the Benchmarks Tests

The design methods presented in Section IV have been vali-dated on an experimental platform with the following nominalparameter values 100 F, 2 mH, 0.1 and

0.5 . For PWM based methods, the switching frequencyis 20 kHz. The nominal source voltage is 25V for the buck and 50 V for the boost. The control objec-tive is to keep the output voltage at the reference level,25 V for the buck, 50 V for the boost, and to make surethat the inductor current does not exceed the limit 2.5A. The nominal load is 50 for the buck and 200for the boost.

A few relevant performance indices were selected for thebenchmark as follows:

1) startup transient; this is a good indicator of the generalperformance of the controller;

2) load transient; the load is subject to large variations during

operation and therefore the load transient is a good indi-cator for DC-DC converters;

3) line transient; the supply voltage is subject to large varia-tions during operation;

4) robustness to parameters which are not well known andaffect the dynamics (capacitor, inductor);5) computation time.

Some measurements were grouped to limit the number of pre-sented plots as follows:

1) startup and load transients are shown on the same plotfor three different reference voltages in Figs. 10 and 14,side-by-side for the different groups;

2) a robustness evaluation is shown in Figs. 11 and 15, wherethree different filter capacitors are used during the startuptransient;

3) startup and line transients are shown in Figs. 12 and 16.

A. Methods’ Specific Parameters for the Buck Topology

1) CRAN: The parameters for the method are

(45)where the (2,2)–blocks of the matrices and are chosenrelatively large to ensure tracking of the output voltage refer-ence.

2) ETH: The model (22) with was employed for thecontroller synthesis. For the cost function, the penalty matrixwas chosen to be and the prediction horizon

. As explained in Section IV-B the explicit state-feedback

controller is defined in a 5-D space, with a polyhedral partitionfeaturing 105 regions.




Fig. 14. Boost converter: startup and load transient. At time t = 25 ms, a load step from 200 to 100 is applied. At time t = 35 ms a step back to the initialvalue is applied. v = 15, 20, 25 V, v = 50 V.

3) KTH: To ensure robust tracking of the output voltage ref-erence, the signal in the cost criterion (29) was chosen as

and the weights were chosen as and .

The corresponding linear quadratic approximate problem wassolved and a feedback vector was obtained. As explainedin Section IV-C, the feedback was implemented with an antiwind-up structure where the gain was .

4) LTH: The weights in the step-cost function were chosenas . An approximate cost function was foundafter 23 value function iterations, with relaxation parameters

and . After reduction, the size of the resultinglookup table was 102.

B. Methods’ Specific Parameters for the Boost Topology

1) ETH: The model (25) was derived with PWA

dynamics, with the intervals being , , and. For the cost function, the penalty matrix was chosento be and the prediction horizon . Asexplained in Section IV-B the explicit state-feedback controlleris defined in a 5-D space, with a polyhedral partition featuring122 regions.

2) KTH: The nonminimum phase characteristics of theboost converter imply that the current should be included inthe cost criterion. Thus, the signal in (29) was chosen as

. The weights were chosen to be ,and the anti wind-up gain was chosen as .

3) LTH: The weights were and an approximatecost function was found after 38 value function iterations

with relaxation parameters and . After reduc-tion, the size of the lookup table was 130.

4) SUPELEC: A discrete-time version of the control lawfeatured by (43) was implemented with the maximum achiev-able sampling rate, 120 kHz. The period and the amplitude of

the oscillations around the reference depend on the parameter ,which was tuned to the value in order to respect the max-imum admissible switching frequency and the maximum capac-itor voltage ripple.

C. Experimental Results Evaluation for the Buck Topology

All control methods globally fulfill the objective. Theyquickly reach the desired reference while respecting the currentlimitation. We will here analyze the experimental results andremark on some similarities and distinctions.

The methods display a different degree of conservativenessregarding the current constraint. The current is more or less kept

at its limit during the transient and the variation is mainly de-pending on the method aggressiveness (flatter most varying:LTH, ETH, KTH, CRAN). Some violation of the current con-straint can be observed for CRAN.

The startup swiftness varies according to the way thecurrent constraint is applied (faster slower: KTH–ETH/ LTH–CRAN). A little overshoot can however be observedduring the startup in the methods by ETH/KTH. This is causedby the outer integral loop.

It can be observed as a general trend that the voltage deviationduring the load transient is small and increases with the outputvoltage, see Fig. 10. The maximum voltage deviation during theload transient is: CRAN 0.4 V, ETH 0.5 V 0.4 V, LTH

0.5 V, KTH 0.7 V 0.5 V. CRAN uses a load observer andtherefore reaches steady-state faster after a load transient.




Fig. 15. Boost converter: robustness evaluation. Startup transient for three different values of capacitor: x = 50, 100, 200 F. v = 20 V, v = 50 V, r =

200 .

All methods are robust to a large capacitor variation, seeFig. 11. No significant deviation from the nominal behavioris observed. As for the nominal startup transient a more pro-

nounced overshoot due to the gain of the outer integral loop isobserved for ETH/KTH.

The voltage deviation during the line transient mainly de-pends on how the supply voltage is accounted for in the control,see Fig. 12. The maximum voltage deviation during the loadtransient is: ETH 0.2 V, LTH 0.2 V 0.55 V, KTH 0.45V 0.55 V, CRAN 0.45 V 0.9 V. ETH scales the state overthe input voltage, which makes the controller less sensitive tothe supply transient.

Some simulation results have been selected in Fig. 13. Thesimulations feature the same operating conditions as the exper-iments and have been performed in MATLAB using the model in

Section II-C with the above nominal values and with delay dueto measurement, conversion, and computation included in themodel. The simulations show close agreement with the exper-iments and only small differences can be observed when somevery fast phenomena occur.

It has to be noted that even if the different controllers arebased on different approaches, their performances are very sim-ilar. An analysis of the results show that most differences arenot critically related to the selected approach. Some factors thataffect the results can be identified as follows.

1) Controller Structure: A part of the control characteristicsis related to the control structure, such as the use or absenceof observer in the loop or how the supply voltage is accounted

for. The observer was necessary to obtain good results with theCRAN approach and the input voltage scaling reduced the sen-

sitivity to input voltage changes in the ETH method. However,both the observer and the scaling idea are not specifically linkedto one approach and could be used together with all methods

with minor modifications, thus leading to different results.2) Controller Tuning: A different tuning could have lead to

another classification of the methods independently of the struc-ture of the control. It is moreover difficult to obtain a controllerthat has good ratings for all performance indices.

3) Outer Integral Loop Tuning: There is unavoidable uncer-tainty linked to the model structure and the parameter values.Several methods use an additional integral loop to compensatefor this uncertainty and this loop is mainly responsible for theobserved overshoot and the slow compensation of static errors.

4) Noise Sensitivity: The results are significantly affectedby the tradeoff between aggressiveness and sensitivity. This is

particularly critical for power electronics applications since thelevel of noise is relatively high. The noise is even more pro-nounced in our experimental setup where the long wires usedto access some measurements propagate noise on the controlboard.

5) Platform: Duty cycle measurements that were obtaineddigitally through the DSP (ETH/LTH) also display a higher sen-sitivity due to the higher accuracy of the measurement and toa larger measurement bandwidth (respectively, 1 MHz and 50kHz).

6) Time Available for the Tuning: Finally, the time availablefor the controller tuning was not the same for all groups due

to scheduling and geographic contingencies as the experimentswere all performed at ETH.




Fig. 16. Boost converter: startup and line transient. At time t = 25 ms a step-down from v = 25 to 15 V is applied on the supply voltage. At time t = 35 ms astep-up to the initial value is applied. v = 50 V, r = 200 .

D. Experimental Results Evaluation for the Boost Topology

The experimental results that are shown in Figs. 14 and 15are similar to the buck case. As for the buck case, the differencemostly stem from aspects not directly related to the control ap-proach and they are not discussed further here, except for thestabilizing control approach which is also based on a differentswitching approach.

In this latter approach, the control variable is directly booleanand the notion of duty cycle has therefore no meaning. Never-theless, for the sake of comparison and due to visibility issues,the evolution of the control variable is shown as an instantaneousduty ratio in Figs. 14–16. The instantaneous duty ratio is com-puted offline based on the control signal, in a similar way withthe definition of the duty cycle from Section II-C. It is the ratiobetween the period when the switch is on the position,and the period between two consecutivecommutationsfrom to . As all these periods are multiples of the samplingperiod, the instantaneous duty ratio takes only discrete values inthe interval .

For the sake of comparison some simulations were addition-ally performed based on the conducted experimental scenarios,

although due to space limitations it was not possible to featureall cases; the simulation was carried out in MATLAB by directlyusing the model presented in Section II-C with the above nom-inal values and accounting for the delay due to measurement,conversion and computation. The chosen plots are displayed inFig. 17, where in particular one scenario is presented for eachcontroller. The first column shows the results obtained with theETH controller for the line transient, where the simulated evo-lution overall mirrors the corresponding experimental sequenceof values. The second column features the plots derived withthe KTH controller for the load transient. Here, the simulatedstates correspond well with the experiment, albeit with a slightlyless pronounced chattering in the duty cycle. The third columncontains the simulated evolution of the LTH controller for thevoltage supply variation: as previously mentioned, it is believedthat the difference between simulation and experiments is dueto quantization errors and noise. Finally, the last column por-trays the values obtained with the SUPELEC controller for thecase of varying capacitor values. The same dependence betweenthe speed of convergence and the capacitor values can be ob-

served. The differences observed between the simulated and thereal transient and amplitude of oscillations on the current are




Fig. 17. Boost converter: Selected simulation results for comparison with experiments.

due to the inaccuracy in the value of the physical parametersand to the measurement noise.

As a general remark, the obtained simulation results quali-tatively resemble the experimental values and corroborate the

validity of the proposed controller synthesis approaches, whichare based on the schematic approximation of the physical circuitgiven in Section II-C.

VII. CONCLUSION

Five control methods from hybrid and optimal control havebeen successfully applied to fixed frequency dc-dc buck andboost converters and compared through experimentation.

The methods presented by ETH, LTH, KTH, and CRANall act at the beginning of each switching period and use theduty cycle as the manipulated variable, rendering a constantswitching frequency operation; the former two allow for a

more systematic modeling of the circuit characteristics buttypically yield an increased degree of complexity in the con-troller, whereas the third might be suitable for higher switchingfrequencies in view of its more affordable implementationrequirements, as reflected by the associated computation times.The method of SUPELEC, on the other hand, directly decideson the discrete position of the controlled switch based on amuch faster sampling of the system, and results in a schemewith an improved reaction time to disturbances, but also re-quires a higher measurement bandwidth and results in a variableswitching frequency.

The methods described in this paper allow to impose con-straints such as the limitation of the coil current, in order to

avoid core saturation and to protect the semiconductor devices.The constraints are respected either intrinsically or with the help

of an external logic. In all cases, it has to be observed thatsome nonlinear control action is necessary in order to obtain aclosed-loop system that respects the state andcontrol constraintswithout sacrificing too much in performance.

The methods perform similarly well and display an excel-lent dynamic performance. Most differences that have been ob-served are related to the tuning of the controller or to additionalcontrol functions that are not linked to a specific approach ex-cept for SUPELEC where the faster reaction to disturbances isinherent to the direct control approach and the higher samplingfrequency. The complexity of the approaches is compatible withthe high-frequencies required by power electronics applications.In particular, the sampled data approach investigated by KTH iseasy to implement and allows fast sampling rates to be consid-ered. The model predictive control suggested by ETH and therelaxed dynamic programming approach by LTH allow a moresystematic treatment of the nonlinear design constraints but maylead to increased yet manageable complexity of the resultingcontroller. A linear approximation was necessary in order toimplement the predictive control of CRAN and more extensivetuning than the other approaches was required. The stabilizationapproach investigated by SUPELEC required a modification inorder to increased dynamic performance.

In principle, the methods can be applied in a systematicfashion to more complex control problems. Possible futuredirections would be to investigate how the methods can beextended to consider higher dimensional converter topologies.

In order to compare and extend the presented results to othercontrol approaches, all relevant parameters, test scenario and

corresponding MATLAB simulation scripts have been madeavailable at the following URL [14].




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Sébastien Mariéthoz (M’05) received the Ph.D. de-gree in electrical engineering for his work on asym-metrical multilevel converters from EPFL, Lausanne,Switzerland, in 2005.

He was a Research Fellow with the PEMC Group,University of Nottingham, Nottingham, U.K., wherehe focused on the design and control of new matrixconverter topologies. He joined the Automatic Con-trol Laboratory, ETH Zürich, Zurich, Switzerland, in2006, where he is currently a Senior Researcher. Hiscurrent research interests include power converter

topologies, control of power electronic systems with emphasis on modelpredictive control, and sensorless control techniques.

Stefan Almér was born in Stockholm, Sweden. Hereceived the M.Sc. degree in engineering physics andthe Ph.D. degree in optimization and systems theoryfrom the Royal Institute of Technology (KTH),Stockholm, Sweden, in 2003 and 2008, respectively.

He currently holds a Research Position with theAutomatic Control Laboratory, ETH Zürich, Zurich,Switzerland. His research interests include switching

and pulse-modulated systems, model predictive con-trol (MPC), and control of power electronics.




Mihai Bâja was born in Sibiu, Romania. Hereceived the engineering and masters diplomasfrom the “Politehnica” University of Bucharest,Bucharest, Romania, in 2004 and 2005, respectively.He is in the process of finalizing his Ph.D. degreewith SUPELEC, where his work is on the controlof switched systems with application to powerconverters.

Andrea Giovanni Beccuti receivedthe M.Sc.degreein electrical engineering from the Politecnico di Mi-lano, Milano, Italy, in 2001, and the Ph.D. degreefromthe Automatic Control Laboratory,ETH Zürich,Zurich, Switzerland, in 2007.

He was with the Transmission and DistributionGrids Business Unit, CESI. He is currently employedat ABB Corporate Research Switzerland, working inthe field of predictive and optimal control techniquesfor power systems and power electronics.

Diego Patino was born in Manizales, Colombia. Hereceived the Master’s degree from la Universidad deLos Andes, Bogota, Columbia, and the Ph.D. degreein automatic control from Nancy University, Nancy,France.

He is an author of several articles. He is an Elec-tronic Engineer from la Universidad Nacional, Bo-gotá, Colombia. Currently, he works as full-timePro-fessor with Pontificia Universidad Javeriana, Bogotá,Colombia.

Andreas Wernrud received the Ph.D. degree onthe topics optimal control and computation from theDepartment of Automatic Control, Lund Institute of Technology, Lund, Sweden, in 2008.

He is now with the Swedish Defense ResearchAgency, Linköping, Sweden.

Jean Buisson received the Dipl.-Ing. degree fromSUPELEC, Cesson-Sévigné Cedex, France, in 1976.

Since 1993, he has been a Professor with SUP-ELEC. His current research interests include the fieldof hybrid systems: physical switched systems mod-eling and control, predictive control, with applicationin thefield of powersystems control, energymanage-ment, and building temperature control.

Hervé Cormerais received the Dipl.-Ing. degreefrom SUPELEC, Cesson-Sévigné Cedex, France,in 1992, and the Master’s degree in theoreticalphysics and the Ph.D. degree in signal processingand communications from the University of Rennes1, Rennes, France, in 1993 and 1998, respectively.

In 1993, he joined SUPELEC, where is now a Pro-fessor. His current research interests include model-

ling and control of nonlinear and switched systemsand more recently the field of biomedical systems.

Tobias Geyer (M’08) received the Dipl.-Ing. andPh.D. degrees in electrical engineering from ETHZurich, Zurich, Switzerland, in 2000 and 2005,respectively.

From 2006 to 2008, he was with GE’s GlobalResearch Center, Munich, Germany, where he wasa project leader working on control and modula-tion schemes for large medium-voltage electricaldrives. In late 2008, he joined the Power ElectronicsGroup, University of Auckland, New Zealand, as aResearch Fellow. His research interests include the

intersection of modern control theory, optimization, and power electronics,including model predictive control, hybrid systems, electrical drives, and dc-dcconversion.

Dr. Geyer was a recipient of an IAS Best Paper Award.

Hisaya Fujioka (M’95) received the B.E., M.E., andPh.D. degrees all from the Tokyo Institute of Tech-nology, Tokyo, Japan, in 1990, 1992, and 1995, re-spectively.

During 1995 to 1997, he was an Assistant Pro-fessor at Osaka University, Osaka, Japan. In 1998,he joined Kyoto University, Kyoto, Japan, wherehe is currently an Associate Professor. His researchinterests include theory and application of robust

and sampled-data control.Dr. Fujioka is currently an Associate Editor of theIEEE TRANSACTIONS ON AUTOMATIC CONTROL.

Ulf Jönsson was born in Barsebäck, Sweden. Hereceived the Ph.D. degree in automatic control fromLund Institute of Technology, Lund, Sweden, in1996.

He held postdoctoral positions with California In-stitute of Technology and at Massachusetts Instituteof Technology from 1997 to 1999. In 1999, he joinedthe Division of Optimization and Systems Theory,Royal Institute of Technology, Stockholm, Sweden,where he is currently an Associate Professor. Hiscurrent research interests include design and analysis

of nonlinear and uncertain control systems, periodic system theory, control of switching systems, and control of network interconnected systems.

Dr. Jönsson served as an Associate Editor of the IEEE T RANSACTIONS ON

AUTOMATIC CONTROL from 2003 to 2005.

Chung-Yao Kao (M’09) was born in Tainan,Taiwan. He received the Sc.D. degree in mechanicalengineering from Massachusetts Institute of Tech-nology, Cambridge, MA, in 2002.

From 2002 to 2004,he held research positions withthe Department of Automatic Control, Lund Instituteof Technology, Lund, Sweden, the Mittag-Leffler In-stitute, Stockholm, Sweden, and the Division of Op-timization and Systems Theory, the Royal Institute of

Technology, Stockholm, Sweden. From July 2004 toJanuary 2009, he was a Senior Lecturer with the De-




partment of Electrical and ElectronicEngineering, the University of Melbourne,Melbourne, Australia. Since February 2009, he joined the Department of Elec-trical Engineering, National Sun Yat-SenUniversity, Kaohsiung, Taiwan, wherehe is currently an Associate Professor. His research interests include analysisand design of networked and distributed systems, specialized computational al-gorithms for control system analysis and synthesis, and control system applica-tions.

Manfred Morari (F’05) received the diploma fromETH Zurich, Zurich, Switzerland, and the Ph.D.from the University of Minnesota, Minneapolis, bothin chemical engineering.

He was appointed head of the Automatic ControlLaboratory, ETH Zurich, in 1994. Before that hewas the McCollum–Corcoran Professor of ChemicalEngineering and Executive Officer for Control andDynamical Systems, the California Institute of Technology, Pasadena. His interests include hybridsystems and the control of biomedical systems.

In recognition of his research contributions, he received numerous awards,among them the Donald P. Eckman Award and the John R. Ragazzini Awardof the Automatic Control Council, the Allan P. Colburn Award, and the Profes-sional Progress Award of the AIChE, the Curtis W. McGraw Research Award of the ASEE, Doctor Honoris Causa from Babes–Bolyai University, and the IEEEControl Systems Field Award. He is a fellow of IFAC and was elected to the Na-tional Academy of Engineering (U.S.). He has held appointments with Exxonand ICI plc and serves on the technical advisory boards of several major corpo-rations.

Georgios Papafotiou (M’03) received the Diplomaand Ph.D. degrees from the Aristotle University of Thessaloniki, Thessaloniki, Greece, in 1997 and2002, respectively, both in electrical engineering.

In 2006, he joined the ABB Corporate ResearchCenter, Dättwil, Switzerland, where he is currentlyworking on the development of modern controland estimation methods for power electronics

applications. From 2003 to 2006, he was with theAutomatic Control Laboratory, ETH Zurich, Zurich,Switzerland, where he worked on MPC for hybrid

systems, with a special focus on dc-dc converters, and induction motor drives.

Anders Rantzer (F’01) was born in Umeå, Swedenin 1963. He received the Ph.D. degree in optimiza-tion and systems theory from the Royal Institute of Technology (KTH), Stockholm, Sweden.

After postdoctoral positions at KTH and IMA,University of Minnesota, he joined the Departmentof Automatic Control, Lund Univeristy, Lund,Sweden, in 1993, where he was appointed Professor

of Automatic Control in 1999. He was a visitingAssociate Faculty Member with Caltech in 2004 and2005. His research interests include modeling, anal-

ysis, and synthesis of control systems, with particular attention to uncertainty,optimization, and distributed control.

Dr. Rantzer has been serving as an Associate Editor of the IEEETRANSACTIONS ON AUTOMATIC CONTROL and several other journals. Hewas a recipient of the SIAM Student Paper Competition, the IFAC CongressYoung Author Price and the IET Premium Award for the Best Article in IEEProceedings—Control Theory and Applications during 2006. He is a memberof the Royal Swedish Academy of Engineering Sciences.

Pierre Riedinger received the M.Sc. degree inapplied mathematics from the University JosephFourier, Grenoble, France, in 1993 and the Ph.D.degree in automatic control from the Institut Na-tional Polytechnique de Lorraine, Nancy University,Nancy, France, in 1999.

He is now an Associate Professor since 2001with the engineering school ENSEM-INPLand Researcher at the CRAN Laboratory, Van-doeuvre-les-Nancy, France. His current researchinterests include analysis, control (optimal, predic-

tive), and observation of complex systems (switched, hybrid systems).

comparison of hybrid control techniques for buck

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