comparing high-end computer architectures for business applications presentation: 493 track: hp-ux...
TRANSCRIPT
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Comparing High-End Computer Architectures for Business Applications
Presentation: 493
Track: HP-UX
Dr. Frank Baetke
HP
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basicsbasics
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basic components / nomeclature
cpu
memory
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processors: bandwidth & latency
cache
cpu
memory
bus
memory bandwidth~0.6 GB/s to 2.7 GB/s
low high
memory latency:~200ns to ~1000ns
on-chip cache latency ~4ns
off-chip cache latency ~30ns
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processorsprocessors
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2© 2002
next generation processor technologyIn
no
va
tio
n
CISC RISC
OOO SuperScalarH/W detects implicit parallelism
H/W O-O-O scheduling & speculation
H/W renames 8-32 registers to 64+
Explicitly
Parallel
Instruction
Computing
Explicitly
Parallel
Instruction
ComputingMultiple Cores &Integrated InterconnectsMultiple Cores &Integrated Interconnects
New features !New features !
New features ?New features ?
Alpha EV7
Itaniumtm2
IA-32 Processor Family
PA-8800
POWER4
SPARC-III
MIPS 14K
PA-8700
Alpha EV68
Itanium
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PA-8700
3 GFLOP/s RISC processor
Actually a PIM (a processor in memory)
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PA-8800 processor
Dual core technology
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trend 1:
large on-chipcaches
multi-core chips
new architecture Itanium®
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Itanium®architecture
formerly IA-64, IPF
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IA-64 (IPF) Key Features:
• Massive resources: 2* 128 64-bit+ registers.n* Integer Units, m*Floating-Point Units, lots of special registers for branches, predication, loop unrolling etc.
• Speculation: The processor can ‘pre-load’ data into the caches even if the access is potentially illegal - so it speculates that the data are valid. Correctness can later be checked in 1 cycle !
• Explicit Parallelization: The compiler ‘tells’ the processor what can be executed in parallel (and what requires sequential processing)
• Predication: The compiler tells the processor to run (for example) both parts of an ‘IF condition’ in parallel and then discard the ‘wrong part’.
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Itanium: Principal CPU-Design
128128GRsGRs
128128GRsGRs
128128FRsFRs
128128FRsFRs
MMEEMMOORRYY
Massively resourced - large register files Massively resourced - large register files Can use registers for ‘vector-like’ loopsCan use registers for ‘vector-like’ loops
ExecutionUnits
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IA-64 (IPF) Key Features:
• Massive resources: 2* 128 64-bit+ registers.n* Integer Units, m*Floating-Point Units, lots of special registers for branches, predication, loop unrolling etc.
• Speculation: The processor can ‘pre-load’ data into the caches even if the access is potentially illegal - so it speculates that the data are valid. Correctness can later be checked in 1 cycle !
• Explicit Parallelization: The compiler ‘tells’ the processor what can be executed in parallel (and what requires sequential processing)
• Predication: The compiler tells the processor to run (for example) both parts of an ‘IF condition’ in parallel and then discard the ‘wrong part’.
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Speculation: preloading data into caches reduces (hides) latency
Memory Latency:~200ns to ~1000ns
On-Chip Cache Latency ~4ns
Off-Chip Cache Latency ~30ns
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IA-64 (IPF) Key Features:
• Massive resources: 2* 128 64-bit+ registers.n* Integer Units, m*Floating-Point Units, lots of special registers for branches, predication, loop unrolling etc.
• Speculation: The processor can ‘pre-load’ data into the caches even if the access is potentially illegal - so it speculates that the data are valid. Correctness can later be checked in 1 cycle !
• Explicit Parallelization: The compiler ‘tells’ the processor what can be executed in parallel (and what requires sequential processing)
• Predication: The compiler tells the processor to run (for example) both parts of an ‘IF condition’ in parallel and then discard the ‘wrong part’.
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RISC vs. EPIC instruction formatRISC vs. EPIC instruction format
Instruction 2Instruction 2 Instruction 1Instruction 1 Instruction 0Instruction 0 TemplateTemplate
128-bit bundle128-bit bundle
00127127
The new instruction format enables scalability w/ compatibilityThe new instruction format enables scalability w/ compatibility
Instruction 0Instruction 0 Instruction 0Instruction 0 Instruction 0Instruction 0 Instruction 0Instruction 0
32-bit parcel32-bit parcel
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Itanium: explicit parallelismItanium: explicit parallelism
Instruction 1Instruction 1 Instruction 2Instruction 2 Instruction3Instruction3 TemplateTemplate
00127127
6 instructions/cycle on Itanium or McKinley6 instructions/cycle on Itanium or McKinley
TemplateTemplateInstruction6Instruction6Instruction 5Instruction 5Instruction 4Instruction 4
128-bit bundle128-bit bundle
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Itanium: explicit parallelism 2Itanium: explicit parallelism 2
Load InstructionLoad Instruction Load InstructionLoad Instruction Instruction3Instruction3 TemplateTemplate
00127127
Itanium2 (ex McKinley) and future processors will allow 4 loads/cycle
Itanium2 (ex McKinley) and future processors will allow 4 loads/cycle
Load InstructionLoad Instruction Load InstructionLoad Instruction Instruction 6Instruction 6 TemplateTemplate
Instruction 7Instruction 7 Instruction 8Instruction 8 Instruction 1Instruction 1 TemplateTemplate
128-bit bundle128-bit bundle
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IA-64 (IPF) Key Features:
• Massive resources: 2* 128 64-bit+ registers.n* Integer Units, m*Floating-Point Units, lots of special registers for branches, predication, loop unrolling etc.
• Speculation: The processor can ‘pre-load’ data into the caches even if the access is potentially illegal - so it speculates that the data are valid. Correctness can later be checked in 1 cycle !
• Explicit Parallelization: The compiler ‘tells’ the processor what can be executed in parallel (and what requires sequential processing)
• Predication: The compiler tells the processor to run (for example) both parts of an ‘IF condition’ in parallel and then discard the ‘wrong part’.
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IA-64: PredicationIA-64: PredicationRun the Run the THENTHEN and and ELSEELSE part in parallel ! part in parallel !
Instruction 2Instruction 2 Instruction 1Instruction 1 Instruction 0Instruction 0 TemplateTemplate
00127127
Predication allows to eliminate branchesPredication allows to eliminate branches
Instruction 2Instruction 2 Instruction 1Instruction 1 Instruction 0Instruction 0 TemplateTemplate
Instruction 2Instruction 2 Instruction 1Instruction 1 Instruction 0Instruction 0 TemplateTemplate
Instruction 2Instruction 2 Instruction 1Instruction 1 Instruction 0Instruction 0 TemplateTemplate
TemplateTemplateInstruction 0Instruction 0Instruction 1Instruction 1Instruction 2Instruction 2
128-bit bundle128-bit bundle
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PA-RISCis the only
RISC architecture
compatible to IA-64
The IA-64 instructions set has been designed with pa-risc instructions in mind
IA-64 processors can:
run pa-risc native code (under HP-UX 11)
run IA-64 native code (hp-ux, linux, …)
run IA-32 native code (Win64)
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running PA-RISC code on Itanium
CPU
Memory
PA-RISC CPU
HP-UX 11
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CPU
Memory
IPF CPU runningHP-UX 11
PA-RISC Code
DyncodeTranslator
running PA-RISC code on IPF
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basics
trend 2:
very few instruction set architectures will survive
(no applications on ‘exotic’architectures !)
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basicsservers
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A small server with 2 CPUsone address space – one copy of HP-UX 11.x (J-Class)
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SMP advantage: big & small jobs, butthe bus may become a bottleneck ….
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rp7400 - a hybrid design (still SMP)
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Half Dome / Super Dome
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SuperDome
•Scalable Architecture –to 64–to .5 TB Physical Memory–to 192 PCI Busses
•HP-UX 11i–resource partitioning –near fault-tolerant capabilities–on-line add/replace for CPUs,
memory and I/O components
•Processor support –PA8600 introduction–PA-RISC & IA64 roadmap
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Cell - A Modular Building Block
Up to 4 processors Up to 16/32 GB memory
(4 carriers x 8 GB ea) IO channel supports 16 PCI
busses, 16 slots Cell crossbar provides
8 GB/s Cell I/O bandwidth is
1.8 GB/s
Cro
ssb
ar
8 G
B/s
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SuperDome Cell Board
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SuperDome / rp8400 (16 CPUs)
Crossbar 32 GB/s
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server rp8400
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SuperDome (32 CPUs)Latencies: 208, 301 and 357 ns
Crossbar 32 GB/s
Crossbar 32 GB/s
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SuperDome (64 CPUs)Latencies: 208, 301 and 357 ns
Crossbar 32 GB/s
Crossbar 32 GB/s
Crossbar 32 GB/s
Crossbar 32 GB/s
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basics
trend 3:
SMPs with crossbars
cells & ccNUMA
inherent upgradability
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basicspartitions
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4 nPartitions (1 x 32, 1 x 16, 2 x 8 CPUs)
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SuperDome (32 CPUs) & virtual partitions3 nPartitions (16, 8, 8 CPUs), 6 Copies of HP-UX
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SuperDome (32 CPUs) & virtual partitions3 nPartitions (16, 8, 8 CPUs), 6 Copies of HP-UX
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rp7400 – with virtual partitions (2 x HP-UX)
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basics
trend 4:
partitioning
- GRIDS- clusters- hard partitions- virtual partitions- schedulers
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basics
Example:SUN’S UE10000
(not a cell-based architecutre)
:
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UE10000: A Special SMP: 560 ns latency
Crossbar 12.6 GB/s
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All traffic goes through one crossbar !!!560 ns latency (SuperDome has 200 – 350ns)
Crossbar 12.6 GB/s
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Loading multiple domains - one left
Crossbar 12.6 GB/s
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basics
Example:
SUN’sMidFrames
(cell-based architectures)
:
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Sun Fire 3800 Server – Basic Design
9.6 GB/s data bandwidth9.6 GB/s data bandwidthI/O 1
I/O 2
4.8
GB
/s
2.4 GB/s
4.8
GB
/s
2.4 GB/s
2.4 GB/s
2.4 GB/s
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Sun Fire 3800 Server – Basic Design
Now with Address Routers included ... Still 9.6 GB/S
9.6 GB/s data bandwidth9.6 GB/s data bandwidthI/O 1
I/O 2
4.8
GB
/s
2.4 GB/s
4.8
GB
/s
2.4 GB/s
2.4 GB/s
2.4 GB/s
Address RouterAddress Router
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Sun Fire 4800 Server – Basic Design
I/O 1
I/O 2
4.8
GB
/s
2.4 GB/s
4.8
GB
/s2.4 GB/s
2.4 GB/s
2.4 GB/s
9.6 GB/s data bandwidth9.6 GB/s data bandwidth
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Sun Fire 6800 Server – Basic Design
I/O 1
I/O 24
.8 G
B/s
2.4 GB/s4
.8 G
B/s
2.4 GB/s
2.4 GB/s
2.4 GB/s4
.8 G
B/s
4.8
GB
/s9.6 GB/s data bandwidth9.6 GB/s data bandwidth
I/O 3
I/O 4
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System BW Scalability (random access)
0
10
20
30
40
50
60
70
0 8 16 24 32 40 48 56 64
cpus
GB
/sec
Sun MidframeN4000Superdome
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basics
trend 5:
multi-OS environments
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basicsExample:
SuperDomeafter an upgrade to Itanium
:
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Cell2 - Dramatic Improvements
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Windows200x
SuperDome-IPF (64 CPUs)4 nPartitions (1 x 32, 1 x 16, 2 x 8 CPUs), 1 and 3 vPars for HP-UX
Linux-64 Win-64HP-UX 11i V2
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OS/ABI flexibility on HP IPF-SystemsWindows64 (native boot)
MS Win64 Applications compiled for IPF (64bit)
Linux64 (native boot)
MS W2Kapps for IA32
HP-UX 11i (native boot)
HP-UX ABILinux ABI
Linux 64 Applications compiled for IPF (64bit)
Linux 64 Applications compiled for IPF (64bit)
HP-UX Applications compiled for IPF
PA-Apps
ARIES
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Windows200x
SuperDome 64 (IPF) CPUs4 nPartitions (1 x 32, 1 x 16, 2 x 8 CPUs)
Windows200xHP-UX 11i V2 HP-UX 11i V2
... all LINUX64 binaries can be
executed here
HP-UX 11i V2HP-UX 11i V2
... all LINUX64 binaries can be
executed here
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Thank You