COE 1502Memory Model

Introduction

Our current processor uses a memory interface with the assumptions:

– Interface signals MemRead, MemWrite, MemoryAddress, MemoryDataOut MemWait, MemoryDataIn

– Byte-addressed– Handshaking bus protocol (for reads):

Introduction

However, the SRAM memory on the Wild-One board:– Word addressed– Different set of interface signals– Different bus protocol

It uses a bus arbitration protocol

The goal of this unit is to reconcile these differences and use this memory for our processor

– For simulation, we have provided a VHDL model for the memory– When we load our processors onto the FPGAs, we’ll remove the

model and use the real memory

Introduction

Wild-One card has two FPGAs that may desire to use the memory (32K x 32 SRAM)

Memory bus consists of an address bus (24-bit) and two data buses (32-bit)

Control signals are used by the FPGAs to gain access to the bus (become bus master)

FPGA 0

FPGA 1

Memory

Arbiter

Shared bus Local control

Simulator memory model from COELib

Parts you will design:

BUS CONTOLLER LOGIC DATA ALIGNMENT UNIT

Your current CPU Design

Interfacing your CPU to Memory on the Wildfire Board

Bus Arbitration

In order to use the memory on the Wild-One card, we use centralized bus arbitration

– Control signals MemBusReq_n, MemStrobe_n,

MemWriteSel_n MemBusGrant_n

– Data signals MemAddr_OutReg,

MemData_OutReg MemData_InReg

A bus controller will reconcile the differences between the existing handshaking protocol and this protocol

– Uses the MemWait signal to stall the processor while arbitration is being performed on behalf of the processor

Memory Read

Memory Write

Bus Arbitration

We use a bus for the processor to access the memory

– A bus is a shared communication link– How is the bus reserved by a device that wishes it to

communicate? Single Master

– CPU is master, memory/(all others) is slave (we assumed this before)

Arbitration schemes– Multiple bus master system– Arbiter decides who is the bus master– Arbiter may employ priority

Bus Arbitration

Bus arbitration schemes (control signals shown)

• Daisy chain

Request

Release

Grant GrantGrant

Arbiter

Device 1 Device 2 Device 3

Request Reques

t Request

Grant GrantGrantArbiter

Device 1 Device 2 Device 3

• Centralized, parallel

Request

Device 1 Device 2 Device 3

• Distributed by self-selection

Request

Device 1 Device 2 Device 3

• Distributed by collision detection

Word Alignment

The next problem we must solve– MemAddr_OutReg is word aligned

Address bits 1 and 0 are not used Must do something about LH and LB which do not address the

low-order portion of the word

– Solution: use little-endian addressing

Byte offset within word

10 00

Byte offset within word

11 10 01 00

Half words within word Bytes within word

Because the processor sign/zero-extends the low-order portion of the word on a LH, LHU, LB, LBU, we just need to right-shift the contents depending on the offset!

Note: this has implications for stores!

Alignment Unit

32-bitWordfrom memory

32-bitWordTo CPU

LSB

MSB

Three modes for the alignment unit Word mode – pass all data, unshifted Halfword mode – shift top two byte lanes to low two byte lane (if

offset = 10) Byte mode – shift high byte lanes to low order (dep. on offset)

Address(0) Address(1)

CPU will Sign extend if necessary

Note! YOU MUST DO THIS FOR MEMORY CODE TO WORK

Must make sure you set…