coa 2nd m-first class
TRANSCRIPT
8/8/2019 Coa 2nd M-first Class
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Todays topics
Single BUS organization of processor
Instruction execution –General idea…
Register transfer…
AL operations…
Fetching a word from memory (to processor)
Storing a word in memory (from processor)
1/16/11 11BINOSHI SAMUVEL. lect.
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A
INSTRUCTION 1
INSTRUCTION 2
A
A+4
MAR MDR
PC
IRREG ALU
CONTRO
L UNITREADWRITE
Memory unit
processor 1/16/11 22BINOSHI SAMUVEL. lect.
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CONTAINS MEM0RY
ADDRESS OF THE NEXT INSTUCTION TO BE
EXECUTED
CONTAINS ADDRESSOF THE LOCATION TO
BE ACCESSED
CONTAINS DATA TO BEWRITTEN INTO OR
READ OUT OF THEMEMORY LOCATION
ARE general purposereg.
Programmer canconsider..
Transperent to the programmer..
Use to hold valuewhile doing some
process
Has 2 pins ..select 4and select
1/16/11 33BINOSHI SAMUVEL. lect.
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A
INSTR 2
A
A+4
MAR MDR
PC
IRREG ALU
CONTRO
L UNITREADWRITE
A
A
INSTR 1
INSTR 1
1/16/11 44BINOSHI SAMUVEL. lect.
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A
INSTR 2
A
A+4
MAR MDR
PC
IRREG ALU
CONTRO
L UNITREADWRITE
A
A
INSTR 1
INSTR 1
1/16/11 55BINOSHI SAMUVEL. lect.
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A
INSTR 2
A
A+4
MAR MDR
PC
IRREG ALU
CONTRO
L UNITREADWRITE
A
INSTR 1
INSTR 1
A+4
result
1/16/11 66BINOSHI SAMUVEL. lect.
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AINSTR 2
A
A+4
MAR MDR
PC
IRREG ALU
CONTRO
L UNITREADWRITE
A
INSTR 1
INSTR 1
A+4
result
1/16/11 77BINOSHI SAMUVEL. lect.
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REGISTER TRANSFERS
two control signals are used to place thecontents of that register on the bus or to loadthe data on the bus into the register.
Ri and Ro
All operations and data transfers within theprocessor take place within time periods
defined by the processor clock.
1/16/11 99BINOSHI SAMUVEL. lect.
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65
0
o
o
0
Reg.1
Reg.2
R1 out
R2 in
R2 out
R1 in
Move reg1,reg2
1/16/11 1010BINOSHI SAMUVEL. lect.
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0
1
o
1
Reg.1
Reg.2
R1 out
R2 in
R2 out
R1 in
R 1 out , R2 in
65
1/16/11 1111BINOSHI SAMUVEL. lect.
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1
0
1
0
Reg.1
Reg.2
R1 out
R2 in
R2 out
R1 in
65
1/16/11 1212BINOSHI SAMUVEL. lect.
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Instruction executioncycles..REGISTER TRANSFER ----------- DONE
Perform an arithmetic or a logic operation and
store the result in a processor register
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PERFORMING ANARITHMETIC OR LOGICOPERATIONControl signals for adding 2 numbers..
Aim add [R1]+[R2]----->R3
Step1…. R1 out , Yin
Step2… R2 out ,select Y ,Add ,Zin
Step3… Z out ,R3 in
1/16/11 1414BINOSHI SAMUVEL. lect.
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8
0
0
Reg.1
R1 out
R2 in
R2 out
R1 in
Reg.2
20
0
0O
0Reg.3
R3 in
R3 out
0
00
Y
MUX
Z
Zout
Z in
Y in
1/16/11 1515BINOSHI SAMUVEL. lect.
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8
0
1
Reg.1
R1 out
R2 in
R2 out
R1 in
Reg.2
20
0
0O
0Reg.3
R3 in
R3 out
1
00
Y
MUX
Z
Zout
Z in
Y in
R1 out , Yin
1/16/11 1616BINOSHI SAMUVEL. lect.
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0
1
Reg.1
R1 out
R2 in
R2 out
R1 in
Reg.2
20
0
0O
0Reg.3
R3 in
R3 out
1
00
Y
MUX
Z
Zout
Z in
Y in
8
1/16/11 1717BINOSHI SAMUVEL. lect.
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next
Step1…. R1 out , Yin
Step2… R2 out ,select Y,Add ,Zin
Step3… Z out ,R3 in
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0
0
Reg.1
R1 out
R2 in
R2 out
R1 in
Reg.21
0
0O
0Reg.3
R3 in
R3 out
0
0
MUX
Z
Zout
Z in
Y in
R2 out ,select Y,Add ,Zin
2
8
1/16/11 1919BINOSHI SAMUVEL. lect.
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0
0
Reg.1
R1 out
R2 in
R2 out
R1 in
Reg.2
0
0
0O
0Reg.3
R3 in
R3 out
0
01
MUX
Z
Zout
Z in
Y in
0
1
R2 out ,select Y,Add ,Zin
1/16/11 2020BINOSHI SAMUVEL. lect.
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next
Step1…. R1 out , Yin
Step2… R2 out ,select Y ,Add ,Zin
Step3…Z out ,R3 in
1/16/11 2121BINOSHI SAMUVEL. lect.
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Instruction execution
cycles..REGISTER TRANSFER ----------- DONE
AL OPERATION__________DONE
Fetching a word from memory
1/16/11 2323BINOSHI SAMUVEL. lect.
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FETCHING A WORD FROMMEMORY
As an exa of a read operation, consider …Move (RI ),R2
The actions needed to execute this instruction are:
1. MAR [RI]2. Start a Read operation on the memory bus
3. Wait for the MFC response from the memory
4. Load MDR from the memory bus
5. R2 [MDR]
1/16/11 2424BINOSHI SAMUVEL. lect.
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MDR
0
0
0
0
MDR OUT E
MDR in E
MDR OUT
MDR in
External busInternal
01 REG.
R1 inR1ou
R1 out, MAR in , Read
11 MAR.
1/16/11 2525BINOSHI SAMUVEL. lect.
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MDR
0
0
0
0
MDR OUT E
MDR in E
MDR OUT
MDR in
External busInternal
01
R1 inR1ou
R1 out, MAR in , Read
11 MAR.
READ
AA
1/16/11 2626BINOSHI SAMUVEL. lect.
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MDR
0
1
0
0
MDR OUT E
MDR in E
MDR OUT
MDR in
External busInternal
0o A
R1 inR1ou
MDRin E, WMFC
o1 A.
READ
WMFC
content
1/16/11 2727BINOSHI SAMUVEL. lect.
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MDR
1
0
0
0
MDR OUT E
MDR in E
MDR OUT
MDR in
External busInternal
0o A
R1 inR1ou
MDR out, R2 in
o1 A.
Reg 2
1content
Pr0cesscompleted
1/16/11 2828BINOSHI SAMUVEL. lect.
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Ti i di
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Timing diagram
1/16/11 2929BINOSHI SAMUVEL. lect.
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Instruction execution
cycles..REGISTER TRANSFER ----------- DONE
AL OPERATION__________DONE
Fetching a word from memory----done
Storing a word in memory
1/16/11 3030BINOSHI SAMUVEL. lect.
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Storing a word inmemoryMove R2,(R1)
C signals…….
1..R1 out, MAR in
2..R2 out, MDR in, WRITE
3…MDR out E, WMFC
1/16/11 3131BINOSHI SAMUVEL. lect.
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MDR
0
0
0
0
MDR OUT E
MDR in E
MDR OUT
MDR in
External busInternal
01
R1 inR1ou
R1 out, MAR in
11 MAR.
READ
AB
5
0
1/16/11 3232BINOSHI SAMUVEL. lect.
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MDR
0
0
0
1
MDR OUT E
MDR in E
MDR OUT
MDR in
External busInternal
0o B
R1 inR1ou
R2 out, MDR in, WRITE
o1 MAR
1
5
write
5
1/16/11 3333BINOSHI SAMUVEL. lect.
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