cms emu trigger electronics

CMS EMU TRIGGER ELECTRONICS

B. Paul Padley

Rice UniversityFebruary 1999

Trigger Layout and Responsibilities

Basic

Requirements

Latency: < 3.2 usFully pipelined

synchronous architecture, dead time =0

Maximum output rate: <15 kHz

Output to the Global Trigger: up to 4 highest Pt muons in each event

Initial Design

Put all front end, LCT generation and processing electronics on chambers

Issues: Poor accessability Power dissipation Radiation hardness

New Design (Summer ‘98 UCLA)

Simple front end boards on chambers

All digital LCT generation and processing logic into 9U crates on periphery

MUON TRIGGER SYSTEM MODULE COUNT (UCLA,

OSU, RICE, UF)

Anode LCT Module - 504Cathode LCT Module - 504Trigger Motherboard - 264DAQ Motherboard - 264Port Card - 60Clock and Control Board - 126Sector Receiver - 24Sector Processor - 24Sorter - 1

Total - 1771

EMU Trigger Motherboard

One board for two chambersReceives up to two anode

and two cathode LCT’sMatches them in timePasses them on to Port Card9U VME board with interface

We have proposal to allow the use of RPC information to resolve ghosts if needed

MB Schematic (and changes)

From port card

VME Interface (New)

TRIGGER MOTHERBOARD

INTERFACE ADDRESS24

CLCT2

LB2

CLCT1

CLOCK40DES1, BX0, START COUNT

LUT RAM

RECEIVER

CLCT2

J1

PREPROCESSING

CLCT1

RPC

ALCT2

ALCT1

LB2 PREPROCESSINGCONTROL

BACKPLANECUSTOM

AND

LUT RAM

RECEIVER

ANODE

RECEIVER

RECEIVER

RPC2 LOGIC

RECEIVER

RECEIVER

RECEIVER

ALCT2

RECEIVER

RECEIVER

LB1

MPC

LOGIC

LOGIC

MUON TRIGGER MOTHERBOARD BLOCK DIAGRAM

CSC2

CSC1

RPC

PREPROCESSING

RECEIVER

LOGICPREPROCESSING

PREPROCESSING

PREPROCESSING

ALCT1

FROM

FROM

CATHODE

RECEIVER

LB1

AND

RECEIVER

DATA16

MPC

LOGIC

FROM

VME

LOGIC

ANODE

FROM

RPC1

RECEIVER

CATHODE

LB3

LB3

RECEIVER

CHANNEL

CHANNEL

LINK

LINK

TRANSMITTERS

TRANSMITTERS

TWO MUONS

TWO MUONS

Summer 98Test Beam Prototypes

Engineering "proofs-of-principle"

Custom analog ASICs (preamps, disc's, comparators)

Wide use of FPGAs at 40 MHz

High-speed LVDS channel links

Clock distribution from motherboard

Trigger drives DAQ system readout

Motherboard Prototype

CAMAC board Communicate with FE via

LVDSSend Clock to FE from

quartz or external generator

Selected LCT’s stored in FIFO for reading by CAMAC

Board is tested and working at 40 MHz.

It was built, and worked!

By that I mean

Communicated with LCT card via National channel link LVDS

Distributed clockCorrectly selected “best”

LCT’sWe could study BXN

matching but we could not test the BXN

PLD code • Its tough testing this in an

asynchronous beam.

BXN Matching Study

Excess

GIF

Turned

OFF

|BXN mismatch| > 1

2% of the time

BXN Matching Study

In this case 3.2% excess

GIF TurnedOn

Caveat Emptor

It must be noted that those BXN matching results are using the worst possible timing you could get from the Anodes

There is no way in this test data to correct the BXN from the anode as will be done in reality.

Thus the results represent upper limits.

Trigger Motherboard New Prototype Design Status

Inputs from LCT modules and outputs to Port Card are specified

PLD design 60% completed

Schematic design in progress

The Port Card

The Port Card

Serves one sector of 8 or 9 chambers

Receives up to 18 LCT’s from motherboards

Selects the best 3 and sends to sector receivers on optical cable

VME 9U board

Port Card

MUON PORT CARD

DATA16

ADDRESS24

CONTROL

J1

VME

INTERFACE

MUON PORT CARD BLOCK DIAGRAM

CUSTOMBACKPLANE


OPTICAL MODULE

OPTICAL MODULE

OPTICAL MODULE

OPTICAL MODULE

OPTICAL MODULE

OPTICAL MODULE

G-LINK

G-LINK

G-LINK

G-LINK

G-LINK

G-LINK

CONNECTOR

THREE MUONS TO

SECTOR RECEIVER

MEZZANINE BOARD

RECEIVERAND

PIPELINE

PIPELINE

RECEIVERAND

RECEIVERAND

PIPELINE

PIPELINE

RECEIVERAND

RECEIVERAND

PIPELINE

PIPELINEAND

RECEIVER

PIPELINE

RECEIVERAND

RECEIVERAND

PIPELINE

PIPELINEAND

RECEIVER

SORTING LOGIC

2 MUONS TMB1

2 MUONS TMB2

2 MUONS TMB3

2 MUONS TMB4

2 MUONS TMB5

2 MUONS TMB6

2 MUONS TMB7

2 MUONS TMB8

2 MUONS TMB9

PORT CARD DESIGN STATUS

Inputs from Trigger Motherboard and outputs to Sector Receiver are specified

Chipset and Optical Modules for communication with Sector Receiver are defined

Sorting Logic designed and under optimization now

Schematic design will start soon

Hardwired Limitations

Note restrictions of the scheme

1 stub per FE card2 stubs per chamber3 stubs per 20 or

degree sector

Consequence of descope, must use 60 degree sectors in stations>1

In station 1 use 20 degree sectors to limit number of Mboards to 9

This used to be 30 degrees

CLOCK AND CONTROL BOARD

DISTRIBUTES TTC SIGNALS TO ALL TRIGGER 9U VME MODULES

UNIFIED DESIGN FOR TRIGGER AND SECTOR PROCESSOR CRATES

ABLE TO GENERATE TTC SIGNALS FROM BUILD-IN SIMULATOR

VME 9U MODULE

ADDRESS

DATA

CONTROL

VMEINTERFACE

BACKPLANE

DIFFERENTIAL

DRIVERS

MUX

MUX

TTCrxBOARDOPTICAL

CABLEFROM TTC

CLOCK

CONTROL

VME 9UMODULE

TTCrxSIMULATOR

MUON CLOCK AND CONTROL BOARD

J1

CUSTOMBACKPLANE

CLOCK40DES1BX ZEROBCR, ECRL1ACC

Clock and Control Board Design Status

Number and list of signals which should be distributed from TTC to trigger modules will be finalized soon

Initial proposal on custom backplane is ready

Schematic design will start soon

MUON SORTER

RECEIVES 72 MUONS FROM 24 SECTOR PROCESSORS (3 MUONS PER SECTOR PROCESSOR)

SELECTS FOUR BEST MUONS AND SENDS THEM TO GLOBAL MUON TRIGGER

VME 9U MODULE

CUSTOM

INTERFACE

J1

ADDRESS24

MUON SORTER BLOCK DIAGRAM

VME

CONTROL

DATA16


RECEIVER_1

RECEIVER_2

RECEIVER_3

RECEIVER_24

RECEIVER_23

72 MUONSFROM

24 SECTORPROCESSORS

TRANSMITTER

TRANSMITTER

TRANSMITTER

TRANSMITTER

MUON_1

MUON_2

MUON_3

MUON_4

TO GLOBAL MUON TRIGGER

SORTING LOGIC

4 OUT OF 72

MUON SORTER DESIGN STATUS

General requirements (inputs from Sector Processors and outputs to Global Trigger) are specified

Basic sorting unit (4 best patterns out of 8) initial design is completed

Optimization and timing analysis in progress

Initial specification will be prepared this year

EMU TRIGGER BITS REDUCTION FACTOR vs TRIGGER LATENCY

10

100

1000

10000

100000

1000000

17 BX 27 BX 33 BX 39 BX 80 BX 92 BX

FEB

LCT TMB

MPC

SP

MS

1 BX = 25 ns

cms emu trigger electronics

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