cmos manufacturing process - giuseppe iannaccone€¦ · cmos manufacturing process circuit design...
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CMOSManufacturingprocess
Circuitdesign Setofopticalmasks
Fabricationprocess
Circuitdesigner
Designruleset
Processengineer
All material: Chapter 2 of J. Rabaey, A. Chandrakasan, B. Nikolic, Digital Integrated Circuits, second edition, Prentice Halls, 2002
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SimplifiedverybasicCMOSProcessCMOS inverter – n-well process
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AModernCMOSProcess
p-well n-well
p+
p-epi
SiO2
AlCu
poly
n+
SiO2
p+
gate-oxide
Tungsten
TiSi2
CMOS inverter – dual-well trench-isolated process
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TwocascadedinvertersVDD VDD
Vin Vout
M1
M2
M3
M4
Vout2
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Twocascadedinverters- LayoutView
Siliconingot
Diameter12 inches(300 mm)
Weight100 Kg
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Oxidation 1000 C
opticalmask
processstep
photoresist coating (1um)photoresistremoval (ashing)
spin, rinse, dryacid etch
photoresist
stepper exposure
development
Typical operations in a single photolithographic cycle (from [Fullman]).
Photo-LithographicProcess
In each processing step, an area of the chip is masked out using optical masks, so that the process step is selectively applied to the other regions
Clean room(class 1-10)
Def:Class 1: <1 dust particle per cubic foot
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Exampleofprocessstep:PatterningofSiO2
Si-substrate
Si-substrate Si-substrate
(a) Silicon base material
(b) After oxidation and depositionof negative photoresist
(c) Stepper exposure
PhotoresistSiO2
UV-lightPatternedoptical mask
Exposed resist
SiO2
Si-substrate
Si-substrate
Si-substrate
SiO2
SiO2
(d) After development and etching of resist,chemical or plasma etch of SiO2
(e) After etching
(f) Final result after removal of resist
Hardened resist
Hardened resist
Chemical or plasmaetch
Recurringprocesssteps(1/2)• Doping
– Diffusion (gaswithdopant,900-1100oC)– Ionimplantation
• Latticedamage(displacementofatoms)àAnnealing step(1000oC for15-30’+slowcooling)
• Deposition (oflayersoverthecompletewafer)– Oxidation [siliconoxide]– ChemicalVaporDeposition:gasphase+heat(850oC)[siliconnitride]
– Chemicaldeposition(polysilicon:silane (SiH4)gasoverheatedwafer(600oC)à reactionanpolysiliconformation
– Sputtering (foraluminum):evaporationinvacuumchamber
Recurringprocesssteps(2/2)
• Etching(defines3Dpatternsonthesurface)– Wetetching(withacidorbasicsolutions)
• e.g.Hydrofluoricacidforsiliconoxide• Almostisotropic
– Dryorplasmaetching• Plasma:mixofnitrogen,chlorine,borontrichloride• Stronglyanisotropic(steepverticaledges)
• Planarization(flattenthesurfacetoallowlayerdeposition)– ChemicalMechanicalPolishing(CMP)
• Liquidcarrierwithasuspendedabrasivecomponent
SimplifiedCMOSProcessflow• Activeareas:wheretransistorsare• Fieldoxide:insulatorbetween
neighboringdevices• Wellsintheactiveareas
• Gatestack
• Contactdoping
• MetalInterconnects
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Define active areasEtch and fill trenches
Implant well regions
Deposit and patternpolysilicon layer
Implant source and drainregions and substrate contacts
Create contact and via windowsDeposit and pattern metal layers
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CMOSProcessWalk-Through
p+
p-epi (a) Base material: p+ substrate with p-epi layer
p+
(c) After plasma etch of insulatingtrenches using the inverse of the active area mask
p+
p-epi SiO2
3SiN
4(b) After deposition of gate-oxide andsacrificial nitride (acts as abuffer layer)
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CMOSProcessWalk-ThroughSiO2
(d) After trench filling, CMPplanarization, and removal of sacrificial nitride
(e) After n-well and VTp adjust implants
n
(f) After p-well andVTn adjust implants
p
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CMOSProcessWalk-Through
(g) After polysilicon depositionand etch
poly(silicon)
(h) After n+ source/drain andp+source/drain implants. These
p+n+
steps also dope the polysilicon.
(i) After deposition of SiO2insulator and contact hole etch.
SiO2
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CMOSProcessWalk-Through
(j) After deposition and patterning of first Al layer.
Al
(k) After deposition of SiO 2insulator, etching of via’s,deposition and patterning ofsecond layer of Al.
AlSiO2
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AdvancedMetallization
CMOSManufacturingprocess
Circuitdesign Setofopticalmasks
Fabricationprocess
Circuitdesigner
Designruleset
Processengineer
All material: Chap. 2 of J. Rabaey, A. Chandrakasan, B. Nikolic, Digital Integrated Circuits, second edition, Prentice Halls, 2002
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DesignRules
• Minimumlinewidthdependsonlithography andprocess
• Micronrules:absolutedimensionsforintra-layerandinter-layerlayouts
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Example:Layersin0.25µmCMOSprocess
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Intra-LayerDesignRules
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Inter-layerrules:TransistorLayout
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Inter-layerrules:Vias andContacts
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Inter-layerrules:SelectLayer
CMOSInverterLayout
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LayoutEditor&DesignRuleChecker
poly_not_fet to all_diff minimum spacing = 0.14 um.
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StickDiagram
1
3
In Out
VDD
GND
Stickdiagramofinverter
Dimensionlesslayoutentities
Onlytopologyisimportant
Finallayoutgeneratedby“compaction”program
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PackagingRequirements
Packagesmustsatisfydifferenttypesofrequirements• Electrical:Low parasitics• Mechanical:Reliableandrobust• Thermal:Efficientheatremoval• Economical:Cheap
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BondingTechniques
Lead Frame
Substrate
Die
Pad
Wire Bonding
Gold wires, large inductance
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Tape-AutomatedBonding(TAB)
(a) Polymer Tape with imprinted
(b) Die attachment using solder bumps.
wiring pattern.
Substrate
Die
Solder BumpFilm + Pattern
Sprockethole
Polymer film
Leadframe
Testpads
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Flip-ChipBonding
Solder bumps
Substrate
Die
Interconnect
layers
Top (where circuit is)
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Package-to-BoardInterconnect
(a) Through-Hole Mounting (b) Surface Mount
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PackageTypes
PGA
DIP
PLCC
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PackageParameters
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Multi-ChipModules