cmos logic and current-mode logic

C H A P T E R 5

CMOS Logic and Current Mode Logic

5.1 Introduction

This chapter describes basic logic circuits. This can be seen as largely backgroundmaterial for applications in later chapters in the design of dividers and phasedetectors in frequency synthesizers. The types of logic discussed will be CMOSrail-to-rail logic, CMOS current mode logic (CML), bipolar CML, and bipolaremitter coupled logic (ECL). Note that CML is a general term and applies to bothbipolar and CMOS; however, with metal oxide semiconductor (MOS) transistors,it is often called MOS current mode logic (MCML). ECL is the name often givento bipolar CML that has emitter followers as the output stage transistors. At lowfrequencies, CMOS rail-to-rail is preferred for its simplicity and low static powerdissipation, while, at higher frequencies, CML or ECL is used, as they can operatefaster with lower power because of the reduced output swing. As shown in Figure5.1, when it is not switching, CMOS rail-to-rail logic does not consume any current,while CML does. CMOS rail-to-rail logic consumes current only during transitions,and its power consumption is proportional to the operation frequency. CML biascurrent must rise as the speed of switching increases, just as CMOS rail-to-raillogic does, but it does so at a slower rate. Thus, above some frequency, CMLbecomes a lower-power solution. CMOS rail-to-rail logic is differential and, there-fore, has good power-supply rejection, which is preferred in many synthesizerapplications. Various types of logic and some important design trade-offs aresummarized in Table 5.1.

Figure 5.1 Comparison of current for CMOS rail-to-rail and CML logic versus frequency.

119

120 CMOS Logic and Current Mode Logic

Table 5.1 Comparison of Different Logic Styles

Noise Power-Supply Maximum Power DissipationLogic Type Performance Rejection Speed

CMOS Bad Bad Moderate Low at low frequency,rail-to-rail high at high frequencyCMOS CML Good Good High High at low frequency,

low at high frequencyBipolar Excellent Good Very High High at low frequency,CML, ECL low at high frequency

5.2 CMOS Logic Circuits

CMOS rail-to-rail logic is by far the most commonly used type of logic circuit;however, in synthesizer design, often CML is preferred. The bulk of this chapterwill focus on CML; however, for lower-speed applications, CMOS rail-to-rail logicis often used. CMOS rail-to-rail logic has outputs that are either at or very closeto one of the power supplies. Since the voltage in this case must change by a largeamount and, hence, requires larger charge and discharge time, rail-to-rail logic isoften slower than the other types of logic we will use. Also, even though the dcpower consumption of CMOS rail-to-rail logic is zero, when such circuits areswitched at high speed, they can consume a lot of power (just check the heat sinkon your Pentium!).

Basic CMOS rail-to-rail logic functions are shown in Figure 5.2 [1, 2]. Theyare always made from a pull-up and pull-down network to pull the output to onerail or the other, depending on the inputs. If the transistors in the figure are thoughtof as switches, it is not hard to see how these circuits implement their various logicfunctions. Their speed is largely determined by how much capacitance they haveto drive and how much current they can source or sink. The transistors in thesecircuits are usually sized by choosing width W and length L so that the pull-downand pull-up currents are equal. For example, transistors M5 and M6 will be ableto sink about four times as much current as transistors M3 and M4 if all transistorsare the same size and p-channel MOS (PMOS) and n-channel MOS (NMOS) arematched. This can be seen by assuming that all transistors have an on resistancegiven by

ron = RS LW D (5.1)

where R is a constant. Also note that the pull-down and pull-up currents will varyif there is more than one transistor in parallel. Thus, for instance, in Figure 5.2(b)the pull-down current will be twice as much if both A and B are high versus whatit would be if only A or B were high by itself.

The power dissipation of CMOS rail-to-rail logic can also be determined quiteeasily. If the CMOS gate is driving a load capacitance CL , then, each cycle, thecapacitor must be charged up to VDD and then discharged to VSS . Each time thishappens, the energy dissipated is

5.3 Large-Signal Behavior of Bipolar and CMOS Differential Pairs 121

Figure 5.2 CMOS digital logic gates: (a) inverter, (b) NOR gate, (c) NAND gate, and (d) XORgate.

E =CL (VDD − VSS)2

2(5.2)

Since both charging and discharging results in this dissipation, coming if theclock frequency is f, then the power dissipated in the gate is

P = CL (VDD − VSS)2 f (5.3)

5.3 Large-Signal Behavior of Bipolar and CMOS Differential Pairs

In CML, the dc current is constant, which leads to less switching noise. CMLcircuits are intrinsically differential, making interfaces with the analog parts of the


synthesizer easier as these blocks are often also differential for a variety of reasons.The basis for all CML is the differential pair [3]. It is important to switch the pairin digital applications, which means that a large enough differential voltage mustbe applied to the input. For the bipolar and CMOS cases, respectively, shown inFigure 5.3, the tail current as a function of either drain or collector currents canbe written as

IEE = iC1 + iC2 or IEE = iD1 + iD2 (5.4)

Also note that the input voltages can be written as the sum of base-emitter orgate-source voltages:

v1 = vBE1 − vBE2 or v1 = vGS1 − vGS2 (5.5)

We will need an expression for the collector or drain current as a function ofthe input voltage. We start, first, with the bipolar case, as it is simpler. The voltagecurrent relationship for a bipolar transistor is

iC = ISevBEvT (5.6)

Figure 5.3 Differential pairs in CMOS and bipolar technology.

5.3 Large-Signal Behavior of Bipolar and CMOS Differential Pairs 123

where IS is the transistor reverse saturation current, and vT is thermal voltage,kT /q, which is about 25 mV at room temperature. This can be written as

vBE = vT lnSiCISD (5.7)

Therefore, (5.5) can be rewritten as

v1 = vT lnSiC1ISD − vT lnSiC2

ISD (5.8)

Now, making use of (5.4),

v1 = vT lnSiC1ISD − vT lnSIEE − iC1

ISD (5.9)

After some manipulation,

ev1vT =

iC1IEE − iC1

(5.10)

iC1 = IEE1 ev1vT

1 + ev1vT2

iC2 can be solved in a similar way:

iC2 = IEE1 e−v1vT

1 + e−v1vT2 (5.11)

Thus, the bipolar differential pair is completely switched when v1 is approxi-mately 4vT or larger, regardless of the size of the transistor used or the current.Therefore, for maximum speed and minimum capacitance, minimum geometrydevices are preferred, provided noise is not an issue, and the current is not beyondthe peak fT current density.

Equations for the CMOS differential pair can be solved in a similar manner,although a few more steps are required. The simple square law voltage-currentrelationship for a CMOS transistor is

iD =mCox

2 SWL D (vGS − VT )2 (5.12)

which can be rewritten as


vGS = √ 2mCox

S LW D√iD + VT (5.13)

Therefore, (5.5) can be rewritten as

v1 = √ 2mCox

S LW D X√iD1 − √iD2 C (5.14)

Now, making use of (5.4),

v1 = √ 2mCox

S LW D X√iD1 − √IEE − iD1 C (5.15)

Now, squaring both sides of (5.15) gives

v 21 =

2mCox

S LW D XiD1 − 2√iD1√IEE − iD1 + IEE − iD1 C (5.16)

v 21 =

2mCox

S LW D XIEE − 2√iD1√IEE − iD1 C

Moving all terms with iD1 in them to one side yields

4mCox

S LW D√iD1√IEE − iD1 =

2mCox

S LW D IEE − v 2

1 (5.17)

Squaring, to remove the roots, results in

16

(mCox)2 S LW D2 XIEE iD1 − i 2

D1C =4

(mCox)2 S LW D2I 2

EE −4

mCoxS L

W D IEE v 21 + v 4

1

(5.18)

Collecting terms gives

16

(mCox)2 S LW D2 i 2

D1

−16

(mCox)2 S LW D2IEE iD1 +

4

(mCox)2 S LW D2I 2

EE −4

mCoxS L

W D IEE v 21 + v 4

1 = 0

i 2D1 − IEE iD1 +

14

I 2EE −

mCox4 SW

L D IEE v 21 +

(mCox)2

16 SWL D2v 4

1 = 0

(5.19)

5.4 Effect of Capacitance on Slew Rate 125

This can be solved for iD1 :

iD1 =IEE2 F1 ± √v 2

1mCoxIEE

SWL D −

(mCox)2

4I 2EE

SWL D2v 4

1 G (5.20)

The term inside the brackets will have a peak value of two at some inputvoltage of v1max. This voltage can be determined by setting the derivative of (5.20)to zero, and the result is given by

v1 max = √2IEE

mCox SWL D (5.21)

The current becomes

iD1 =IEE2

X1 ± √2 − 1 C =IEE2

(1 ± 1) = 0, IEE (5.22)

Clearly, (5.20) is no longer valid for values greater than v1max, as the equationthen incorrectly predicts that the current starts to decrease again. For larger valuesof voltage, one side continues to take all the current, and the other side just becomesmore firmly off. In real circuits, for large v1 , the source voltage then starts tofollow input voltage, limiting the total voltage to v1max.

Note that in (5.20) the ‘‘+’’ sign is correct for v1 greater than zero, and the‘‘−’’ sign is correct for v1 less than zero. Thus, the current moves around thequiescent point of IEE/2. In this case, complete switching is dependent on currentand device size. The current is completely switched when the term under the squareroot in (5.20) is one.

From (5.21), it can be seen that for larger current, the required switchingvoltage increases, while for larger W /L ratios, the switching voltage decreases.Since the switching voltage is inversely related to the square root of W /L, largeincreases of W /L are often required for a particular decrease in switching voltage.This can make it difficult to reduce switching voltage by this method. As an example,suppose we have a 0.1-mm technology. Then, for a width of 1 mm, the switchingvoltage (normalized to √2IEE /mCox) is 0.316; for a width of 10 mm, it is 0.1; andfor a width of 100 mm, it is 0.0316. Thus, beyond 10 mm, transistor size has tobecome large by IC standards to have much effect on switching voltage. For CML,a 10-mm transistor would already be quite large and require a large current toswitch quickly. Since speed is often an issue, using huge transistors is not a verypractical solution.

5.4 Effect of Capacitance on Slew Rate

The bias current through a differential pair required for proper operation at agiven speed is dependent on the load capacitance as well as the required output


swing. If there were no capacitance, then arbitrarily large output swings could beachieved with arbitrarily small currents. Of course, this is unrealistic. When thedifferential pair is fully switched, one side has no current such that the outputvoltage on this side is at the rail (VCC ), while the other side has all the currentflowing through it. Thus, the peak differential swing is

vo1 = VCC − IEERL (5.23)

Generally, the swing must be large enough to fully switch the following stagethat is being driven. Any additional swing is a waste of power. However, as outputwaveforms are not perfectly square, to switch faster, additional swing will berequired to ensure that the fully switched condition is satisfied over a longer periodof time. In the case of bipolar, 100–200-mV peak is typically considered to besufficient. In CMOS, usually more is required, depending on the current andtransistor sizes involved, but generally 200–400-mV peak is a good ballparknumber.

The load capacitance will determine the slew rate of the stage. The slew rateis the rate of change of the output voltage. For a capacitance C, the rate of changeof voltage is given by

dVdt

=1C

?dqdt

(5.24)

where q is the charge on the capacitor. Assuming that each side of the differentialpair has a load capacitance CL connected to it, the slew rate is given by

Slew rate =dvo1dt

=1

CL? Icap (5.25)

where Icap is the current flowing through the capacitor. The time required for theoutput to fully switch should be a small percentage of the period of the squarewave. Otherwise, the wave will have a triangular shape, as shown in Figure 5.4.

Figure 5.4 Illustration of the effect of slew rate on a square wave.

5.4 Effect of Capacitance on Slew Rate 127

Now the total transistor current ID is divided between the capacitor currentIcap and the load resistor current IR such that

ID = Icap + IR (5.26)

From (5.25) and making use of Ohm’s law, this can be rewritten as

ID = CLdvo1dt

+vo1RL

(5.27)

An important consideration is that the transistor current does not switch instan-taneously. This can lead to a lower slew rate than would otherwise be expectedfrom the equations above. Assume that the stage is being switched by another stagethat is also loaded by RLCL . With such loading, the bias current does not switchon or off instantaneously; rather, it has an exponential component to it. In orderto determine output voltages and currents, (5.27) must be modified to include achanging bias current:

ID (t) = IEE S1 − e−t

RLCLD = CLdvo1dt

+vo1RL

(5.28)

Solving this differential equation yields (for the case of current turning on)

vo1(t) = IEERL S1 − e−

tRLCL −

tRLCL

e−

tRLCLD (5.29)

In the case of current turning off, it yields

vo1(t) = IEERL Se−

tRLCL +

tRLCL

e−

tRLCLD (5.30)

The instantaneous current through the capacitor is the difference between thetotal current and the current in the resistor:

Icap(t) = ID(t) −vo1(t)

RL= ±IEE ?

tRLCL

? e−

tRLCL (5.31)

for either turning on or turning off the transistor current. Equations (5.31), (5.30),and (5.29) are plotted in Figure 5.5. One can see that, with the finite turn-on timeof transistor current, the maximum capacitor current is about 38% of IEE. If thetransistor had switched current instantaneously to IEE, the peak capacitor currentwould also have been IEE at the start of the transient.

Thus, a rough estimate for the time to switch logic levels through a circuitmade of CML inverters would be

Time to switch = 5 ? RLCL (5.32)


Figure 5.5 Illustration of the effect of slew rate on a square wave.

However, since the following circuit will start to switch when its input voltageis halfway to its final value, the time required (often simply called delay) is approxi-mately

Delay = 1.5 ? RLCL (5.33)

Thus, for n stages, the time between the first stage’s starting to switch and thenth stage’s starting to switch is

Delayn = 1.5 ? RLCL ? n (5.34)

For the circuit to reach maximum swing, the time to switch cannot be morethan one-half of a period. Therefore, from (5.32), the maximum frequency at whicha circuit could operate would be

fmax =1

10 ? RLCL(5.35)

The instantaneous slew rate as a function of time is

Slew rate = IEE ?t

RLC 2L

? e−

tRLCL (5.36)

Since slew rate is often useful for doing quick hand calculations, a quick estimateof the maximum slew rate is based on an estimate of IEE/3 as the maximumcapacitor current shown in Figure 5.5. The resulting slew rate is

5.5 Trade-Off Between Power Consumption and Speed 129

Slew rate =IEE

3CL(5.37)

5.5 Trade-Off Between Power Consumption and Speed

In general, with CML circuits, more current results in faster operation. This is abasic trade-off between current, load resistance, and capacitance. In bipolar CML,this relationship is simple because the transistors do not have to scale with changingbias current. If the current in a bipolar CML inverter is doubled, the load resistancewill be cut in half for the same output swing. Since current is doubled, but thecapacitance remains the same, the slew rate of the circuit is also doubled. WithCMOS, the effect of changing bias current is somewhat more complicated sincethe size of the transistors also needs to be adjusted to switch with a particularvoltage swing. For a given desired output swing vo , the required transistor size fora given current has previously been given as

vo = √2IEE

mCox SWL D (5.38)

If the current were doubled, then to keep the switching voltage constant, thetransistor W /L ratio would also have to be doubled. Therefore, the transistor sizewould double and so would its capacitance, keeping the slew rate roughly constant.Thus, it might seem that speed is independent of current. If this were the case, onewould always use minimum current; however, not all capacitance in the circuitwill double when the current is doubled. For example, one would expect theinterconnect capacitance to remain relatively constant, even when the transistorsize is doubled. Therefore, even with CMOS, higher currents do, in general, makefor faster circuits.

Example 5.1: Speed Versus Current Trade-Off in CML InvertersDetermine the delay through a set of four series-connected CML inverters (differen-tial amplifiers as shown in Figure 5.3) in 0.18-mm CMOS technology. Design theinverters to operate with a 1.8-V supply with a 500-mV peak-to-peak voltageswing, and set all the tail currents to the same value, first 100 mA, then 1 mA,and, finally, 10 mA. Assume that each circuit node has 20 fF of parasitic inter-connect capacitance loading it and, for this process, that mCox = 215 mA/V2 andCox = 6.5 fF/mm2.

Solution: The first step is to determine the required transistor size to switchwith a 500-mV peak signal. Since the waveforms should look approximately square,some margin should be allowed, so 300 mV for full switching will be used. Assuminga length of 0.18 mm for the transistors for maximum speed, the widths of thedevices can be determined from (5.38) as

W =2IEEL

mCoxv2o

= 1.9 mm, 19 mm, 190 mm


for the three currents. The load resistance for each current must give a voltagedrop of 500 mV when all of the tail current is being drawn through it. Therefore,

RL =voIEE

= 5 kV, 500V, 50V

for the three currents.Now, for each of these currents, the Cgs for the transistors can also be worked

out as

Cgs = WLCox = 2.2 fF, 22 fF, 222 fF

Thus, the total load capacitance for the three currents will be 22.2 fF, 42 fF,and 242 fF. Consequently, the time to switch through a stage for each of the threecurrents will be

Time to switch = 5 ? RCtotal

= 5 ? 5 kV (22.2 fF), 5 ? 500V (42 fF), 5 ? 50V (242.2 fF)

= 555 ps, 105 ps, 60.5 ps (5.39)

From this simple analysis, it can be seen that, if the parasitic capacitance islarger than the transistor capacitance, then more current is advantageous. However,if Cgs is dominant, then adding more current buys less advantage. The delay forfour stages can also be calculated as

Delayn = 1.5 ? RCtotal ? n

= 1.5 ? 5 kV (22.2 fF) ? 4, 1.5 ? 500V (42 fF) ? 4, 1.5 ? 50V (242.2 fF) ? 4

= 666 ps, 126 ps, 72.7 ps (5.40)

Thus, theoretically, the 100-mA design could function at a maximum speed ofapproximately 1 GHz. So, for the purposes of exploring this circuit, it will bedriven with a 1-GHz, 500-mV, ideal square wave, and the outputs will be observed.The output versus input voltage for the three designs is shown in Figure 5.6. Notethat the 100-mA design never fully reaches its output level. This is expected sincethe time to switch is estimated as 555 ps, but the input switches every 500 ps.Thus, it never fully reaches its maximum output level and slews for the entire500 ps allowed. The 1-mA design takes 120 ps to rise from about 10% to 90%of its final value, which is in line with prediction. The 10-mA waveform changesfrom about 10% to 90% of its final value in about 80 ps. This is also reasonablyclose to the prediction.

Figure 5.7 shows the delay through each of the four stages for the inverterswith tail current set to 1 mA. From this diagram, it can be seen that each stagehas a delay of about 30 ps (calculated by measuring the time between zero crossingsof consecutive stages) for a total of about 120 ps. Again, this is close to the predictedvalue. The other two delay times can be calculated from Figure 5.6 as 80 ps for

5.5 Trade-Off Between Power Consumption and Speed 131

Figure 5.6 Input and output voltages for a set of four CML inverter stages.

Figure 5.7 Input and output voltages for a set of four CML inverter stages showing the voltageswitching in each stage for a 1-mA current setting.

the inverters with 10 mA of current and as 350 ps in the inverters with 100 mAof current. Note that in this last instance, the prediction does not line up well withthe simulation results because the waveform shapes are no longer close to theshapes assumed in the derivation.


Drain current in one transistor in the last stage can be compared for the threecurrent levels and is shown in Figure 5.8. Note that the drain current appears morelike a square wave than does the output voltage, even for the 100-mA current level.Note that each curve has been normalized for easy comparison.

5.6 CML Combinational Circuits

For high-speed applications and for low switching noise, synthesizers do not alwaysuse standard CMOS logic, but use CML instead. By choosing the polarity of theoutputs appropriately, the differential pair already discussed can be used to makean inverter. Other common logic functions, such as AND, OR, and XOR gates,can be implemented as shown in Figure 5.9. If the inputs A and B are assumed tobe square waves of sufficient amplitude to switch the current flowing through thetransistors, then it is easy to prove correct functionality by tracing out the currentflow. For instance, in the OR gate, if A is high, then the current must flow throughM2 and M5 (note that M5 is included for level matching), pulling the negativeoutput low and, thus, producing logic one. If A is low, then B determines theoutput. With the differential CML topology, the CML AND gate is exactly thesame as the CML OR gate in structure, but the input and output polarities arechanged. This is not surprising, as DeMorgan’s law points out that

A ? B = A + B (5.41)

The XOR gate looks like a mixer, not surprisingly, since it is the same circuitexcept that, in a mixer, A would be small enough so that M1 and M2 would notswitch but would perform as a linear amplifier. As an XOR gate, it can be shownthat if either A or B, but not both, is high, a logic one is the result.

Figure 5.8 Drain current of one transistor in the last stage of a set of four CML inverter stages.

5.6 CML Combinational Circuits 133

Figure 5.9 Simple CML logic gates: (a) an OR gate, (b) an AND gate, and (c) an XOR gate.

An adder is another commonly used combinational logic block. Figure 5.10illustrates the CML logic circuits for the sum and carry-out of a 1-bit full adder,which implements the following logic expressions:

Sum = A ⊕ B ⊕ Cin (5.42)

Cout = A ? B + A ? Cin + B ? Cin

where Cin is the carry-in of the full adder. When a ripple adder is formed using ahalf adder for the least significant bit (LSB) and cascaded, 1-bit full adders for allother bits, the carry-in of the full adder is connected to the carry-out of the previous


Figure 5.10 A CML full adder logic circuit: (a) sum circuit, sum = A ⊕ B ⊕ C, and (b) carry-outcircuit, Cout = A ? B + A ? C in + B ? C in .

bit, as illustrated in Figure 5.11. Since the carry-in bit arrives later than the inputbits A and B, Cin is connected to the upper level of the CML circuits, where thedelay to the output is minimum.

5.7 CML Sequential Circuits

Unlike combinational logic circuits, sequential logic circuits have memory functionsdue to built-in feedback. Latches and flip-flops are building blocks of sequential

5.7 CML Sequential Circuits 135

Figure 5.11 A ripple adder formed by a half adder and cascaded full adders.

logic circuits. Although both latches and flip-flops are memory devices, a latchdiffers from a flip-flop in that a latch is not edge-triggered, with the result that itsoutput follows the input variations during the clock active phase, while a flip-flopis edge-triggered such that its output updates only at the clock transition. As willbe shown, two latches can be used to make a master-slave flip-flop, which isultimately used for the design of CML sequential circuits, such as dividers andphase detectors. A gated delay latch (D-latch) has two inputs, a clock CLK usedas the enable signal and an input signal D. When the clock goes high, the latchholds the previous value of the input until the clock goes low again. As shown inFigure 5.12, a D-latch operates as follows: when the clock is high, the latch isenabled and operates in ‘‘update’’ mode; that is, its output Q follows the inputsignal D. When the clock is low, the latch is in ‘‘hold’’ mode; that is, its outputQ holds the previous value. The D-latch state diagram is shown in Figure 5.12(b),where the two-digit number CD denotes the clock input and the data input, respec-tively, and d represents the ‘‘don’t care’’ input. A symbol for an active-high clockedD-latch is shown in Figure 5.12(c). Note that the circle in the output line indicatesinverted signal polarity.

The above-discussed D-latch characteristics can be expressed using the follow-ing logic equation:

Figure 5.12 Clocked D-latch (a) excitation table, (b) state diagram, and (c) symbol.


Q+ = D ? CLK + CLK ? Q (5.43)

where Q+ indicates the next state value of the latch output. Figure 5.13 illustratesa typical timing diagram for a positive-level sensitive D-latch. As shown, the outputof the latch follows the input change during the clock positive phase. Hence, thelatch is not an edge-triggered device. Instead, the clock signal is an enable signal; forthis reason, the latch is also called a level-triggered memory device to differentiate itfrom the edge-triggered flip-flops to be discussed in Section 5.8.

A MOS CML latch is usually implemented as shown in Figure 5.14. A bipolarlatch has the same topology. When CLK is low, all current is passed through M1 ,and M2 is off. Thus, M5 and M6 are also off and do nothing. In this state, thelatch behaves as if it were a differential pair, and the output follows the input.When CLK goes high, M1 turns off, turning off M3 and M4 . In this state, M5 andM6 turn on. These two transistors are connected in positive feedback, which latchesthe output value.

To understand this, consider the case when CLK goes high, and Q is also high.In this case, the gate of M6 is at VDD, while the gate of M5 is low. Thus, currentthrough M2 will be drawn mostly by M6 because it will have a much higher VGSthan does M5 . Since little current is drawn through M5 , the high value of Q willbe reinforced, and since M6 is drawing current, the low value of Q will be reinforced.If Q had been low, M5 would instead have turned on, reinforcing the low valueof Q. Thus, with M2 drawing current, the latch has been shown to be ‘‘holding’’its state.

Many variants of this basic circuit are possible. One variant useful for imple-menting a divide-by-three with 50% duty cycle is a latch with an invertible clock[4], shown in Figure 5.15(a). Here, when the u input is high, the clock signal passesthrough transistors M7 and M10 , but when u is low, the clock signal is inverted,passing through M8 and M9 .

Figure 5.13 Timing diagram showing a typical D-latch operation.

5.7 CML Sequential Circuits 137

Figure 5.14 CML D-latch circuit.

Figure 5.15 CML latch with invertible clock: (a) circuit implementation, and (b) logic diagram.


In comparison to the simple latch circuit shown in Figure 5.14, the extratransistors M7 through M10 act like an XOR, gating the clock. Thus, the logicdiagram for this latch needs to be modified to include this, as shown in Figure5.15(b).

The major advantage to adding the XOR gate, as shown in Figure 5.15, is thatstacking the circuits reduces the total current. This can only happen if the supplyvoltage in the process is high enough to allow such stacking. If such stacking isnot possible, the functions can still be implemented, but more tail-current sourceswill be needed to achieve the same logic function. Stacking can also be done withthe input as well as the clock. For example, Figure 5.16 shows an input thatincorporates an AND gate and a latch into one tail current.

Often it is desirable to be able to reset the latch to a known state, then torelease the reset asynchronously so that all the latches clocked by the same signalcan start their operations simultaneously. This is particularly important in orderto synchronize the flip-flops built using latches. If the supply voltage is high enoughto allow four-level transistor stacking, a resetable latch can be implemented byinserting a pair of reset transistors (Q7 and Q8) below the clock and input transis-tors, as shown in Figure 5.17. Note that RST_ is a convention for active-lowsignals. When the reset signal RST_ is low, transistor Q8 is turned on, which forcesthe current flow through the positive output path and causes the output Q to be

Figure 5.16 CML latch stacked with an AND gate: (a) circuit implementation, and (b) logic diagram.

5.8 Master-Slave D-Flip-Flop 139

Figure 5.17 CML latch with active-low reset using four-level transistors.

low. Meanwhile, transistor Q7 is turned off, which causes the output Q to be high.Overall, the latch is reset to zero when RST_ is low. However, with supply voltageslower than about 2.4V, it is very hard to keep all the bipolar transistors fromsaturation in four-level CML logic. A three-level, resetable latch can be implementedby placing the reset transistors in parallel with the latch transistors, as shown inFigure 5.18 [5]. The structure is a latch followed by an AND gate that providesthe reset function, with the final outputs fed back to clear the latch’s internalstate during the reset mode. This topology is very suitable for low supply voltageapplications.

5.8 Master-Slave D-Flip-Flop

As shown, the output of a latch is not stable. During the update phase, any inputchange will be passed to its output. Moreover, the transition of the latch outputis not synchronized to the clock edge. The problem can be solved by cascadingtwo latches in a master-slave (MS) configuration, as shown in Figure 5.19. Thetwo latches are driven by complementary clocks such that only one latch is activeat a time. During the negative phase of the clock, the master latch is active, and


Figure 5.18 CML latch with active-low reset using three-level transistors for low-supply voltageapplications.

Figure 5.19 MS D-flip-flop using two D-latches.

its output QM is updated according to current input, while the slave latch isdisabled, preventing the flip-flop output Q from changing. At the rising edge ofthe clock, the master latch changes from update to hold mode, while the slavelatch becomes enabled, passing the last captured QM value to the flip-flop outputQ. During the positive phase of the clock, the master latch is disabled, preventingthe flip-flop output Q from changing, even if the slave latch is in update mode.Thus, the transition of the MS flip-flop output is only allowed at the rising edgeof the clock signal. From this point of view, the MS flip-flop is an edge-triggereddevice. However, data captured in an MS flip-flop is not quite edge-triggered. Any

5.8 Master-Slave D-Flip-Flop 141

input change during the negative phase of the clock will be captured at the masterlatch output QM , although only the last update captured right before the clockrising edge will be passed to the flip-flop output.

The behavior of the MS D-flip-flop can be summarized as

Q+ = D (5.44)

and is also shown in Figure 5.20.Therefore, the new output (Q+ ) of the D-flip-flop always assumes the value

of its input (D) at the clock rising edge. Note that there is a delay through the flip-flop. Thus, if a signal arrives at the input of the flip-flop, it must wait one clockcycle to be passed to the output. Thus, a flip-flop is one way to implement a unitdelay; in other words, it has a transfer function of z−1. The MS D-flip-flop can beimplemented in a CML topology as shown in Figure 5.21. Note that emitterfollowers (labeled EF in Figure 5.21) are used in series with the latch cross-couplingtransistors to prevent the latch transistors from saturating and to provide drive

Figure 5.20 MS D-flip-flop: (a) excitation table, and (b) state diagram.

Figure 5.21 CML MS D-flip-flop.


capability between the stages. If power consumption is a concern or the supplyvoltage does not provide enough headroom for a four-level transistor topology,the emitter followers can be omitted. In such a case, the latch transistors are soft-saturated with an ac swing larger than 200 mV since their base and collector arebiased at the same dc voltage.

5.9 CML Circuit-Delay Analysis

To understand the CML circuit operation speed, the delay-time constants need tobe modeled for a series-gated bipolar CML D-latch, which is the common basicbuilding block of many high-speed switching circuits. Figure 5.22 illustrates theD-latch, half-circuit, small-signal model, where Rc_pre denotes the load resistanceof the previous CML stage. For worst-case propagation delay, the upper-level datainputs are set as constant, and a step is provided at the input of the lower-level clocktransistors [6, 7]. We assume that transistors Q3 and Q5 are on, and transistors Q4and Q6 are off. The load parasitic capacitance CL2 is ignored since only dc currentflow occurs in the half-circuit analysis. The analysis of the half circuit is sufficientfor differential operations. The delay model can apply not only to CML sequentialcircuits, such as the D-latch, but also to any combinational circuits, such as AND,OR, and XOR gates.

Figure 5.22 D-latch, half-circuit, small-signal model.

5.9 CML Circuit-Delay Analysis 143

The delay through the CML D-latch can be expressed as the sum of RC timeconstants, assuming dominant pole behavior [8]. The time constants associatedwith various capacitors for lower transistors in the equivalent circuit model aregiven by

tp1 =re1 + rb1

1 + gm1 re1 +re1 + rb1

rp1

Cp1

t bcx1 = Src1 + re3 +rp3 + rb3 + Rc_pre

b + 1 DCbcx1

t bci1 = 5Src3 + re3 +rp3 + rb3 + Rc_pre

b + 1 D (5.45)

+ rb131 +gm1Src1 + re3 +

rp3 + rb3 + Rc_pre

b + 1+ re1D

1 + gm1 re1 46 ? Cbci1

t cs1 = Src1 + re3 +rp3 + rb3 + Rc_pre

b + 1 DCcs1

The time constants for upper transistors are listed as follows:

tp3 =1

Sgm3 +1

rp3D ? Cp3

t bci3 = (2Rc_pre + rc3 + rb3) ? Cbci3

t bcx3 = (2Rc_pre + rc3) ? Cbcx3

t bci5 = (2Rc_pre + rc5 + rb5) ? Cbci5 (5.46)

t bcx5 = (2Rc_pre + rc5) ? Cbcx5 , t cs3 = (Rc_pre + rc3) ? Ccs3

t cs5 = (Rc_pre + rc5) ? Ccs5

t je4 = (Rc_pre + rb4 + 2re4) ? Cje4

t cload = RC1 ? CL1

where subscripts c, b, e, and s mean collector, base, emitter, and substrate of thecorresponding transistors; p denotes base-emitter junction; subscripts i and x denotethe intrinsic and extrinsic parts of the base-collector capacitances; and subscriptje denotes the junction capacitance. The delays associated with upper and lowertransistors can be found by summing all the delays in (5.45) and (5.46):


tlower = tp1 + t bci1 + t bc1 + t cs1

tupper = tp3 + t bci3 + t bcx3 + t bci5 + t bcx5 + t cs3 + t cs5 + t je4 + t cload (5.47)

ttotal = 0.69 × (tlower + tupper )

At any junction where voltages change rapidly by a large amount, those junctioncapacitances are modified from zero bias value Cjo as K ? Cjo by using coefficientK, given by [6]

K = S fm

V2 − V1DF(f − V1)1 − m

1 − m−

(f − V2)1 − m

1 − m G (5.48)

where the ac swing is from voltage V1 to V2, and an ac voltage swing of ±150mVpp is considered to be large, f is the built-in potential across the junction underzero bias, and m is the grading coefficient and equals 1/2 for an abrupt junction.The transistor capacitances are assumed to be constant when bias current varies,which is a good approximation at low bias current.

5.10 Low-Power CML Circuits

CML circuit design always involves trade-offs between power consumption andspeed. The delay model developed in the previous sections can be used to optimizeCML circuits to improve circuit performance in terms of power consumption andspeed. Using the delay models developed in previous sections, Figure 5.23 showsthe CML D-latch propagation delay with respect to the bias current [9].

It comes as no surprise that the optimum biasing current for minimum delayis the transistor peak fT current. According to Figure 5.23, it is obvious that thereis not much speed improvement by increasing the biasing current beyond 60% ofthe peak fT current. Biasing the circuit close to the peak fT current may cause theactual bias current to go beyond the peak fT current under temperature, supply,and process variations, which leads to a dramatic speed penalty as a result ofcurrent crowding and conductivity-modulation effects in the base region. Unlessthe absolute maximum speed of operation is required, it is good practice to biasthe CML circuit with less than 60% of the peak fT current to save unnecessarypower consumption. Figure 5.23 shows that biasing the CML circuits at about60% of the peak fT current (0.9 mA) can achieve about 80% of the maximumspeed that would have been achieved at the peak fT current.

Moreover, it is evident that the CML latch delay is dominated by the delayassociated with the upper transistors. Hence, reducing the delay due to upper-leveltransistors is critical to improving CML switching speed. The optimum bias currentfor minimum delay is not the same for upper- and lower-level transistors. Thelower transistors have minimum delay at lower bias current. It is thus intuitivethat there will be a speed improvement if the CML circuit is biased with slightlyhigher bias current for the upper-level transistors than for the lower-level transistors.For instance, with the same total bias current, the bias currents can be reduced byabout 20% for the lower-level transistors and increased by 20% for the upper-

5.10 Low-Power CML Circuits 145

Figure 5.23 CML D-latch delay versus bias current for a transistor size of 0.5 mm by 2.5 mm.

level transistors. Figure 5.24 illustrates a modified CML D-latch biased in such amanner. The technique is called ‘‘keep alive’’ since there will always be a smallamount of bias current flowing through the upper-level transistors, keeping themalive in slightly on states, regardless of the clock and data. As a result, the capacitorsassociated with the upper-level transistors, which are the dominant contributors

Figure 5.24 CML D-latch with keep-alive topology.


to the CML propagation delay, will be precharged to a certain level before theclock is enabled. When the clock is enabled, the upper-level capacitors will needrelatively less time to reach their steady-state values. Moreover, optimization canalso be performed in terms of transistor sizing for upper and lower transistors. Aspeed improvement of about 11% can be achieved by using the keep-alive CMLtopology [9]. The keep-alive technique does not increase the power consumption,but the output noise margin (voltage swing) is slightly reduced; that is, noise marginis traded for circuit speed and power consumption.

5.11 CML Biasing Circuits

So far, all the current sources in the CML circuits have been shown as ideal, butthese are an important part of the design as well. Their design depends on thetechnology being used, but, fundamentally, a current source consists of a currentmirror of some kind, with the reference current typically generated by a bandgapcircuit.

In bipolar technology, a current-mirror biasing circuit could look like thatshown in Figure 5.25(a). In this mirror, the current is scaled up N times from thereference produced by the bandgap circuit. Resistors RE and NRE are included toincrease the output impedance of the current mirror and to improve matchingbetween the diode connected transistor Q1 and the current source transistor NQ1 .This is because the current-voltage relationship in a bipolar transistor is exponential;thus, the sensitivity of the output current to changes in VBE is greater than thesensitivity of the output current to changes in RE . An additional feature of thiscurrent source is the addition of transistor Q2 to provide base current to the mainmirror transistors, thus improving current matching. The capacitor C is includedto reduce the circuit noise, and RBL is included to ensure that transistor Q2 isalways biased in the active region.

The output impedance of the current mirror can be computed with the aid ofFigure 5.25(b). Here, it is assumed that transistor Q1 , being essentially diode

Figure 5.25 (a) A bipolar current source, and (b) a simplified model for calculating the outputimpedance.

5.11 CML Biasing Circuits 147

connected, provides a short circuit (low impedance path) to ground. Then, theoutput impedance of this circuit is given by

Zout =RE //re + ro

1 − gmRE //re(5.49)

Note that, as expected, the value of Zout reduces to be simply ro if no degenera-tion is added to the circuit; however, it is clear that even a small amount ofdegeneration will add significantly to the output impedance of the circuit. Thisimpedance, when combined with parasitic capacitance connected to the output ofthe current mirror, can be used to determine at which frequency the output imped-ance will start to decrease and, thus, help to determine the frequencies at whichthis structure will provide a useful current source.

In CMOS technologies, it is not as common to use degeneration resistors as itis in bipolar technology. However, since CMOS typically has much lower outputimpedance, often cascode transistors are included, as shown in Figure 5.26(a).Also, if current matching is a concern, then the voltage at the drain of both M3and M2 should be matched as closely as possible. These cascode transistors alsoprovide an additional degree of freedom in the design of the mirror. As an example,the switching speed of a CML stage can be affected by the output capacitance ofits current source (switching the stage means that second harmonic voltage willappear on the tail-current source). For a single-transistor current source, there isa trade-off between output impedance and capacitance. However, with a cascodecurrent source, the cascode transistor can be chosen to be of a minimum lengthto minimize capacitance, and longer channel devices can be used for transistorsM1 and NM1 for high output impedance.

The output impedance of the current mirror can be computed with the aid ofFigure 5.26(b). Here, it is assumed that transistor M1 , being essentially diodeconnected, provides a short circuit (low impedance path) to ground. This meansthat the current source of M2 is not active as the gate and source are ac grounded.Thus, the output impedance of this circuit is given by

Figure 5.26 (a) A CMOS current source and (b) a simplified model for calculating the outputimpedance.


Zout =(ro3 + ro2 − gmro2ro3)

1 − 2gmro2(5.50)

Note that the value of Zout reduces to be simply ro2 if no cascode is used. Thisimpedance, when combined with parasitic capacitance connected to the output ofthe current mirror, can be used to determine at which frequency the output imped-ance will start to decrease and, thus, help to determine the frequencies at whichthis structure will provide a useful current source.

Now it is also necessary to provide reference currents that are supply andtemperature independent [10–13]. Since circuit performance in a silicon process isaffected by temperature, supply voltage, and process variations, it is possible tofind dependencies that cancel one another. To start, consider the bipolar baseemitter voltage characteristic described in Appendix B:

VBE =kTq

lnICIS

(5.51)

This expression seems to show that base-emitter voltage is directly proportionalto temperature; however, IS has a large temperature dependence as well. An expres-sion for VBE as a function of temperature is [14, 15]

VBE = VBG S1 −TT0D + VBE0

TT0

+2.3 ? kT

qln

T0T

+kTq

ln S ICIC0

D (5.52)

where T0 is the reference temperature, VBE0 is the base-emitter voltage at thereference temperature, and VBG is the bandgap voltage of silicon (approximately1.206V). Even though it may not be immediately obvious from this expression,VBE will actually decrease for a constant collector current with increasing tempera-ture. Thus, if the collector current is assumed to be constant, then the derivativeof VBE with respect to temperature is

dVBEdT

=VBE0 − VBG

T0+

2.3 ? kq

lnT0T

+−2.3 ? k

q(5.53)

Note that this expression shows that not a lot can be done to adjust the slopeof the temperature dependence.

Next, to cancel this negative temperature/voltage relationship, a voltage thatincreases with temperature must be found. To do this, assume that two BJTs arebiased at different currents. Then, the difference between their base-emitter voltageswill be given by

DV = VBE1 − VBE2 =kTq

lnIC1IS

−kTq

lnIC2IS

=kTq

lnIC1IC2

(5.54)

Since (5.54) does not contain IS , this relationship is much simpler than (5.52),and this voltage is directly proportional to temperature. In this case, the slope ofthe temperature dependence is given by

5.11 CML Biasing Circuits 149

dDVdT

=kq

lnIC1IC2

=kq

ln m (5.55)

Therefore, the slope can be adjusted by changing m, the ratio of IC1 to IC2 ,and, by proper choice, can be made equal in magnitude and opposite in sign to(5.53).

A simple circuit that could be used to generate a bandgap reference is shownin Figure 5.27. In this circuit, the op-amp is used to keep the voltage at the collectorof Q1 and the voltage at the top of the resistor R the same by adjusting the valueof the VGS of the identical PMOS transistors. Thus, the voltage Vref is given by

Vref = VBE1 = VBE2 + VR (5.56)

where VR is the voltage drop across the resistor R.Therefore, the voltage across the resistor R can also be given by

VR = VBE1 − VBE2 (5.57)

VR is therefore equal to the difference in the two base-emitter voltage drops.Thus, Vref is given by

Vref = VR + VBE2 (5.58)

and therefore is made up of two voltages that have opposite temperature depen-dences and consequently this voltage can be made to be independent of temperature.The current through the circuit is given by

Iref =VBE1 − VBE2

R(5.59)

Figure 5.27 A simple bandgap reference generator with an output current proportional to absolutetemperature.


Thus, current is proportional to absolute temperature. This current can bescaled or mirrored to other PMOS transistors to create as many copies as is needed.

Note that, in practice, this circuit requires a startup circuit because, in additionto the solution just assumed, the condition where all currents in the circuit arezero will also provide a stable operating point for the op-amp. Startup could beaccomplished by injecting some current into the circuit at power up.

5.12 Driver Circuits

In modern ICs, often the synthesizer clock will have to be routed all over the chip.In most ICs, this will mean the need to drive millimeters of interconnect. There ismuch debate over how best to do this. Regardless of which approach is adopted,the driver circuit will require a large current. As a result, efficient design of thesecircuits is important. In addition, driving this amount of interconnect will meanthat a lot of inductance and capacitance will act to degrade the signal. The twomost obvious choices for driver circuits are the inverter and the emitter/sourcefollower circuits. Figure 5.28 shows an emitter follower (using a bipolar transistor).The equivalent circuit with bipolar transistors replaced with MOS transistors wouldbe called a source follower. Emitter and source followers work well at low frequen-cies, where inductance is not as much of a problem as capacitance, but they tendto work less well at higher frequencies. This is because their low output impedancereduces the effective RC time constant on the line. However, since they drive voltagerather than current, the inductance of the line forms a voltage divider with theload at higher frequencies.

Inverter circuits can also work quite well but often require very large currentsto keep their RC time constants low. They can also be connected in a cascodeconfiguration to allow them to drive a fairly low load impedance (although, throughswitching action, this will not be as low as might be expected), as shown in Figure5.29.

A superior approach is to combine these two circuits in a push-pull arrangement,as shown in Figure 5.30. Here, a follower circuit is combined with an inverterstage to drive a transmission line. The idea is that for half of the cycle, the followerM3 supplies current to the transmission line while current is sunk out of the

Figure 5.28 Followers as interconnect driver circuits.

5.12 Driver Circuits 151

Figure 5.29 Inverter circuits as interconnect driver circuits.

Figure 5.30 Efficient push-pull output buffer.


transmission line by the inverter transistor M2 . Meanwhile, transistors M4 andM1 are off. In the other half of the cycle, the follower M4 turns on, and currentis sunk out of the transmission line by the inverter transistor M1 . Since in thiscircuit almost all the current ends up flowing through the transmission line andvery little is wasted just biasing the transistors, this circuit can provide very square-looking waves using minimal current. The only other wrinkle to the proper designof this stage is that, for best operation, the clock edges in the four transistors haveto be lined up properly. Since the delay through the two amplifiers is usuallydifferent, another stage may have to be used ahead of the actual driver to providea delay to line up the clock edges.

References

[1] Sedra, A. S., and K. C. Smith, Microelectronic Circuits, 5th ed., New York: Oxford Press,2004.

[2] Jaeger, R. C., and T. N. Blalock, Microelectronic Circuit Design, 2nd ed., New York:McGraw-Hill, 2004.

[3] Baker, R. J., H. W. Li, and D. E. Boyce, CMOS Circuit Design, Layout, and Simulation,New York: IEEE Press, 1998.

[4] Magoon, R., and A. Molnar, ‘‘RF local Oscillator Path for GSM Direct ConversionTransceiver with True 50% Duty Cycle Divide by Three and Active Third HarmonicCancellation,’’ IEEE Radio Frequency Integrated Circuit Symposium, Seattle, WA, 2002,pp. 23–26.

[5] Dai, F. F., et al., ‘‘A Low Power 5 GHz Direct Digital Synthesizer Implemented in SiGeTechnology,’’ IEEE 5th Topical Meeting on Silicon Monolithic Integrated Circuits in RFSystems, Atlanta, GA, September 2004.

[6] Rabaey, J. M., A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits: A DesignPerspective, 2nd ed., Upper Saddle River, NJ: Prentice Hall, 2003.

[7] Alioto, M., and G. Palumbo, ‘‘Modeling and Optimized Design of Current Mode MUX/XOR and D-Flip-Flop,’’ IEEE Transactions on Circuits and Systems-II, Vol. 47, No. 5,May 2000, pp. 452–461.

[8] Sharaf, K. M., and M. Elmasry, ‘‘An Accurate Analytical Propagation Delay Model forHigh-Speed CML Bipolar Circuits,’’ IEEE J. Solid-State Circuits, Vol. 29, January 1994,pp. 31–45.

[9] Kakani, V., F. F. Dai, and R. C. Jaeger, ‘‘Delay Analysis and Optimal Biasing for HighSpeed Low Power CML Circuits,’’ IEEE International Symposium on Circuits and Systems(ISCAS), Vancouver, Canada, May 2004, pp. 869–872.

[10] Johns, D. A., and K. Martin, Analog Integrated Circuit Design, New York: John Wiley &Sons, 1997.

[11] Razavi, B., Design of Analog CMOS Integrated Circuits, New York: McGraw-Hill, 2001.[12] Lee, T. H., The Design of CMOS Radio Frequency Integrated Circuits, Cambridge, United

Kingdom: Cambridge University Press, 1998.[13] Grey, P. R., et al., Analysis and Design of Analog Integrated Circuits, 4th ed., Cambridge,

United Kingdom: Cambridge University Press, 1998.[14] Brugler, J., ‘‘Silicon Transistor Biasing for Linear Collector Current Temperature Depen-

dence,’’ IEEE J. Solid-State Circuits, Vol. SC-2, June 1967, pp. 57–58.[15] Tsividis, Y., ‘‘Accurate Analysis of Temperature Effects in IC–VBE Characteristics with

Application to Bandgap Reference Sources,’’ IEEE J. Solid-State Circuits, Vol. 15,December 1980, pp. 1076–1084.

cmos logic and current-mode logic

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