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 Open the Microwind Editor window.

Select the Foundry file from File menu. Select “cmos025.rul ” file.

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Draw the layout of 2 input NAND gate baed on the tic! diagram in "igure #.

Use : NMOS size - W=6 , L=2

  PMOS size - W=12 , L=2

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 Change to white backgo!n"

Ma!e ure that your layout obey all the deign rule.

$un D$% by electing&

>Analysis>Design Rule Checker

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Simulate the Nand gate layout by electing&

>Simulate> Run Simulation>Voltage vs Time (default) on the main menu.

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 #$M$N% &$'%('M

'art ( & Simulating the layout of a (oolean e)uation.

*. Simulate the (oolean e)uation layout. +et the the timing diagram of the circuit.

2. Determine the propagation delay of the output. $ie time &,-n, "all time &,*n,..

#. Specify the i/e of your deigned circuit & 000000000 λ 1 000000000 λ Area 000000000000 λ 2