cmos complementary logic 2
TRANSCRIPT
-
8/6/2019 Cmos Complementary Logic 2
1/7
Institute ofMicroelectronicSystems
7. Complementary MOS (CMOS)Logic Design
7: CMOS Logic 2
Institute ofMicroelectronicSystems
Basic CMOS Logic Gate Structure
PMOS and NMOSswitching networks arecomplementary
Either the PMOS orthe NMOS network ison while the other isoff
No static powerdissipation
VDD
LogicInputs
PMOS SwitchingNetwork
NMOS SwitchingNetwork
Y
-
8/6/2019 Cmos Complementary Logic 2
2/7
7: CMOS Logic 3
Institute ofMicroelectronicSystems
CMOS NOR Gate
MN
v I
M P
V = 5 VDD
vo
2
1
5
1
V = 5 VDD
A B
Z
101
101
2
12
1
NOR Gate Truth Table
A B
0 0
0 1
1 01 1
1
0
00
Z = A + B
7: CMOS Logic 4
Institute ofMicroelectronicSystems
Transistor Sizing for CMOS Gates: Review
Goal: To maintain the delay times equal the reference inverter designunder the worst-case input conditions
Example: 2 input CMOS NOR gate
- Each transistor of the NMOS network is capable of discharging
individually the load capacitance C Same size as NMOStransistor of reference inverter
- PMOS network conducts only when AB = 00 (Transistors in
serie) Each PMOS must be twice larger( On-resistance proportional to (W/L)-1 )
-
8/6/2019 Cmos Complementary Logic 2
3/7
7: CMOS Logic 5
Institute ofMicroelectronicSystems
CMOS NAND Gate
MN
vI v O
MP
V = 5 VDD
2
1
5
1
Z
V = 5 VDD
4
1A
B
5
1
5
1
4
1
A B Z = AB
0 00 11 01 1
1110
NAND Gate Truth Table
7: CMOS Logic 6
Institute ofMicroelectronicSystems
Multi-Input NAND Gate
C
V = 5 VDD
A
B
C
Y
D
E
Y
15
15
1
515
1
5
1
10
110
1
10
110
110
Y= ABCDE
Why should oneprefer a NANDgate rather than aNOR gate?
-
8/6/2019 Cmos Complementary Logic 2
4/7
7: CMOS Logic 7
Institute ofMicroelectronicSystems
Steps in Constructing Graphs for NMOS andPMOS Networks (I)
Y = A + B (C + D)
+5 V
M AA
Y
PMOSSwitch
Network
ABCD
M CCMDD
MBB
C + D
B (C + D)
A + B (C + D)
7: CMOS Logic 8
Institute ofMicroelectronicSystems
Steps in Constructing Graphs for NMOS andPMOS Networks (II)
0
1
2
A
B
CD
(b) NMOS Graph
1
+5 V
M AA21
Y
PMOSSwitchNetwork
ABCD
2
3
M CCMDD
MBB
41
41
4
1
0
1
(a)
3
4
2
0
1
2
A
B
C
D
2
3
4
5
(c) NMOS Graph with
New Nodes Added
0
1
2
A
B
C
D
2
34
5
(d) Graph with
PMOS Arcs Added
-
8/6/2019 Cmos Complementary Logic 2
5/7
7: CMOS Logic 9
Institute ofMicroelectronicSystems
Steps in Constructing Graphs for NMOS andPMOS Networks (III)
+5 V
M CC MDDMAA
M BB
41
21
Y
41
41
4
B
A
C
D
151
151
151
7.51
Final CMOS Circuit
3
4
5
2
1
0
1
2
A
B
C
D
2
34
5
Graph with
PMOS Arcs Added
7: CMOS Logic 10
Institute ofMicroelectronicSystems
Summary
AND - serially connected FET
OR - parallel connected FET
NMOS network implementszeros
PMOS network implementsones
W/L ratio has to be determined asa design parameter
+5 V
M CC
MDD
MAA
M BB
41
21
Y
41
41
B
A
C
D
151
151
151
7.51
-
8/6/2019 Cmos Complementary Logic 2
6/7
7: CMOS Logic 11
Institute ofMicroelectronicSystems
CMOS Gate Design: Minimum Size Vs.Performance (I)
CMOS circuit with onlyminimum size transistors
Considerable savings in chip area,but increased logic delay
Example:
7: CMOS Logic 12
Institute ofMicroelectronicSystems
CMOS Gate Design: Minimum Size Vs.Performance (II)
(W/L) for PMOS network = 2/3 PLHIPLHIPLH 5.7
3
2
1
5
=
=
of reference inverterPLHPLHI =
The average propagation delay of the minimum size logic gate is:
( ) ( )PLHI
PLHIPLHIPHLIPLHPHLP
75.42
5.9
2
5.72
2==
+=
+=
Mininimum size gate will 4.75 times slower than reference inverter whendriving the same load capacitance
For NMOS networkPHLIPHL
2=
-
8/6/2019 Cmos Complementary Logic 2
7/7
7: CMOS Logic 13
Institute ofMicroelectronicSystems
Power-Delay Product (PDP)
The PDP is an important figure of merit for a logic technology
PAVPPDP =
For CMOS: fCVP DDAV 2= withT
f 1=
CMOS switching waveform
7: CMOS Logic 14
Institute ofMicroelectronicSystems
Power-Delay Product (contd)
bfar ttttT +++ The period T must satisfy:
Assumptions: At high frequencies ta 0 and tb 0, tr and tf account forapproximately 80 % of the total transition time
For symmetrical inverter:
( )P
PrtT
58.0
22
8.0
2==
55
22
DDP
P
DD CVCVPDP =