cloudnet 2013 an efficient flow cache algorithm with improved fairness in software-defined data...
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CloudNet 2013
An Efficient Flow Cache algorithm with Improved
Fairness in Software-Defined Data Center Networks
Bu Sung Lee 1, Renuga Kanagavelu2 and Khin Mi Mi Aung2
1Nanyang Technological University, Singapore2 A-STAR (Agency for Science and Technology), Data
Storage Institute, Singapore
CloudNet 2013
Changing scene in DC
• Data Center size has grown to a scale that we never imagine (http://storageservers.wordpress.com/2013/07/17/facts-and-stats-of-worlds-largest-data-centers
/ ) . – Google: 900,000 servers across 13 data centers– Amazon: 450,000 servers, in 7 locations
• Virtualisation.• Changing Data Center Network traffic (North-South to
East-West)• Traffic Types : mice and elephant.
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Constraints
• Openflow switches flow table can hold up to 1500 entries.
• It is possible to increase TCAM entries, but it consumes lots of ASIC space, power and cost.
• Centralized controller
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Limitations of 3-tier network architecture
Address Interface Time
62-FE-F7-11-89-A3
1 9:32
7C-BA-B2-B4-91-10
2 9:47
… … …
Table size increases proportionally to the number of servers => Scalability issue
Racks of servers
Top of Rack Switches
Aggregation Switches
Core Switch
…… …Interface 1
Interface 2
MAC Addr: 62-FE-F7-11-89-A3
MAC Addr: 7C-BA-B2-B4-91-10
Redundant paths are not used (due to STP) => Total bandwidth reduction issue
Forwarding table:
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Traffic types
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Technology used
• Flow cache organised into separate buckets for elephant and mice.– Determine flow type by using 100 Mbytes in 5 second
threshold.– Used the vLAN priority code bit (PCB) to indicate. – Uses dynamic index hashing.
• Cache replacement strategy– Uses Least Recently Used (LRU)
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Experimental set-up
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Architecture
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Dynamic index Hashing
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Bucket Expansion
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Performance Evaluation
Comparison of cache hit Ratio
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Performance Evaluation
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1k 2k 4k 8k0
1
2
3
4
5
6
Look up vs cache Bucket size
Wild-card Linear
Mice-Dynamic Index Hashing
Elephant-Dynamic Index Hashing
cache bucket size
look
up
time(
ms)
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Performance Evaluation Look up Time
0 1 2 3 4 5 6 7 80%
20%
40%
60%
80%
100%
Linear
look up (500)
look up (1000)
look up (1500)
look up (3000)
look up (5000)
Look up time (ms)
Per
cen
tag
e
0 1 2 3 4 5 6 70%
20%
40%
60%
80%
100%
Mice
look up (500)
look up (1000)
look up (1500)
look up (3000)
look up (5000)
Look up time (ms)
Per
cen
tag
e
0 0.5 1 1.5 2 2.5 3 3.5 40%
20%
40%
60%
80%
100%Elephant
look up (500)
look up (1000)
look up (1500)
look up (3000)
look up (5000)
Look up time (ms)
Per
cen
tag
e
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Performance Evaluation
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DDR3 SDRAM16bits
DDR3 SDRAM16bits
DDR3 SDRAM16bitsMemory
Memory Controller
64 bits (8Bytes)
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Look-Aside Interface
SHA - 1
Look upUpdateDrop
Add entry
Output Buffer
Input Buffer
Header
Action
Header Action
SHA Value
Cache architecture
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Conclusions
• Simple and effective means to address the overload on the controller
• Fast lookup• Reduced cache miss ratio with LRU• We have developed a NVRAM version of the cache for
plugging into switches.
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Future work
• DC VM Placement strategy– Power aware– Network aware– Resilience
• Inter-domain Openflow
• Software defined everything
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