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8/7/2019 Class Notes Digital Lec01

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Telephone :

PABX : 9661920-73/4980

DEPT. OF APPLIED PHYSICS, ELECTRONICS &

COMMUNICATION ENGINEERING

UNIVERSITY OF DHAKA

DHAKA-1000, BANGLADESH

FAX: 880-2-8615583

E-MAIL: [email protected]

Ref. No............................ Dated, the.

In case of any query or suggestion please contact Sazzad, Lecturer, APECE, DU (url: sazzadmsi.webs.com)

Multiplexer/Data Selector:

Fig.: Functional diagram of a digital multiplexer (MUX).A digital multiplexer or data selector is a logic circuit that accepts several digital data inputs and selects one of themat any given time to pass on to the output. The routing of the desired data input to the output is controlled by SELECTinputs, also referred to as ADDRESS inputs.The multiplexer acts like a digitally controlled multiposition switch where the digital code applied to the SELECTinputs controls which data inputs will be switched to the output.A multiplexer selects 1 out of N input data sources and transmits the selected data to a single output channel. This iscalled multiplexing.

Basic Two-Input Multiplexer:

Fig.: Two-input multiplexer.Figure shows the logic circuitry for a two-input multiplexer with data inputs I0 and I1 and SELECT input S.The logic level applied to the S input determines which AND gate is enabled so that its data input passes through theOR gate to output Z.The Boolean expression for the output is

SISIZ 10 +=

With S=0, the expression becomes Z=I0.1+I1.0=I0

I0

I1

IN-1

DATA

inputs

SELECTinputs

Output

Z

MUX

1

2

I1

I0

S

DATAinputs

SELECT input

SISIZ .. 10 +=

S Output

01

Z=I0Z=I1

Lec-01, Pg-01


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Telephone :

PABX : 9661920-73/4980



UNIVERSITY OF DHAKA


FAX: 880-2-8615583


Ref. No............................ Dated, the.


which indicates that Z will be identical to input signal I0, which in turn can be a fixed logic level or a time-varying logicsignal.With S=1, the expression becomes

Z=I0.0+I1.1=I1showing that the output Z will be identical to input signal I 1.

Four-Input Multiplexer:

Fig.: Four-input multiplexer.Here there are four inputs I0, I1, I2 and I3, which are selectively transmitted to the output according to the fourpossible combinations of the S1S0 select inputs. The Boolean expression for the output is

013012011010 ........ SSISSISSISSIZ +++=

I0 is gated with 01SS so that I0 will pass through its AND gate to output Z only when S1=0 and S0=0.

Thus, each data input is gated with a different combination of select input levels.

S1 S0 Output

0 00 11 01 1

Z=I0Z=I1Z=I2Z=I3

1

3

I1

I0

S0

2

4

I2

I3

S1

Z

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Telephone :

PABX : 9661920-73/4980



UNIVERSITY OF DHAKA


FAX: 880-2-8615583


Ref. No............................ Dated, the.


Eight-Input Multiplexer:

Fig.: 74151 Multiplexer logic diagram, truth table and logic symbol.Figure shows the logic diagram for the 74151 eight-input multiplexer. The Boolean expression for the output is

0127012601250124

0123012201210120

............

............

SSSISSSISSSISSSI

SSSISSSISSSISSSIZ

++++

+++=

This multiplexer has an enable input E and provides both normal and the inverted outputs.

When 0=E , the select inputs S2S1S0 will select one data input, from I0 through I7, for passage to output Z.

When 1=E , the multiplexer is disabled so that Z=0 regardless of the select input code.

S2

S1

S0

E

I0 I1 I2 I3 I4 I5 I6 I7

ZZ

Inputs Outputs

E S2 S1 S0 Z Z

H X X X H L

L L L L 0I I0

L L L H 1I I1

L L H L 2I I2

L L H H3I I3

L H L L 4I I4

L H L H 5I I5

L H H L 6I I6

L H H H7I I7

74ALS1518-input MUX

S2

S1

S0

E

I0 I1 I2 I3 I4 I5 I6 I7

ZZ

Lec-01, Pg-03


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Telephone :

PABX : 9661920-73/4980



UNIVERSITY OF DHAKA


FAX: 880-2-8615583


Ref. No............................ Dated, the.

I f ti l t t S d L t APECE DU ( l d i b )

Quad Two-Input Multiplexer:

Fig.: 74157 multiplexer logic diagram, truth table and logic symbol.The 74157 is a very useful multiplexer IC that contains four two-input multiplexers. For each Z output to take on thelogic level of its corresponding I0 input

First of all, the enable input must be active; that is, 0=E . In order for Za to equal I0a, the select input must be LOW.

These same conditions will produce Zb=I0b, Zc=I0c and Zd=I0d.

With 0=E and S=1, the Z outputs will follow the set of I1 inputs; that is, Za=I1a, Zb=I1b, Zc=I1c and Zd=I1d.

All of the outputs will be disabled (LOW) when 1=E .[Ref.: Digital Systems Principles and Applications, R.J. Tocci and N.S. Widmer]

S

I1a I0a I1b I0b I1c I0c I1d I0d

Za Zb Zc Zd

E

74ALS157MUX

Za Zb Zc Zd

I1a I1b I1c I1d I0a I0b I0c I0d

S

E

E S Za Zb Zc Zd

H X L L L LL L I0a I0b I0c I0dL H I1a I1b I1c I1d

Lec 01 Pg 05

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