circular built-in self-test - auburn universitystrouce/datseminar/dixit05s.pdf · seminar 3/9/05 1...

VLSI Design & Test Seminar 3/9/05

1

Circular BuiltCircular Built--In SelfIn Self--TestTestChuck StroudChuck Stroud

Dept. of Electrical & Computer EngineeringDept. of Electrical & Computer EngineeringAuburn UniversityAuburn University

VLSI Design & Test Seminar 3/9/05 2

Outline of Presentation

Overview BILBOOverview BILBOProblems for Practical ApplicationsProblems for Practical Applications

Circular BIST TechniquesCircular BIST TechniquesCircular BISTCircular BISTCircular SelfCircular Self--Test PathTest PathSimultaneous SelfSimultaneous Self--TestTest

Problems with Circular BISTProblems with Circular BISTSolutionsSolutions


Simple BILBO Application

BuiltBuilt--In Logic Block ObserverIn Logic Block ObserverB. Koenemann, J. Mucha and G. Zwiehoff, ITC’79

Convert existing Convert existing FFsFFs to to BILBOsBILBOsOne BILBO acts as Test Pattern Generator (TPG)One BILBO acts as Test Pattern Generator (TPG)

Linear Feedback Shift Register (LFSR) generates test patternsLinear Feedback Shift Register (LFSR) generates test patternsOther BILBO acts as MultipleOther BILBO acts as Multiple--Input Signature Register (MISR)Input Signature Register (MISR)


Original BILBO Register

Add XOR, AND, and NOR Add XOR, AND, and NOR gates to each FFgates to each FFAdd MUX and XOR primitive Add MUX and XOR primitive polynomial feedback to polynomial feedback to registerregisterFour modes controlled by Four modes controlled by B1 and B2B1 and B2No TPG modeNo TPG mode

Extra gatesExtra gates


BILBO Test Sessions

Multiple test sessions requiredTest session Test session scheduling scheduling requiredrequiredRegister selfRegister self--adjacency adjacency must be must be avoidedavoided


My BILBO Questions

Why not run all Why not run all BILBOsBILBOs in MISR mode?in MISR mode?Let signatures be the next test patternsLet signatures be the next test patternsForget about register selfForget about register self--adjancyadjancy

Do we need to read every MISR at end of Do we need to read every MISR at end of BIST sequence?BIST sequence?

Let signatures propagate through chain to output Let signatures propagate through chain to output registerregister

Do we need polynomials for every register?Do we need polynomials for every register?Different polynomials for different size registersDifferent polynomials for different size registers


Circular BIST Design


Complete CBIST Design

I wanted a sequential logic BIST for systemI wanted a sequential logic BIST for system--levellevelFor systemFor system--level use we needlevel use we need

Input isolationInput isolationTest controllerTest controller

Not incorporated in:Not incorporated in:Circular SelfCircular Self--Test PathTest Path

CSTPCSTP

Simultaneous SelfSimultaneous Self--TestTestSSTSST


Circular BIST FFs

Circular SelfCircular Self--Test PathTest PathKrasniewskiKrasniewski & & PilarskiPilarski, 1987, 1987

Simultaneous SelfSimultaneous Self--TestTestBardellBardell, , McAnneyMcAnney & & SavirSavir, 1982, 1982

Circular BIST, Stroud, 1985Circular BIST, Stroud, 1985akaaka Modified BILBO, Hudson, 1987Modified BILBO, Hudson, 1987


Circular BIST

Selective replacement of Selective replacement of FFsFFs with CBIST with CBIST FFsFFsreduces area overhead and performance penaltyreduces area overhead and performance penalty

Only about 60% to 70% of Only about 60% to 70% of FFsFFs need to be replacedneed to be replaced

Fault coverage was 91% to 98% for my applicationsFault coverage was 91% to 98% for my applicationsI used partial scan mode for improving fault coverageI used partial scan mode for improving fault coverageKrasniewskiKrasniewski & & PilarskiPilarski claimed CSTP would get 100%claimed CSTP would get 100%

They ignored limit cyclingThey ignored limit cycling

Problems observed in my applications and by othersProblems observed in my applications and by othersRegister adjacencyRegister adjacencyLimit cyclingLimit cycling


Circular BIST Scan Mode

Used to augmentfault coverage formanufacturing testbut not used in mysystem applications


Problems with Circular BIST

Register adjacencyRegister adjacencySolution:Solution:

reorder chainreorder chain

Limit cyclingLimit cyclingSolutions:Solutions:

Apply partial scan Apply partial scan vectorsvectorsFind head stateFind head stateReRe--seed CBIST seed CBIST chain using partial chain using partial scan modescan modeAdd Add FFsFFs to circuits to circuits prone to limit cyclingprone to limit cycling


Who’s Afraid of the Big Bad Limit Cycle?

Circuits prone to limit cycling: Circuits prone to limit cycling: NNFF FF //CCinin < 2< 2where where NNFFFF = number of = number of FFsFFsand and CCinin = number of inputs to largest logic cone= number of inputs to largest logic cone

almostalmostalwaysalways

almostalmostnevernever

sometimessometimes

Modifying Multi-Mode Scan to handle hard-to-detect faults & X-states

Research Advisor: Adit SinghCommittee Members: V. Agrawal, C. E. Stroud

Dept. of ECE, Auburn University

Ayoush DixitDept. of ECE, Auburn University

3/9/2005 The VLSI Design & Test Seminar Series, Spring 2005

Outline• Introduction• Background

– Scan Design– BIST

• Scan Based BIST• Multi-Mode Scan• Circular BIST• Use of Multi-Mode Scan in Circular BIST• Problems with BIST

– Handling hard-to-detect faults– Handling X-states

• Conclusion• Q&A


Background

• Scan Design

• BIST


Classical Scan

Conceptual Schematic of Classical Scan


Classical Scan (contd....)

Normal Operation (C = 0)


Classical Scan (contd....)

Scan Shift Operation (C = 1)


Scan Based BIST

Limitation: Slow test-per-scan test execution




• Scan Based BIST

• Multi-Mode Scan• Circular BIST• Use of Multi-Mode Scan in Circular BIST• Problems with BIST


• Conclusion/Q&A


Multi-Mode Scan• Employs Circular BIST• Combines test generation/results compression in FFs

• Retains ALL benefits of scan based BIST• Fast test-per-clock operation• BIST controller not required (area saving)


Circular BIST

Basic Idea:• Scan in random states

as initial states• Run in test mode• Capture the response • EXOR the new circuit state

to get another random state vector


Circular BIST (contd....)

• Kraśniewski & Pilarski (1986)CSTP Cell

1Test

0System

CModes



• C. E. Stroud (1988)BIST Cell

BIST11

System01

Shift10

Init00

ModeB1B0



• Easy to automate this DFT method• High fault coverage (typically >

90%)• At-speed testing• Low area & performance penalties

– typically 10% to 20% additional logic

• Also known as Circular Self-Test Path (CSTP)




• Scan Based Logic BIST• Multi-Mode Scan• Circular BIST• Use of Multi-Mode Scan in Circular BIST• Problems with BIST




Multi-Mode Scan Memory Element


Multi-Mode Scan Memory Element (contd....)

Normal Operation / Scan Shift (C=0)


Multi-Mode Scan Memory Element (contd....)

Pseudorandom Self-Test (C=1)


Normal Operation / Scan Shift Mode

• Independent Scan Register• No switching activity in the scan chain if Scan-In is held steady.


Pseudorandom Self-Test Mode

• Scan/MISA Register provides state input• Next state vector is accumulated (modulo 2) in (shifted) Scan/MISA

Register


Problems With BIST

• Limit cycling• Register adjacency• X-states• Hard-to-detect faults (random pattern resistive

faults)


Limit Cycling


Register Adjacency

CSTP Our Approach


Hard-to-detect faults

Causes:• Reset and Start signals in the circuit

minimizes circuit fault coverage in pseudorandom test mode

• When circuits enter a loop degradation in fault coverage can be seen

• Required conditions for fault to be detected are never met or hardly met


Handling hard-to-detect faults

• Solutions:– Mixed mode approach (using LFSR and ROM)– Embedded Deterministic Test (on-chip deterministic

pattern generation)– Bit-Fixing– LFSR reseeding

• Approach used:– LFSR reseeding (similar effect can be achieved by

flipping test-mode bit randomly).– Bit-fixing of some of the bits in the test cubes to a fixed

logic depending on their effect on the system outputs.


29111048982901437902891394462881274342871223222861210982851198982841173822831982628229698

Cumulative Faults# of faultsVec #

Handling hard-to-detect faultsITC’99 circuit b09


Handling hard-to-detect faultsITC’99 circuit b09 (contd....)

________________________________________________Det@ PO Scan Chain--------------------------------------------------------------------------------104898 0 01001011010000011101000001111043790 0 11000001011111011000010000000139446 0 11001001111101001000010000010121098 0 1110001011010010010100100110119826 0 0100010011011110011010010101109698 0 110110111110000000101001010000--------------------------------------------------------------------------------27434 1 11100101101101001111001010011022322 1 01001111010001000111010110001019898 1 11011111000001100011010011000117382 1 010001011100000001100100000001


Handling hard-to-detect faultsITC’99 circuit b09 (contd....)

___________ ___________OUTPUT = 1 | OUTPUT = 0----------------- | -----------------1 => 2 times 0 => 2 times | 1 => 4 times 0 => 2 times I0-SO1 => 4 times 0 => 0 times | 1 => 6 times 0 => 0 times D-IN-REG-0-SO1 => 1 times 0 => 3 times | 1 => 1 times 0 => 5 times D-OUT-REG-7-SO1 => 1 times 0 => 3 times | 1 => 1 times 0 => 5 times D-OUT-REG-6-SO1 => 2 times 0 => 2 times | 1 => 3 times 0 => 3 times D-OUT-REG-5-SO1 => 4 times 0 => 0 times | 1 => 1 times 0 => 5 times D-OUT-REG-4-SO1 => 2 times 0 => 2 times | 1 => 3 times 0 => 3 times D-OUT-REG-3-SO1 => 4 times 0 => 0 times | 1 => 4 times 0 => 2 times D-OUT-REG-2-SO1 => 2 times 0 => 2 times | 1 => 4 times 0 => 2 times D-OUT-REG-1-SO1 => 2 times 0 => 2 times | 1 => 6 times 0 => 0 times D-OUT-REG-0-SO1 => 1 times 0 => 3 times | 1 => 3 times 0 => 3 times OLD-REG-7-SO1 => 1 times 0 => 3 times | 1 => 4 times 0 => 2 times OLD-REG-6-SO1 => 0 times 0 => 4 times | 1 => 2 times 0 => 4 times OLD-REG-5-SO1 => 3 times 0 => 1 times | 1 => 3 times 0 => 3 times OLD-REG-4-SO1 => 1 times 0 => 3 times | 1 => 2 times 0 => 4 times OLD-REG-3-SO1 => 0 times 0 => 4 times | 1 => 2 times 0 => 4 times OLD-REG-2-SO1 => 1 times 0 => 3 times | 1 => 3 times 0 => 3 times OLD-REG-1-SO1 => 3 times 0 => 1 times | 1 => 3 times 0 => 3 times OLD-REG-0-SO1 => 4 times 0 => 0 times | 1 => 2 times 0 => 4 times Y-REG-SO1 => 3 times 0 => 1 times | 1 => 2 times 0 => 4 times STATO-REG-1-SO1 => 0 times 0 => 4 times | 1 => 2 times 0 => 4 times STATO-REG-0-SO1 => 3 times 0 => 1 times | 1 => 2 times 0 => 4 times D-IN-REG-8-SO1 => 1 times 0 => 3 times | 1 => 1 times 0 => 5 times D-IN-REG-7-SO1 => 1 times 0 => 3 times | 1 => 2 times 0 => 4 times D-IN-REG-6-SO1 => 3 times 0 => 1 times | 1 => 0 times 0 => 6 times D-IN-REG-5-SO1 => 1 times 0 => 3 times | 1 => 4 times 0 => 2 times D-IN-REG-4-SO1 => 0 times 0 => 4 times | 1 => 2 times 0 => 4 times D-IN-REG-3-SO1 => 1 times 0 => 3 times | 1 => 3 times 0 => 3 times D-IN-REG-2-SO1 => 2 times 0 => 2 times | 1 => 3 times 0 => 3 times D-IN-REG-1-SO1 => 2 times 0 => 2 times | 1 => 3 times 0 => 3 times O0-SO


Handling hard-to-detect faults b09 (contd....)

________________________________________________Det@ PO Scan Chain--------------------------------------------------------------------------------104898 0 01001011010000011101000001111043790 0 11000001011111011000010000000139446 0 11001001111101001000010000010121098 0 1110001011010010010100100110119826 0 0100010011011110011010010101109698 0 110110111110000000101001010000--------------------------------------------------------------------------------27434 1 11100101101101001111001010011022322 1 01001111010001000111010110001019898 1 11011111000001100011010011000117382 1 010001011100000001100100000001


Handling hard-to-detect faults b09 (contd....)Detection of a fault before 9698th vector was @ 9218





– Handling hard-to-detect faults– Handling X-state problem



X-state problem• X-states are present in industrial circuits

– Un-initialized and uncontrollable sequential elements,– Bus contention,– Floating buses,– Interactions among multiple clock domains, and,– Modeling inaccuracies.

• Signature can be corrupted by signals whose logic values are not known during fault-free simulation, also called X’s


X-state problem (contd....)

x x x0 x 14

x x 00 x 13

0 1 x1 0 x2

1 0 01 0 01

MISR out1 2 3

Scan out1 2 3

Clock CycleInitial State of MISR = 000


Handling X-state problem• Solutions:

– Fixing X’s to 1 or 0 before compacting the response.– Post-processing the response data to determine whether the

CUT is defective.– Designing X-tolerant compaction hardware.

• First two solutions heavily depend on the tester and knowledge of the X’states.

• The third solution is ideal for BIST purposes as it is not dependent on external resources.

• Approach Used:– Fixing X’s to 0 before compacting the response.


Handling X-state problem (contd…)

Pseudorandom Self Test

11

X-state elimination & scan capture

01

Scan Capture01

Normal Op / Scan Shift

00

ModesC2C1


Final implementation


Scan Capture01Scan Capture01Scan Capture0101

Self test/ Force 0 or 1

11Self Test11Self Test1110

Self test11X-state Elimination & Scan capture

01Self Test1111

Normal Op / Scan Shift

00Normal Op / Scan Shift

00Normal Op / Scan Shift

0000

ModesC23C1

3ModesC22C1

2ModesC21C1

1C2C1

Control logic for the final implementation

C11 = C1 ٧ C2

C11 = C1

2= C13

C2 = C21=C2

3

C22 = Not(C1) ٨ C2


Some Results for ITC’99 Benchmark Circuits

---74.2297.08Avg.

98.432.4595.79b13

100.021.2296.44b12

99.291.8195.94b11

100.091.56100.00b10

100.087.33100.00b09

100.098.15100.00b08

99.958.2898.86b07

100.0093.71100.00b06

N/A33.4876.56b05

99.984.2498.48b04

100.0074.82100.00b03

100.0099.33100.00b02

100.0098.45100.00b01

Limited Scan Operations3 (%)

Random2

(%)FC1

(%)Circuit

1 Fault Coverage using MMSFF/MMSME2 Coverage using Pseudo random patterns (Corno et al. 2000)3 Coverage using Limited scan operations proposed by Cho et al. (2004)


Some Results for ITC’99 Circuits (contd…)

• F. Corno, M. S. Reorda and G. Squillero, RT-level ITC'99 benchmarks and first ATPG results, Design & Test of Computers, IEEE ,Volume: 17 , Issue: 3 , July-Sept. 2000 Pages:44 – 53

• Yonsang Cho, Irith Pomeranz and Sudhakar M. Reddy, Test Application Time Reduction for Scan Circuits Using Limited Scan Operations, Proceedings International Symposium on Quality Electronic Design, March, 2004.


Conclusion

• Better and comparable fault coverage than the different published results.

• Effective DFT method for sequential circuits with minimal implementation time.

• Complete BIST solution with minimal tester dependency.

• Most of the BIST problems taken care of.


Comments/Questions

?Comments and question can be emailed to

[email protected] / [email protected]

circular built-in self-test - auburn universitystrouce/datseminar/dixit05s.pdf · seminar 3/9/05 1...

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