introduction to ise & modelsim - auburn universitystrouce/class/elec4200/lab 0.pdf · elec 4200...
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ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Introduction
About this tutorial
This tutorial consists of an introduction to creating simplecircuits on an FPGA using a variety of methods. There are twoways to create the circuit: using Schematic Capture or by usingVHDL. You have to do both of these methods, one at a time.For the VHDL method, you can either add a pre-existing file orcreate a new file using the wizard. You only have to use one ofthese methods.
How to use this tutorial
This tutorial consists of several steps broken down overmultiple slides. Read each slide carefully and then press“Space”, scroll down or click the “Forward” arrow to advancethe slides. Also pay attention to things highlighted in green,these are usually important.
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Objectives
• In this Lab exercise, we will design a 2-to-1 multiplexer(MUX) using the following two types of design entry:
1 Schematic Capture using ISE (Xilinx Corp.)2 VHDL entry using any text editor
• After design entry (either schematic capture or VHDLentry), ModelSim (Mentor Graphic Corp.) will be used tosimulate and verify the design (with debugging performedas needed).
• After the design is fully verified, we will use ISE tosynthesize the design into a Spartan 3 FPGA configurationdata file which will then be downloaded onto a Spartan 3printed circuit board (PCB) where the implemented designwill be verified.
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Design Specifications
The 2-to-1 multiplexer has three inputs (two data inputs andone select input) and one data output.
• Data Inputs: Din0, Din1
• Select Input: Sel
• Data Output: Dout
• Logic Function:• when Sel=0, Dout=Din0• when Sel=1, Dout=Din1
• Boolean Logic Equation: Dout = Din0 * Sel + Din1 * Sel
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Basic Design Steps of this Lab
1 Create a new project using ISE Click here
2 Create circuit using one of the following:• Schematic capture using ISE Click here
• VHDL file Click here
3 Simulation using ModelSim Click here
4 Synthesize design to an FPGA Click here
5 Download and verify design Click here
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
New Project
Click the start menu, and type in Project. Then look for“64-bit Project Navigator” and click on it.
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
New Project
After ISE is launched, we will create a new project in File →New Project...
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
New Project
IMPORTANT
For lab sessions it is highly recommended that the projectdirectory be on a flash drive or the C: drive (and not your H:drive) to maximize performance during synthesis andsimulation. Furthermore there are known problems with usingthe H: drive. Backup your project to the H: drive if you mustafter you finish the lab.
Again
Should you fail to observe this, and use the H: drive to storeyour lab, and problems ensue, I will not be helpful. To behonest I will laugh at you.
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
New Project
Create a new project under the directory “C:\TEMP\” oranother directory of your choice, and give the project adescriptive name such as “Lab0 VHDL”. Also set the“Top-level source type:” to “HDL” if your are using VHDL or“Schematic” if you are using Schematic Capture. Click “Next”.
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
New Project
The Spartan 3 Starter Kit PCB board uses a Xilinx Spartan3XC3S200 FPGA chip which is packaged in a flat thin 256-pin(FT256) Ball Grid Array, so make the following changeshighlighted in green. Make sure you select “Modelsim-SEMixed” as well. Click “Next” when you’re done.
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
New Project
The next page displays a summary of the new project. Click“Finish” when you’re done to exit. Create circuit
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Read carefully
Choose one of the following
1 Schematic Capture Click here
2 VHDL Design Click here
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Schematic Capture in ISE
Now we create a blank sheet for schematic capture. First, clickProject → New Source...
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Schematic Capture in ISE
Click Schematic in the left frame and type in the name for yourschematic, for example “mux21”.
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Schematic Capture in ISE
This summary page is displayed and we can click “Finish”.
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Schematic Capture in ISE
Your file should be open by default. Click “Symbols” in therow of tabs, highlighted in green below, to begin placingcomponents.
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Schematic Capture in ISE
Here we have selected an “and2” gate and placed it neatly onthe sheet.
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Schematic Capture in ISE
A Helpful Suggestion
Being neat and placing your components with ample spacesurrounding them will save you a lot of trouble. It will makethings easy for the auto-router, which will make things easy foryou.
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Schematic Capture in ISE
Repeat the previous operations until all components are placedon the schematic. In this example, we will use two AND2s, oneOR2 and one INV.
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Schematic Capture in ISE
Select the add wire icon to begin connecting all componentswith wires.
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Schematic Capture in ISE
To connect two components with a wire, left click mouse onthe start point and then left click mouse on the destinationpoint. Note the “crosshairs”, and only click if you see them.
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Schematic Capture in ISE
A Helpful Hint
If you’ve placed the parts neatly with enough space betweencomponents, the autorouter should handle all connectionsneatly. You will still need to add atleast three wires manually,so don’t worry if the autorouter fails to work properly.
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Schematic Capture in ISE
Your circuit should end up looking like the circuit below
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Schematic Capture in ISE
You will still need to manually add three wires for your inputs.Just left click an input and then move the mouse to the leftand double-click. Do this for all three inputs.
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Schematic Capture in ISE
Select the add marker icon, then move the mouse over aninput/output look for the crosshairs and click. Do this for all 4inputs/outputs.
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Schematic Capture in ISE
Your circuit should look like below. Note the direction of themarker arrows.
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Schematic Capture in ISE
Change the names of the markers to something moredescriptive by double-clicking on them. You can also do this tothe internal connections, but this is not necessary. See nextslide for the names of the inputs and outputs.
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Schematic Capture in ISE
Make sure you use the following labels on the markers.
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Schematic Capture in ISE
Click the “Check Schematic” icon. If you were neat andcareful, it should pass. Save your work and proceed to“Simulation”. Otherwise fix every error and do not proceeduntil it passes. Onto Simulation
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
VHDL
Read very carefully
Choose ONE of the following methods to add the multiplexerVHDL file to your project.
1 Add a pre-existing file to the project Click here
2 Create a new file and edit it Click here
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Add an existing VHDL file
Open Notepad, enter the following VHDL code and save thefile as “mux.vhd”. Make sure that Notepad doesn’tautomatically add “.txt” to the end of it.
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Add an existing VHDL file
Click on Project → Add Copy of Source...This helps keeps things neat and in one place. “Add Copy ...”uses the file in its current location, which may be anywhere.
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Add an existing VHDL file
Look for your file and click “Open”. It should now be added tothe project. Onto Simulation
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Add an existing VHDL file
Click on Project → New Source...
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Add an existing VHDL file
Select VHDL module and give the file a name.
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Add an existing VHDL file
Add the port names and directions as shown.
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Add an existing VHDL file
Click “Finish” to exit the wizard.
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Add an existing VHDL file
Add the following line of code.Dout <= (Din0 and not Sel) or (Din1 and Sel);
Save the file and proceed to Simulation. Onto Simulation
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Design Verification with ModelSim
Choose “Simulation” mode in the “Design” tab, and select theyour file. Then expand “ModelSim Simulator” double-click“Simulate Behavioral Model”. Alternatively you can right-clickas shown and select run. Problems?
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Design Verification with ModelSim
The following ModelSim window should pop-up.
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Design Verification with ModelSim
We will force the inputs and observe the output. By comparingthem with the desired output we can verify that the circuit isworking properly. We will test all possible input combinations,and observe the output for each combination.
Important
This is called exhaustive testing and it is not practical for largercircuits, generally circuits with 6 or more inputs.
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Design Verification with ModelSim
• The basic force statement format is:force signal-name state-value time
• For example:force Din0 0 100, 1 200
means signal Din0 is forced to logic 0 at 100 time unitsand is forced to logic 1 at 200 time units.
• Enter the following commands in the console.
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Design Verification with ModelSim
• Now enter the commandrun 400
• This command runs the simulation for 400 time units, bydefault ns.
• Observe the output waveform and look for the expected“Dout” values for all possible inputs of “Din0”, “Din1”,and “Sel”.
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Design Verification with ModelSim
We can use the GUI to force signals by right clicking on thesignal name and select Force. Below is an explanation of thedialog that pops up. Note that this also prints the forcecommand in the console window.
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Design Verification with ModelSim
Clocking is useful for periodic signals, such as clocks. Rightclick on a signal and select clock. Below is the dialog withexplanations of the options. This also prints the command inthe console window.
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Design Verification with ModelSim
We can save console commands to a file and then tellModelSim to run the contents of the file. Save the following toa file called “mux.do”. Make sure Notepad does notautomatically add a “.txt” extension.
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Design Verification with ModelSim
Click Tools → Tcl → Execute Macro
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Design Verification with ModelSim
Look for your “mux.do” file and click “Open” to run it.
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Design Verification with ModelSim
WARNING
If you observe any incorrect results during simulation, go backand debug your circuit. Do not under any circumstancesproceed any further.
LEGAL AGREEMENT
I verify that I have simulated my circuit properly to the best ofmy knowledge, and in the event that problems ensue due toimproper simulation of my circuit, the GTA at his solediscretion may laugh at me and/or refuse to help me and mypartner I agree
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Synthesize Design
Select “Implementation” mode, then select the file to besynthesized and the double-click on “Synthesize”. You can alsoright-click on “Synthesize” and select Run.
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Synthesize Design
We need a constraints file to ensure that inputs and outputs goto the desired pins.
Final Warning
If you have stored your project on the H: drive, this step willfail every time. Make sure your project is not stored on the H:drive.
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Synthesize Design
Select Project → New Source...
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Synthesize Design
Click “Implementation Constraints File” in the left frame andtype in the name for the constraints file, for example “mux21”.Then click “Next” and “Finish”.
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Synthesize Design
Double click on the “I/O Pin Planning (PlanAhead) -Post-Synthesis” under “Under Constraints” to launchPlanAhead. For future reference you can just skip the previoustwo step and ISE will automatically offer to add a constraintsfile to the project.
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Synthesize Design
Click on Din0, enter F12 as the pin and click “Apply” to makethe changes permanent.
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Synthesize Design
Make sure you constrain all inputs and outputs as shownbelow, highlighted in green. Make sure to save yourconstraints, and then exit PlanAhead.
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Synthesize Design
Now double-click on “Implement Design” to use yourconstraints. Download to FPGA
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Download and Verify Design
Connect the 5V DC power cable to the power input on thedemo board (J4).
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Download and Verify Design
A Helpful Hint
If you see a series of numbers and flashing lights, don’t fret.This is just a test configuration stored in the flash memory onthe PCB and you can manipulate the various switches andbuttons to see what happens.
Another Helpful Hint
You can zoom in and out with F7 and F8 to make it easier toplace the components.
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Download and Verify Design
Connect the download cable between the PC parallel port andthe demo board (J7). Carefully note the position of the labelon the cable.
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Download and Verify Design
Double-click on “Generate Programming File”.
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Download and Verify Design
Double-click on “Configure Target Device”.
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Download and Verify Design
Click “OK” on the dialog box that pops up.
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Download and Verify Design
Double-click on “Boundary Scan”.
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Download and Verify Design
Click on the “Initialize Chain” button. You will learn moreabout Boundary Scan later on in ELEC 4200.
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Download and Verify Design
Click on “Yes” to assign the Programming File you previouslygenerated to the FPGA.
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Download and Verify Design
Find the Programming File, it should have a “.bit” extension,and click open.
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Download and Verify Design
Click “Bypass” on the next dialog box.
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Download and Verify Design
Click “OK” on the next page.
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Download and Verify Design
Double-click “Program” on the left hand side and look for thewords “Program Succeeded” to appear on the bottom. If itfails, try again. If it fails more than three times, call the GTA.
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Download and Verify Design
That’s it, you’re done. Play around with the circuit and see if itworks. If it does call the GTA and show it. If it doesn’t, try andfigure out what’s wrong if it doesn’t work as expected. Whenyou’re done, close iMPACT and click “No” on the dialog box.
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Common Problems
Click Here
Click Here
Click Here
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Libraries not compiled
The above is a harmless dialog box that may pop up, click“No” and go on your merry way. Return
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
ModelSim not found
The above means that ISE can’t find Modelsim, so you have totell it where it is.
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
ModelSim not found
Go to Edit → Preferences
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
ModelSim not found
Enter the location highlighted in green in the “IntegratedTools” menu, or use the “...” to find Modelsim graphically.
Return
ELEC 4200Lab 0
ELEC 4200
Introduction
Overview
Objectives
DesignSpecifications
Basic DesignSteps
New Project
Design Entry
Choose one
SchematicCapture
VHDL
Verification
Download &Verify
Synthesis
Download
Problems
Libraries notcompiled
Modelsim notfound
Modelsimassociations
Modelsim associations
ModelSim wants to associatiate itself with “.vhdl” files. I’drecommend you click “No”. Return