CHNG

CHNG 2: KHO ST LINH KIN

chu k thc thi lnh ny ch c dng c lnh u tin ti label SUB_1. Nh vy c th xem lnh 3 cn 2 chu k xung clock thc thi.

TCY5: thc thi lnh u tin ca SUB_1 v c lnh tip theo ca SUB_1.

Qu trnh ny c thc hin tng t cho cc lnh tip theo ca chng trnh.

Thng thng, thc thi mt lnh, ta cn mt chu k lnh gi lnh , v mt chu k xung clock na gii m v thc thi lnh. Vi c ch pipelining c trnh by trn, mi lnh xem nh ch c thc thi trong mt chu k lnh. i vi cc lnh m qu trnh thc thi n lm thay i gi tr thanh ghi PC (Program Counter) cn hai chu k lnh thc thi v phi thc hin vic gi lnh a ch thanh ghi PC ch ti. Sau khi xc nh ng v tr lnh trong thanh ghi PC, mi lnh ch cn mt chu k lnh thc thi xong.

2.1.6 CC DNG PIC V CCH LA CHON PIC

* Cc k hiu ca vi iu khin PIC - PIC12xxxx: di lnh 12 bit - PIC16xxxx: di lnh 14 bit - PIC18xxxx: di lnh 16 bit

- C: PIC c b nh EPROM (ch c 16C84 l EEPROM)

- F: PIC c b nh flash

- LF: PIC c b nh flash hot ng in p thp LV: tng t nh LF, y l k hiu c.

Bn cnh mt s vi iu khin c k hiu xxFxxx l EEPROM, nu c thm ch A cui l flash (v d PIC16F877 l EEPROM, cn PIC16F877A l flash).Ngoi ra cn c thm mt dng vi iu khin PIC mi l dsPIC. Vit Nam ph bin nht l cc h vi iu khin PIC do hng Microchip sn xut.

*Cch la chn PIC

Trc ht cn ch n s chn ca vi iu khin cn thit cho ng dng. C nhiu vi iu khin PIC vi s lng chn khc nhau, thm ch c vi iu khin ch c 8 chn, ngoi ra cn c cc vi iu khin 28, 40, 44 chn.

Cn chn vi iu khin PIC c b nh flash c th np xa chng trnh c nhiu ln hn. Tip theo cn ch n cc khi chc nng c tch hp sn trong vi iu khin, cc chun giao tip bn trong. Sau cng cn ch n b nh chng trnh m vi iu khin cho php. Ngoi ra mi thng tin v cch la chn vi iu khin PIC c th c tm thy trong cun sch Select PIC guide do nh sn xut Microchip cung cp.

2.1.7 NGN NG LP TRNH PIC

Ngn ng lp trnh cho PIC rt a dng. Ngn ng lp trnh cp thp c MPLAB (c cung cp min ph bi nh sn xut Microchip), cc ngn ng lp trnh cp cao hn bao gm C, Basic, Pascal, Ngoi ra cn c mt s ngn ng lp trnh c pht trin dnh ring cho PIC nh PICBasic, MikroBasic

2.1.8 PIC16F877A

2.1.8.1 HINH DANG VA S CHN

Hnh 2.2: Vi iu khin PIC16F877A/PIC16F874A v cc dng s chn

2.1.8.2 MT VI THNG S V PIC 16F877A

y l vi iu khin thuc h PIC16Fxxx vi tp lnh gm 35 lnh c di 14 bit. Mi lnh u c thc thi trong mt chu k xung clock. Tc hot ng ti a cho php l 20 MHz vi mt chu k lnh l 200ns. B nh chng trnh 8Kx14 bit, b nh d liu 368 byte RAM v b nh d liu EEPROM vi dung lng 256 byte. S PORT I/O l 5 vi 33 pin I/O.

Cc c tnh ngoi vi bao gm cc khi chc nng sau:

- Timer0: b m 8 bit vi b chia tn s 8 bit.

- Timer1: b m 16 bit vi b chia tn s, c th thc hin chc nng m da vo xung clock ngoi vi ngay khi vi iu khin hot ng ch sleep.

- Timer2: b m 8 bit vi b chia tn s, b postcaler.

- Hai b Capture/so snh/iu ch rng xung.

- Cc chun giao tip ni tip SSP (Synchronous Serial Port), SPI v I2C.

- Chun giao tip ni tip USART vi 9 bit a ch.

- Cng giao tip song song PSP (Parallel Slave Port) vi cc chn iu khin RD, WR, CS bn ngoi.

Cc c tnh Analog: - 8 knh chuyn i ADC 10 bit. - Hai b so snh.

Bn cnh l mt vi c tnh khc ca vi iu khin nh:

- B nh flash vi kh nng ghi xa c 100.000 ln.

- B nh EEPROM vi kh nng ghi xa c 1.000.000 ln.

- D liu b nh EEPROM c th lu tr trn 40 nm.

- Kh nng t np chng trnh vi s iu khin ca phn mm.

- Np c chng trnh ngay trn mch in ICSP (In Circuit Serial Programming)

thng qua 2 chn.

- Watchdog Timer vi b dao ng trong.

- Chc nng bo mt m chng trnh.

- Ch Sleep.

- C th hot ng vi nhiu dng Oscillator khc nhau.

2.1.8.3 S KHI CUA PIC16F877A

Hnh 2.3: S khi vi iu khin PIC16F877A.

2.1.8.4 T CHC B NH

Cu trc b nh ca vi iu khin PIC16F877A bao gm b nh chng trnh (Program

memory) v b nh d liu (Data Memory).

* B nh chng trnh

B nh chng trnh ca vi iu khin PIC16F877A l b nh flash, dung lng b nh 8K word (1 word = 14 bit) v c phn thnh nhiu trang (t page0 n page 3) . Nh vy b nh chng trnh c kh nng cha c 8*1024 = 8192 lnh (v mt lnh sau khi m ha s c dung lng 1 word (14 bit).

Khi vi iu khin c reset, b m chng trnh s ch n a ch 0000h (Reset vector). Khi c ngt xy ra, b m chng trnh s ch n a ch 0004h (Interrupt vector). B nh chng trnh khng bao gm b nh stack v khng c a ch ha bi

b m chng trnh.

* B nh d liu

B nh d liu ca PIC l b nh EEPROM c chia ra lm nhiu bank. i vi PIC16F877A b nh d liu c chia ra lm 4 bank. Mi bank c dung lng 128 byte, bao gm cc thanh ghi c chc nng c bit SFG (Special Function Register) nm cc vng a ch thp v cc thanh ghi mc ch chung GPR (General Purpose Register) nm vng a ch cn li trong bank. Cc thanh ghi SFR thng xuyn c s dng (v d nh thanh ghi STATUS) s c t tt c cc bank ca b nh d liu gip thun tin trong qu trnh truy xut v lm gim bt lnh ca chng trnh. S c th ca b nh d liu PIC16F877A nh sau:

Hinh 2.4: S b nh d liu cua PIC16F877A** THANH GHI CHC NNG C BIT SFR:

y l cc thanh ghi c s dng bi CPU hoc c dng thit lp v iu khin cc khi chc nng c tch hp bn trong vi iu khin. C th phn thanh ghi SFR lm hai lai: thanh ghi SFR lin quan n cc chc nng bn trong (CPU) v thanh ghi SRF dng thit lp v iu khin cc khi chc nng bn ngoi (v d nh ADC, PWM ).

Thanh ghi STATUS (03h, 83h, 103h, 183h):thanh ghi cha kt qu thc hin php ton ca khi ALU, trng thi reset v cc bit chn bank cn truy xut trong b nh d liu.

Thanh ghi OPTION_REG (81h, 181h): thanh ghi ny cho php c v ghi, cho php iu khin chc nng pull-up ca cc chn trong PORTB, xc lp cc tham s v xung tc ng, cnh tc ng ca ngt ngoi vi v b m Timer0.

Thanh ghi INTCON (0Bh, 8Bh,10Bh, 18Bh):thanh ghi cho php c v ghi, cha cc bit iu khin v cc bit c hiu khi timer0 b trn, ngt ngoi vi RB0/INT v ngt interrputon- change ti cc chn ca PORTB.

Thanh ghi PIE1 (8Ch): cha cc bit iu khin chi tit cc ngt ca cc khi chc nng ngoi vi.

Thanh ghi PIR1 (0Ch) cha c ngt ca cc khi chc nng ngoi vi, cc ngt ny c cho php bi cc bit iu khin cha trong thanh ghi PIE1.

Thanh ghi PIE2 (8Dh): cha cc bit iu khin cc ngt ca cc khi chc nng CCP2, SSP bus, ngt ca b so snh v ngt ghi vo b nh EEPROM.

Thanh ghi PIR2 (0Dh): cha cc c ngt ca cc khi chc nng ngoi vi, cc ngt ny c cho php bi cc bit iu khin cha trong thanh ghi PIE2.

Thanh ghi PCON (8Eh): cha cc c hiu cho bit trng thi cc ch reset ca vi iu khin.

** THANH GHI MC CH CHUNG GPR:

Cc thanh ghi ny c th c truy xut trc tip hoc gin tip thng qua thanh ghi FSG (File Select Register). y l cc thanh ghi d liu thng thng, ngi s dng c th ty theo mc ch chng trnh m c th dng cc thanh ghi ny cha cc bin s, hng s, kt qu hoc cc tham s phc v cho chng trnh.

* Stack

Stack khng nm trong b nh chng trnh hay b nh d liu m l mt vng nh c bit khng cho php c hay ghi.

Khi lnh CALL c thc hin hay khi mt ngt xy ra lm chng trnh b r nhnh, gi tr ca b m chng trnh PC t ng c vi iu khin ct vo trong stack. Khi mt trong cc lnh RETURN, RETLW hat RETFIE c thc thi, gi tr PC s t ng c ly ra t trong stack, vi iu khin s thc hin tip chng trnh theo ng qui trnh nh trc.

B nh Stack trong vi iu khin PIC h 16F877A c kh nng cha c 8 a ch v hot ng theo c ch xoay vng. Ngha l gi tr ct vo b nh Stack ln th 9 s ghi ln gi tr ct vo Stack ln u tin v gi tr ct vo b nh Stack ln th 10 s ghi ln gi tr ct vo Stack ln th 2.

Cn ch l khng c c hiu no cho bit trng thi stack, do ta khng bit c khi no stack trn. Bn cnh tp lnh ca vi iu khin dng PIC cng khng c lnh POP hay PUSH, cc thao tc vi b nh stack s hon ton c iu khin bi CPU.

2.1.8.5 CAC CNG XUT NHP CUA PIC16F877A

Cng xut nhp (I/O port) chnh l phng tin m vi iu khin dng tng tc vi th gii bn ngoi. Bn cnh , do vi iu khin c tch hp sn bn trong cc c tnh giao tip ngoi vi nn bn cnh chc nng l cng xut nhp thng thng, mt s chn xut nhp cn c thm cc chc nng khc th hin s tc ng ca cc c tnh ngoi vi nu trn i vi th gii bn ngoi.

Vi iu khin PIC16F877A c 5 cng xut nhp, bao gm PORTA, PORTB, PORTC, PORTD v PORTE.

*PORT A:

PORTA (RPA) bao gm 6 I/O pin. y l cc chn hai chiu (bidirectional pin), ngha l c th xut v nhp c. Chc nng I/O ny c iu khin bi thanh ghi TRISA (a ch 85h). Mun xc lp chc nng ca mt chn trong PORTA l input, ta set bit iu khin tng ng vi chn trong thanh ghi TRISA v ngc li, mun xc lp chc nng ca mt chn trong PORTA l output, ta clear bit iu khin tng ng vi chn trong thanh ghi TRISA. Thao tc ny hon ton tng t i vi cc PORT v cc thanh ghi iu khin tng ng TRIS (i vi PORTA l TRISA, i vi PORTB l TRISB, i vi PORTC l TRISC, i vi PORTD l TRISD vi vi PORTE l TRISE). Bn cnh PORTA cn l ng ra ca b ADC, b so snh, ng vo analog ng vo xung clock ca Timer0 v ng vo ca b giao tip MSSP (Master Synchronous Serial Port).

Cc thanh ghi SFR lin quan n PORTA bao gm:

- PORTA (a ch 05h) : cha gi tr cc pin trong PORTA.

- TRISA (a ch 85h) : iu khin xut nhp.

- CMCON (a ch 9Ch) : thanh ghi iu khin b so snh.

- CVRCON (a ch 9Dh) : thanh ghi iu khin b so snh in p.

- ADCON1 (a ch 9Fh) : thanh ghi iu khin b ADC.

* PORT B:

PORTB (RPB) gm 8 pin I/O. Thanh ghi iu khin xut nhp tng ng l TRISB. Bn cnh mt s chn ca PORTB cn c s dng trong qu trnh np chng trnh cho vi iu khin vi cc ch np khc nhau. PORTB cn lin quan n ngt ngoi vi v b Timer0. PORTB cn c tch hp chc nng in tr ko ln c iu khin bi chng trnh.

Cc thanh ghi SFR lin quan n PORTB bao gm:

- PORTB (a ch 06h,106h) : cha gi tr cc pin trong PORTB

- TRISB (a ch 86h,186h) : iu khin xut nhp

- OPTION_REG (a ch 81h,181h) : iu khin ngt ngoi vi v b Timer0.

* PORT C:

PORTC (RPC) gm 8 pin I/O. Thanh ghi iu khin xut nhp tng ng l TRISC. Bn cnh PORTC cn cha cc chn chc nng ca b so snh, b Timer1, b PWM v cc chun giao tip ni tip I2C, SPI, SSP, USART.

Cc thanh ghi iu khin lin quan n PORTC:

- PORTC (a ch 07h) : cha gi tr cc pin trong PORTC

- TRISC (a ch 87h) : iu khin xut nhp.

* PORT D:

PORTD (RPD) gm 8 chn I/O, thanh ghi iu khin xut nhp tng ng l TRISD. PORTD cn l cng xut d liu ca chun giao tip PSP (Parallel Slave Port).

Cc thanh ghi lin quan n PORTD bao gm:

- Thanh ghi PORTD : cha gi tr cc pin trong PORTD.

- Thanh ghi TRISD : iu khin xut nhp.

* PORT E:

PORTE (RPE) gm 3 chn I/O. Thanh ghi iu khin xut nhp tng ng l TRISE. Cc chn ca PORTE c ng vo analog. Bn cnh PORTE cn l cc chn iu khin ca chun giao tip PSP.

Cc thanh ghi lin quan n PORTE bao gm:

- PORTE : cha gi tr cc chn trong PORTE.

- TRISE : iu khin xut nhp v xc lp cc thng s cho chun giao tip PSP.

- ADCON1 : thanh ghi iu khin khi ADC.

2.1.8.6 TIMER 0

y l mt trong ba b m hoc b nh thi ca vi iu khin PIC16F877A. Timer0 l b m 8 bit c kt ni vi b chia tn s (prescaler) 8 bit. Cu trc ca Timer0 cho php ta la chn xung clock tc ng v cnh tch cc ca xung clock. Ngt Timer0 s xut hin khi Timer0 b trn.

Hinh 2.5: S khi ca timer 0

Mun Timer0 hot ng ch Timer ta clear bit TOSC (OPTION_REG), khi gi tr thanh ghi TMR0 s tng theo tng chu k xung ng h (tn s vo Timer0 bng

tn s oscillator). Khi gi tr thanh ghi TMR0 t FFh tr v 00h, ngt Timer0 s xut hin. Thanh ghi TMR0 cho php ghi v xa c gip ta n nh thi im ngt Timer0 xut hin mt cch linh ng. Mun Timer0 hot ng ch counter ta set bit TOSC (OPTION_REG). Khi xung tc ng ln b m c ly t chn RA4/TOCK1. Bit TOSE (OPTION_REG) cho php la chn cnh tc ng vo bt m. Cnh tc ng s l cnh ln nu TOSE=0 v cnh tc ng s l cnh xung nu TOSE=1. Khi thanh ghi TMR0 b trn, bit TMR0IF (INTCON) s c set. y chnh l c ngt ca Timer0. C ngt ny phi c xa bng chng trnh trc khi b m bt u thc hin li qu trnh m. Ngt Timer0 khng th nh thc vi iu khin t ch sleep.

Cc lnh tc ng ln gi tr thanh ghi TMR0 s xa ch hot ng ca prescaler.

Khi i tng tc ng l Timer0, tc ng ln gi tr thanh ghi TMR0 s xa prescaler nhng khng lm thay i i tng tc ng ca prescaler. Khi i tng tc ng l WDT, lnh CLRWDT s xa prescaler, ng thi prescaler s ngng tc v h tr cho WDT.

Cc thanh ghi iu khin lin quan n Timer0 bao gm:

- TMR0 (a ch 01h, 101h) : cha gi tr m ca Timer0.

- INTCON (a ch 0Bh, 8Bh, 10Bh, 18Bh): cho php ngt hot ng (GIE v PEIE).

- OPTION_REG (a ch 81h, 181h): iu khin prescaler.

2.1.8.7 TIMER 1

Timer1 l b nh thi 16 bit, gi tr ca Timer1 s c lu trong hai thanh ghi (TMR1H:TMR1L). C ngt ca Timer1 l bit TMR1IF (PIR1). Bit iu khin ca Timer1 s l TMR1IE (PIE). Tng t nh Timer0, Timer1 cng c hai ch hot ng: ch nh thi (timer) vi xung kch l xung clock ca oscillator (tn s ca timer bng tn s ca oscillator) v ch m (counter) vi xung kch l xung phn nh cc s kin cn m ly t bn ngoi thng qua chn RC0/T1OSO/T1CKI (cnh tc ng l cnh ln). Vic la chn xung tc ng (tng ng vi vic la chn ch hot ng l timer hay counter) c iu khin bi bit TMR1CS (T1CON). Sau y l s khi ca Timer1:

Hinh 2.6: S khi cua Timer1

Cc thanh ghi lin quan n Timer1 bao gm:

- INTCON (a ch 0Bh, 8Bh, 10Bh, 18Bh): cho php ngt hot ng (GIE v PEIE).

- PIR1 (a ch 0Ch): cha c ngt Timer1 (TMR1IF).

- PIE1( a ch 8Ch): cho php ngt Timer1 (TMR1IE).

- TMR1L (a ch 0Eh): cha gi tr 8 bit thp ca b m Timer1.

- TMR1H (a ch 0Eh): cha gi tr 8 bit cao ca b m Timer1.

- T1CON (a ch 10h): xc lp cc thng s cho Timer1.

2.1.8.8 TIMER 2

Timer2 l b nh thi 8 bit v c h tr bi hai b chia tn s prescaler v postscaler. Thanh ghi cha gi tr m ca Timer2 l TMR2. Bit cho php ngt Timer2 tc ng l TMR2ON (T2CON). C ngt ca Timer2 l bit TMR2IF (PIR1). Xung ng vo (tn s bng tn s oscillator) c a qua b chia tn s prescaler 4 bit (vi cc t s chia tn s l 1:1, 1:4 hoc 1:16 v c iu khin bi cc bit T2CKPS1:T2CKPS0 (T2CON)).

Hinh 2.7: S khi ca Timer 2

Ngoi ra ng ra ca Timer2 cn c kt ni vi khi SSP, do Timer2 cn ng vai tr to ra xung clock ng b cho khi giao tip SSP.

Cc thanh ghi lin quan n Timer2 bao gm:

- INTCON (a ch 0Bh, 8Bh, 10Bh, 18Bh): cho php ton b cc ngt (GIE v PEIE).

- PIR1 (a ch 0Ch): cha c ngt Timer2 (TMR2IF).

- PIE1 (a ch 8Ch): cha bit iu khin Timer2 (TMR2IE).

- TMR2 (a ch 11h): cha gi tr m ca Timer2.

- T2CON (a ch 12h): xc lp cc thng s cho Timer2.

- PR2 (a ch 92h): thanh ghi h tr cho Timer2.

Timer0 v Timer2 l b m 8 bit (gi tr m ti a l FFh), trong khi Timer1 l b m 16 bit (gi tr m ti a l FFFFh). Timer0, Timer1 v Timer2 u c hai ch hot ng l timer v counter. Xung clock c tn s bng tn s ca oscillator. Xung tc ng ln Timer0 c h tr bi prescaler v c th c thit lp nhiu ch khc nhau (tn s tc ng, cnh tc ng) trong khi cc thng s ca xung tc ng ln Timer1 l c nh. Timer2 c h tr bi hai b chia tn s prescaler v postcaler c lp, tuy nhin cnh tc ng vn c c nh l cnh ln. Timer1 c quan h vi khi CCP, trong khi Timer2 c kt ni vi khi SSP.

2.1.8.9 ADC

ADC (Analog to Digital Converter) l b chuyn i tn hiu gia hai dng tng t v s. PIC16F877A c 8 ng vo analog (RA4:RA0 v RE2:RE0). Hiu in th chun VREF c th c la chn l VDD, VSS hay hiu in th chun c xc lp trn hai chn RA2 v RA3. Kt qu chuyn i t tn tiu tng t sang tn hiu s l 10 bit s tng ng v c lu trong hai thanh ghi ADRESH:ADRESL.

Cc thanh ghi lin quan n b chuyn i ADC bao gm:

- INTCON (a ch 0Bh, 8Bh, 10Bh, 18Bh): cho php cc ngt (cc bit GIE, PEIE).

- PIR1 (a ch 0Ch): cha c ngt AD (bit ADIF).

- PIE1 (a ch 8Ch): cha bit iu khin AD (ADIE).

- ADRESH (a ch 1Eh) v ADRESL (a ch 9Eh): cc thanh ghi cha kt qu chuyn i AD.

- ADCON0 (a ch 1Fh) v ADCON1 (a ch 9Fh): xc lp cc thng s cho b chuyn i AD.

- PORTA (a ch 05h) v TRISA (a ch 85h): lin quan n cc ng vo analog PORTA.

- PORTE (a ch 09h) v TRISE (a ch 89h): lin quan n cc ng vo analog PORTE.

2.1.8.10 GIAO TIP NI TIP

USART (Universal Synchronous Asynchronous Receiver Transmitter) l mt trong hai chun giao tip ni tip.USART cn c gi l giao din giao tip ni tip SCI

(Serial Communication Interface). C th s dng giao din ny cho cc giao tip vi cc

thit b ngoi vi, vi cc vi iu khin khc hay vi my tnh. Cc dng ca giao din USART ngoi vi bao gm:

- Bt ng b (Asynchronous).

- ng b_ Master mode.

- ng b_ Slave mode.

PIC16F877A c tch hp sn b to tc baud BRG (Baud Rate Genetator) 8 bit dng cho giao din USART. BRG thc cht l mt b m c th c s dng cho c hai dng ng b v bt ng b v c iu khin bi thanh ghi PSBRG. dng bt ng b, BRG cn c iu khin bi bit BRGH ( TXSTA). dng ng b tc ng ca bit BRGH c b qua. Tc baud do BRG to ra c tnh theo cng thc sau:

Trong X l gi tr ca thanh ghi RSBRG ( X l s nguyn v 0