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Nuclear Instruments and Methods in Physics Research A 516 (2004) 327–347

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doi:10.1016

CHICSi—a compact ultra-high vacuum compatibledetector system for nuclear reaction experiments at storage

rings. III. readout system

L. Carl!ena, G. F^rreb, P. Golubeva, B. Jakobssona,*, A. Kolozhvarid,P. Marciniewskid, A. Siweka,c, E.J. van Veldhuizend, L. Westerbergd,

H.J. Whitlowa,e, J.M. Østbyb

aDepartment of Physics, Lund University, Box 118, Lund SE-221 00, SwedenbSINTEF Electronics and Cybernetics, Forskningsveien 1, Oslo N-0314, Norway

cHenryk Niewodnicza !nski Institute of Nuclear Physics, Cracow PL-31-342, PolanddThe Svedberg Laboratory, Uppsala University, Box 533, Uppsala SE-751 21, SwedeneSchool of Technology and Society, Malm .o University, Malm .o SE-205 06, Sweden

CHIC Collaboration

Received 5 June 2003; received in revised form 22 August 2003; accepted 27 August 2003

Abstract

(CHICSi) Celsius Heavy Ion Collaboration Si detector system is a high granularity, modular detector telescope array

for operation around the cluster-jet target/circulating beam intersection of the CELSIUS storage ring at the The. Svedberg

Laboratory in Uppsala, Sweden. It is able to provide identity and momentum vector of up to 100 charged particles and

fragments from proton–nucleus and nucleus–nucleus collisions at intermediate energies, 50–1000A MeV: All detector

telescopes as well as the major part of electronic readout system are placed inside the target chamber in ultra-high vacuum

(UHV, 10�9–10�7 Pa). This requires Very Large Scale Integrated (VLSI) microchip for the spectroscopic signal processing

and the generation and transport of digital control signals. Eighteen telescopes, read out with chip-on-board technique by

ceramics Mother Boards (MB) and corresponding 18 microchips are mounted on a 450� 45 mm2 Grand Mother Board

(GMB), processed on FR4 glass-fibre material. Each of these 28 GMB units contains a daisy-chain organisation of the

VLSI chips and associated protection circuits. Analogue-to-digital conversion of the spectroscopic signals is performed on

a board outside the chamber which is connected on one side to a power distribution board, directly attached to a UHV

mounting flange, and on the other side to the VME-based data acquisition system (CHICSiDAQ). This in its turn is

connected via a fibre-optic link to the general TSL acquisition system (SVEDAQ), and in this way data from auxiliary

detector systems, read out in CAMAC mode, can be stored in coincidence with CHICSi data.

r 2003 Elsevier B.V. All rights reserved.

PACS: 29.40.Wk; 25.70.Pq

Keywords: Multi-detector system; Ultra-high vacuum compatibility; VLSI electronics

onding author. Tel.: +46-46-222-7708.

ddresses: [email protected] (B. Jakobsson).

- see front matter r 2003 Elsevier B.V. All rights reserved.

/j.nima.2003.08.161

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L. Carl!en et al. / Nuclear Instruments and Methods in Physics Research A 516 (2004) 327–347328

1. Introduction

Collecting event-by-event data from nucleus–nucleus collisions is a unique tool for the study offormation and decay of highly excited nuclearmatter. In order to collect such data set a detectorsystem that registers as many as possible of theemitted fragments and particles is required. TheCHICSi detector, for experiments at storage rings,is constructed for this purpose. This requires thatit covers as large solid angle as the internal targetsystem allows and as large momentum-space asmodern detector technique allows. Furthermore,the granularity must be sufficiently high to allowhigh efficiency for registering all products incollisions where up to 100 charged particles andfragments are emitted.

CHICSi must be UHV compatible since it is aninternal detector system. The sensors—ion im-planted Si and GSO/PD (Gd2SiO5 scintillatingcrystal/photodiode) detectors—are chosen partlybecause of this requirement. The VLSI readoutchips and the GMB, which contain all electronicsup to the point where analogue-to-digital conver-sion of spectroscopic signals appears, are alsoplaced inside the target chamber and thereforeconnected to the UHV system of the acceleratorwhile the remaining parts of the electronics and theCHICSiDAQ and SVEDAQ acquisition systemsare external.

Electronics and data acquisition are described indetail in this paper while the general structure ofthe detector system and its mechanics as well asdetails about detectors have been discussed inprevious papers [1,2]. In Ref. [1] a more detailedmotivation for the physics program with theCHICSi detector is also presented.

2. Overview of the readout system

2.1. Specifications and requirements

The basic requirement for the readout system isthat it must be capable of simultaneous registra-tion of all charged particles and fragments,ranging from 2 to 100, from a single collision.The maximum rate of valid events is estimated to

be at most a few hundred per second. However,the singles rate registered by an individualtelescope is anticipated to approach a few times104 per second.

An overall view of the CHICSi readout system isshown in Fig. 1. This system should provide anefficient filtering of uninteresting signals withoutloss of physically relevant information. This isachieved in the way shown schematically in Fig. 2.When a signal exceeding the noise threshold occursin the second detector of any telescope, a fast ‘‘hit’’trigger signal is generated. This signal serves bothas an indication that a hit has been registered andas a time reference for initiating subsequentreadout and synchronisation with signals fromthe auxiliary detector systems [1,3,4] or from anyother external detectors in an experiment withCHICSi as central unit. The chip also generatesanother fast trigger signal if certain conditions thatidentify an intermediate-mass fragment (IMF,with mass number 3pAp20) or a light particleare satisfied. The high-level trigger processing fromgroups of chips is carried on outside the vacuumchamber where conventional NIM electronicsnormally is used and this allows signals also fromthe external detectors to be included in the triggerdecision.

If the trigger is valid, a signal entitled ‘‘T1’’ isgenerated 1 ms after the start of the hit signal toinitiate storage of signals from the analogueshaper. Subsequently, if the event is accepted asvalid, the digital trigger pattern and analoguesignals from all the chips on the readout chain maybe read out via the bus to an analogue to digitalconverter for registration. If the event is not validthe data can be simultaneously discarded onreceipt of a master reset.

The need to read out up to 1800 detectorsarranged in 500–600 telescopes, makes conven-tional approaches with standard modular electro-nics and individual vacuum lead-through for eachdetector impossible. It was therefore decided toadopt the approach where each detector telescopeis read out by an individual Application SpecifiedIntegrated Circuit (ASIC) VLSI microchip that ismounted in vacuum. This chip performs all theanalogue and digital signal handling for readout ofone detector telescope to serial analogue and

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Fig. 2. Schematic of the event triggering electronics in CHICSi experiments.

Fig. 1. Overview of the CHICSi detector telescope readout system. Details of the internal (in UHV) signal transport are shown in

Figs. 2–6.

L. Carl!en et al. / Nuclear Instruments and Methods in Physics Research A 516 (2004) 327–347 329

digital buses. The high-level signals to and fromthese chips are transported by a signal bus, whichsignificantly reduces the number of electrical

signals that need to pass through the vacuumwall. ASIC-based readout was thus chosen be-cause it allows major space and cost reductions.

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Furthermore, adoption of ASIC electronics hasallowed a considerable reduction in size and powerconsumption (see Section 2.2) as compared toconventional electronics. The ASIC group atSINTEF Electronics and Cybernetics was chosento design the microchip.

2.2. UHV issues and power consumption

The VLSI chips must obviously be completelycompatible with the UHV environment within thestorage ring. VLSI chips are normally fabricatedfrom low vapour pressure materials (Si, Al, SiO2;silicides, etc.), which are suitable for UHV use.Moreover, the baking of the vacuum system toremove water and other high vapour pressurecontaminants must be contained within thethermal budget. Generally, the thermal budget isset by the B400�C anneal to alloy the Almetallisation and thus a mild (120–200�C) bakeshould not influence the chip performance. Otherrequirements are that both the adhesive, used tobond the chip to the substrate and the GMB, mustsatisfy the UHV requirements. In addition surfacemounted auxiliary components such as resistorsand capacitors must be fabricated from ceramicmaterials and Ag–Pd alloy contacts. A detaileddescription of out-gassing tests of materials andcomponents is presented in Ref. [1].

High power consuming elements (high resolu-tion ADC, power distributors and regulators andlogic level buffering and conversation) are alllocated outside the chamber on the ADC board.The GMB provides enough heat-sink from its

Table 1

Detector signal level span, resolution and noise level and detector ca

Detector Channel

designation

Signal span

(MeV in Si)

DE; 10 mm Si E1 0–30

E; 300 mm Si E2-low 0–230

E2-high 0–23

GSO/PD E3 0–5

6 mm=300 mmVeto E4 0–230

300 mm Si

mechanical mounting [1] to accept the powerconsumption of the VLSI chip which is estimatedto be no more than 40 mW with nominal biasreferences.

2.3. Sensitivity and noise requirements

Table 1 summarises signal level span andrequired noise levels for the analogue spectroscopysignals in the Si detectors and photodiodes. Thesignal and noise levels are specified in terms ofthe signal amplitudes from protons incident in thedetector. They create one electron–hole pair forevery B3:67 eV of energy deposited in electronicprocesses. The deviation from this value is lessthan B10% also for IMFs [5]. In order to achievea wide enough dynamic span in the E2 channel(the thick Si detector) the signal is fed into twochannels with different gains. The acceptable noiselevel for each spectroscopy channel is set by therequirement for separating IMFs with unitydifference in proton number, Z: The actualperformance of the detectors, obtained underrealistic conditions, and details on their construc-tion and performance are presented in Ref. [2].

2.4. Trigger considerations and pile-up issues

In order to achieve a flexible system, the readoutsystem generates internal fast triggers that can becombined with fast and slow trigger informationby conventional fast NIM electronics outside thevacuum chamber. This trigger electronics instructsthe readout computer to send a ‘‘T1’’ signal on the

pacitance specifications for each kind of Si (PD) detector

Resolution

(FWHM) (keV

in Si)

Electronic noise

(FWHM) (keV

in Si)

Detector

capacitance (pF)

B50 o50 1000

B20 o15 35

B20 o15 35

B17 o7 44

B20 o15 35

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Readout- and control bus (Fig. 2) that initiatesreadout or to reset the entire readout system(global reset). In particular the trigger logic basesits decision on:

* Internal trigger when a certain light particle(essentially p, d, t, 3He; a) multiplicity isexceeded.

* Internal trigger when a certain IMF multiplicityis exceeded.

* External fast trigger from the PF-WALL [4] orother fast external detectors (e.g., plasticscintillator telescopes for charged particles andliquid scintillators for neutrons).

* External, slow (0.5–1 ms) trigger from theauxiliary HR-TOF array [3].

* Combinations of the above.

Two types of pile-up are of importance: (i) localpile-up where two or more particles enter a singledetector telescope within the period the input isopen (this corrupts the information from indivi-dual detector telescopes) and (ii) global pile-upwhen particles from two events impinge on twodifferent detector telescopes within the input activetime. Provided the time that the particles enter thedetector is different, global pile-up events can beidentified and separated without loss of anyphysics information. This is achieved by startinga time-to-analogue converter (TAC) each time aparticle enters the telescope. Local pile-up isidentified on-chip and signalled by setting a digitalflag on that particular telescope where it occurred.

2.5. Calibration and stability

In any detector system that measures spectro-scopic properties, calibration and stability are keyissues. For our purpose we require absolute energyto be measured in each detector telescope. Thecontrol of temperature associated gain drift in theelectronics is not trivial since the major part is invacuum. Furthermore, the response of individualVLSI chips may exhibit non-linear behaviourbecause of the large signal span. The philosophyadopted to overcome these difficulties, is to buildup a dynamic calibration database that enables thesignal from each channel to be transformed to anabsolute energy. The control of the signals is

carried out both by a programmed trigger pulsegenerator that is used to measure the electronicresponse of each channel on every chip during thestorage ring cycle and in addition by the absolutecalibration of each detector channel periodicallyagainst radioactive 241Am reference sources. Byusing this approach thermal gain drifts in theelectronics and response changes in detectors canbe compensated for.

2.6. Interface philosophy

The interface between the chips and the rest ofthe data acquisition system serves as an informa-tion concentrator. The approach adopted isillustrated in Fig. 3. The analogue and digitalsignals are synchronously clocked out onto serialanalogue and digital bus lines from each chip inturn. A travelling-token address system is used.The synchronous clock is computer controlled sothat chips that do not contain detector signals thatexceed a well-defined noise threshold are quicklyskipped over, whilst those chips that hold validevent data are read out more slowly to achieveaccurate conversion in the ADC. In this way, nulldata is filtered away allowing the system to handlereasonably high data rates in combination withhigh granularity and low average multiplicity.

3. The ASIC readout chip

3.1. Functional description

Figs. 4 and 5 present functional schemes of theanalogue and digital blocks of the mixed-modeCHICSi VLSI chip. The analogue block performsanalogue spectroscopic signal processing andgeneration of digital signals that are processed inthe digital block. When a particle enters anydetector telescope the signals from three detectorsare fed to separate charge-sensitive preamplifiersfor the channels E1 (10–12 mm Si detector), E2(300 mm Si detector), E3 (6 mm=300 mm GSO/PDdetector) or E4 (300=500 mm Si detector). It shouldbe stressed that either the E3 channel (forwardangle telescopes, FAT) or the E4 channel (largeangle, LAT or medium angle MAT telescope) is

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DE

TE

CT

OR

S

E1

E2

E3

E4

Block

Analogue

DigitalBlock

Multiplicity and Event Trigger Bus

Multiplexed Analogue Spectroscopy Signal

DiscriminatorOutputs

LevelsThreshold

Discriminator

Control Signals

Readout andControl Bus

ControlSignals

PatternHit

ProgramData

Hit + Multiplicity

Fig. 3. A block scheme of the CHICSi readout schematic.

S 1 sµ+V

Det

Test

+V

Det

Test

+V

Det

Test

+V

Det

Test

P

P

P

P

S 200 ns

S 1 sµ

S Hi 1 sµ

S 200 ns low

S 200 ns high

S 50 ns

S 1 sµ

S 200 ns

SL 200 ns

SL 1 sµ

E1

E2

E3

E4

D

D

D

D

D

D

D

Amux

AbusControl

Discrim. levels

Timing TACReset/hold

E1 noise

E1 event

E2 high gain event

E2 low gain event

E2 fast noise

E3 event

E4 noise

Fig. 4. Analogue block scheme of the CHICSi VLSI, Mk2 chip.


read out and the other one is terminated. Thepreamplifier signals are fed to fast (50 and 200 nspeak time) and slow (1 ms peak time) shapers. Theslow shapers are of sample and hold kind and the

analogue signals they deliver are subsequentlypassed to the analogue multiplexers, whichsequentially transmit them to the analogue outputbus. The hold signal is generated by the ‘‘T1’’

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BlockDigital

levelsDiscrim.

shapersHold

E1 eventE1 noise

E2 high gain event

E2 low gain eventshapersReset

E2 noise

E3 event

E4 noise

Event signalHit signal

Hit pattern

Hit patternT1 Timing TAC

Triggerbus

Control

T1

7 x 8 bitDAC

Hit evaluation logic

DigitalMultiplexer

Hit and event

multiplicity trigger

Pile updetection

Interfacecontrol

logic

Uploadcontrollogic

Analogmux and

buffer

Readout and control bus

Analogbus

Fig. 5. Digital block scheme of the CHICSi VLSI, Mk2 chip.


signal, which in its turn is generated by theexternal trigger electronics, 1 ms after a valid eventis identified. The reset is generated after 2 ms;internally by the digital block if no ‘‘T1’’ signal isreceived or externally after the readout sequence isfinished. In order to achieve the wide dynamicrange required for the E2 channel two analogueshapers are introduced in this channel with a low(�1) and a high (�10) gain.

The fast shapers feed discriminators that pro-duce a digital signal when the signal amplitudeexceeds thresholds corresponding to the noise levelor to another level that defines an event. Thethreshold levels are individually defined by 8-bitstatic Digital-to-Analogue Converters (DAC) inthe digital block. The longer ð200 nsÞ shaping timewas chosen to optimise amplitude resolution. Adiscriminator, fed by the fast ð50 nsÞ peak-time,free-running shaper from the E2 channel is used toderive a trigger signal optimised for timingresolution (E2 fast noise). Process variations are

to a large extent correlated for the differentshapers. Thus, all shapers are biased from a singleexternal resistance that serves as a current referencethat can be used to tune the shaping time.

The digital block performs a number of func-tions:

* Identification of hit patterns.* Generation of hit and multiplicity trigger

signals.* Pile-up identification and flagging.* Control of readout of analogue and digital hit

pattern information sent to the analogue andreadout/control bus.

* Handling generation of shaper sample-and-holdand reset signals from the ‘‘T1’’ signal.

* Controlling uploading of logic control signalsand programmable discriminator thresholdlevels.

The programmable hit evaluation logic con-tinuously monitors the output of the seven

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Table 2

Readout sequence of the eight clock periods of the CHICSi

Mk2 chip

Clock

period

Digital bus Analogue bus Address

bus

1 E4 noise Analogue

ground

0

2 E1 noise Analogue

ground

0

3 E2 fast noise E4 0

4 E1 event E1 0

5 E2 low-gain event E2 low-gain 0

6 E2 high-gain event E2 high-gain 0

7 E3 Event E3 0

8 Local pile up flag Analogue time 1


discriminators and if any of them have triggered, ahit signal will be generated. The E2 noisediscriminator, which has the best time resolution,always defines the time reference and generates aHIT signal, which is fed to the external triggerelectronics via the trigger bus. The hit pattern fromthe event discriminators is evaluated to determineif the pattern satisfies the Boolean expression,

Event ¼GðE1evE2lowev þ E2highevE3evÞ

þ %GðE1evE2lowev þ E2highevE3evÞ: ð1Þ

Here G is a programmed logic level that allowsselection of events with larger energy deposition inthe DE detector (here essentially IMF fragments)or a small energy deposition (light particles). Bothtypes of events will contribute to the eventmultiplicity signal. If the event criterion is satisfied,the 2 ms multiplicity signal, discussed below, is fedto the trigger bus. The chip produces, 200 ns afteran event, two fast trigger signals with 2 msduration. One is the event trigger that is used asthe time reference for the trigger and readout whena particle enters a telescope. The second one is amultiplicity signal that indicates when a particlesatisfies the event criteria above. These signals aredifferential and they are matched to an impedanceof 75 O: A special feature of them is that they areadded linearly to generate an analogue signal withamplitude proportional to the number of triggeredchips. This provides a simple multiplicity triggersignal.

If the external trigger logic (Fig. 2) determinesthat the event is to be read out, a ‘‘T1’’ signal isreceived by the chip, 1 ms after the initial hit signalwas sent. This signal is used to derive the shaperhold/reset signal discussed above. This preventsregistration of further counts by the analoguespectroscopy chain and also serves as a timereference for the pile-up detector.

The interface control logic deals with synchro-nous read out of analogue and digital informationfrom the chip to the readout and control bus. Thereadout sequence starts on the next leading edge ofthe clock signal when a ‘‘token in’’ signal occurs.After the subsequent eight clock periods, the datafrom all the analogue and digital multiplexerchannels is shifted onto the analogue and digital

readout bus lines. This sequence is specified inTable 2. During the last clock cycle of a readoutsequence a ‘‘token out’’ signal is generated andtransmitted to the next chip and the address bus isset to confirm completion. The minimum readoutclock period is limited to 10 ms for readout ofanalogue data but it can also be as short as 100 nsif only digital information is read out. Theanalogue bus output swing is72 V with a baselinevoltage varying from chip to chip between �1:5and �0:5 V: In order to compensate for this largevariation, that is associated with process varia-tions, the analogue ground level is read out fromeach chip during the first two clock periods inorder to provide a zero-level reference for mea-surements of the analogue signal levels.

The pile-up detector unit monitors the hit signalto determine if local pile-up takes place and alsostarts an analogue timer that can be used as an off-line signature for global pile-up. It also provides alogical signal if one or more events enter thedetector telescope after the first hit signal was sent.This local pile-up flag signal is fed to the digitalmultiplexer. In addition a TAC signal is used togenerate an analogue clock signal that is passed onto the analogue multiplexer and used as an off-linesignature for global pile-up. The TAC is thusstarted by any of the fast E2 discriminators andstopped by the T1 signal. It should be stressed thatpile-up information is only stored off-line.

The upload control logic is used to program thestatic DACs. These are used to generate the

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threshold levels for the noise and event discrimi-nators and set the programmable hit evaluationlogic and set an ‘‘always readout’’ level. Thefunction of this signal is to allow all channels ofthe chip to be read out even if no hit has takenplace. The same address sequence is used toprogram the DAC values for setting the thresh-olds.

3.2. Preamplifier and input circuits

The preamplifier/shaper chain determines theoverall spectroscopic performance of the chip.Fig. 6 shows the schematic of the input circuit. Thecharge sensitive preamplifier is of cascode typewith the gain determined by the feedback capa-citor, Cf ; in parallel with Rf : For simplicity the DCoperating point is not zero but is shifted to a fewtenths of a volt from zero. Unfortunately the4:7 nF thin film DC blocking capacitors C1; C2

that are suited for UHV operation have a highleakage current. Thin film capacitors with Ag–Pdcontacts and type NPO dielectric were usedbecause of their low loss. Unfortunately the highvalue of Rf prevented stabilisation of the operatingpoint, the shift of which was sufficiently large as todrive the preamplifiers into a non-linear regime orsaturation when the full DC bias ð50 VÞ wasapplied across the (E2) detector. To overcome this,a DC path was provided via the protection diodes,D1 and D2: These act as a voltage clamp that

A

R bias

+V bias

Detector D1, D2

C1

C testC f

R f

C2

V out

Fig. 6. Schematic of the input circuit. Components within the

dashed frame are integrated on the VLSI chip.

reduces the offset current by clamping the DCpotential difference across C2 to close to zeropotential. D1 and D2 were implemented on-chip asa stack of p–n junctions. Simulations showed thatthese gave an acceptable protection of the pre-amplifier input against electrostatic discharge. Inaddition, capacitors for injection of test chargesinto the inputs are included on the chip for allchannels.

Following Nyg(ard [5] the equivalent noisecharge (ENC) in rms e� for an MOS preamplifiersuch as the one in the CHICSi Mk2 chip (seeFig. 7) is dominated by the thermal noise in thechannel at temperature T ;

ENC ¼2:71ðCdet þ CinÞ

e

ffiffiffiffiffiffiffiffiffiffiffiffiGkT

3tpgm

sð2Þ

where Cdet and Cin are the detector and MOStransistor input capacitance, G is the excess noisefactor, which was taken to be 1:5; gm is thetransconductance of the input transistor and e isthe normal unity charge ð1:602� 10�19 CÞ: Understrong inversion conditions, gm can be determinedfrom

gm ¼

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi2mpCoxWID

L

rð3Þ

where mp is the hole mobility, Cox the gate oxidecapacitance per unit area. ID is the drain currentand W and L are the channel width and length,respectively. The channel length is set by theprocess, here the AMS 0:8 mm high resistive poly2BiCMOS process [6]. It has been shown by Nyg(ard

Fig. 7. Calculated electronic noise contributions (FWHM) in

the E1 channel, using proper AMS BiCMOS parameters.

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[5] that for a given power consumption theoptimum noise performance is achieved when

Cin ¼ 13

Cdet ¼ WLCdet: ð4Þ

The chip operation in UHV sets severe demandson the power consumption. One of the reasonsthat we use a voltage supply system with þ2V and�2V is to minimise the thermal power dissipationin the target chamber vacuum.

The noise is dominated by the thermal channelnoise of the input MOS transistor. Other con-tributions to the noise are

flicker noise :

ENCfl ¼ðCdet þ CinÞ2:71

e

ffiffiffiffiffiffiffiffiffiffiffiFk

2WL

rð5Þ

bulk noise :

ENCbulk ¼ðCdet þ CinÞ2:71

e

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiRbulkZ2kT

2tp

sð6Þ

bias resistor noise :

ENCbias ¼2:71

e

ffiffiffiffiffiffiffiffiffiffiffitpkT

2Rp

sð7Þ

detector leakage :

ENCdiode ¼2:71

e

ffiffiffiffiffiffiffiffiffiffiffiffiffieIdettp

4

rð8Þ

series resistor noise :

ENCseries ¼2:71ðCdet þ CinÞ

e

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiRserieskT

2tp

s: ð9Þ

The peaking time tp was chosen to be 1 ms: Thisrepresents a compromise between the optimum forminimization of serial leakage noise (tpB2–3 ms)and parallel noise introduced by irradiationdamage [2] of the detector ðtpB0:25 msÞ: The E1channel is certainly the most problematic one fromnoise viewpoint because of its large detectorcapacitance ðB1 nFÞ: Fig. 7 shows the principlenoise contribution expressed as FWHM in Si withdetector capacitance for this channel. The calcula-tion parameters are for the relevant AMS BiC-MOS process. Inspection of Eqs. (2)–(9) showsthat attainment of the ENC performance requiresoptimisation of the input MOS transistor trans-

conductance gm and gate capacitance Cin and ofthe peaking time tp of the analogue channel. Thisin turn is governed by the drain current ID (powerconsumption), and effective gate length L andwidth W (consumption of chip area) according toEq. (3) above. In Ref. [2] we show that the widthmeasured under experimental conditions is slightlyhigher due to the effects of spurious pickup.Evidently the noise contribution in the E1preamplifier channel, where the detector capacitanceis of the order of 1 nF; is dominated by the thermalnoise. The next largest contribution arises from theresistance in series with the input. This originatesfrom the loss factor of the decoupling capacitors C1;C2 (Fig. 6). For this reason ceramic NPO dielectric,which has a loss factor, tan dp0:1% at 1 MHz; waschosen for these capacitors.

The preamplifiers for the other detectors arematched to smaller Cdet: The same basic construc-tion was used but with smaller area inputtransistors. The gain of each channel was chosenso that the maximum input energy corresponds toa 0:5 V output voltage swing. In order to allow thecalibration of the overall gain for each channel testcapacitors Ctest; connected to the gate of the inputMOSFET, are included on-chip. Ctest was dimen-sioned so that the highest input energy for eachchannel corresponds to a 1 V signal on the testinput.

3.3. Control of spurious pickup

The combination of sensitive low-level analoguespectroscopy signals with high-level analogue andfast digital signals on the same chip implies that ifthe resolving power is to be maintained, seriousconsideration has to be given to control pick up ofspurious signals from other regions of the chip inthe input circuitry. This challenging requirement isachieved in a number of ways:

* Maintenance of near-static state with minimaldigital and high-level signal activity while thepreamplifier input is active.

* Low-level differential signaling for fast digitalevent and multiplicity trigger signals

* Separate power supplies for low-level analogue,high-level analogue and digital part of the chip.

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* Separate inputs for each preamplifier.* Chip layout with separation by ground planes

and trench isolation of low-level analogue,high-level analogue and digital circuits. Privateshields for each input connected directly tosource of input transistor. Low-level inputsignals not crossed by any signal or power line.

It turned out that propagation of spurioussignals to the input circuits via the power lineswas a major issue. This was particularly trouble-some because of the large distance between thechip and readout control board where the powersupply regulators are located. This leads tosubstantial power supply line impedance whichhad to be overcome by using separate 72 V powerbus lines for the low-level analogue, high-levelanalogue (shapers and multiplexer) and digitalcircuits that were bussed to each chip. These powerlines were individually decoupled off-chip butclose to the contact pad. The separate power lineswere connected together at the readout controllerso that the power bus line impedance contributedto the decoupling rather than acting against thedecoupling, as would be the case if they were

Fig. 8. Optical microphotograph o

joined together close to the chip. To reduce pickupfurther, each preamplifier is provided with aground input that serves to provide the commonground contact to the detectors and with on-chipground planes that serve to shield the input lines.Outside the chip these completely surround theinput line as well as the decoupling capacitors andbias resistor.

Fig. 8 shows an optical micrograph of the entireCHICSi readout chip. The E1–E4 preamplifiersare located along the left-hand side of Fig. 8. Thelarge (grey) areas are the meandered feedbackresistors in high resistivity poly-Si. The large areainput MOSFET required to match the high Cdet;10 mm Si, DE detectors in the E1 channel can beclearly discerned. The digital and analogue outputcircuits are located on the opposite side of thechip. Between the high-level circuits with high-level output signals and intense switching activityis a B1 mm wide band containing the DACs.These are completely stable during the phase whenthe preamplifier inputs are open. The shapers anddiscriminators are in turn separated from thepreamplifiers by wide power supply and groundlines.

f CHICSi, Mk2 readout chip.

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3.4. Chip performance

The resolving power of the entire detectortelescope + readout system can be seen fromFig. 19 in Ref. [2]. This represents data on particlesand fragments coming from 17 MeV per nucleon20Ne on 197Au reactions obtained at the GustafWerner cyclotron at TSL in a slightly less extremeUHV environment, about 1� 10�4 Pa; than in theCELSIUS cluster-jet chamber under full target gasflow (a few times 10�6 Pa). These measurementswere made with detector telescopes mounted onthe GMB at 20� laboratory emission angle. Fromthe results of these tests we could determine thatfrom all DE–E combinations that are going to beused for particle identification (E1 vs. E2, E2 vs.E3 and E2 vs. E4) in the CHICSi telescopesthere is full charge resolution for fragments up toZ ¼ 10 or more. The energy resolution dE=E

(FWHM) is of the order of 10% for the E1channel and much better, about 2% for the otherchannels as expected. In the E2 (high gain)-E4combination (using two 300 mm Si detectors) wecould even separate p, d, t, 3He and 4He isotopes.In a more recent commissioning run at CELSIUS,1

isotopic resolution could be achieved for evenlarger fragments (e.g., 10B; 11B).

CHICSi must be able to determine the absoluteenergy of a particle in any detector at any timeduring an experiment. The response function,which describes the relation between pulse ampli-tude (converted in the ADC) and the equivalentenergy deposited in the detector (from which theparticle energy can be determined) can both benon-linear and have long-term variations. Non-linearity is normally found for large amplitudes asseen in Fig. 9, which also shows that increasingpulse amplitudes (c) result in stronger non-linearity (see also Ref. [7]). Provided the responsefunction is monotonic and can be described by thecalibration, this is of no practical consequence.Measured noise performance as a function of thedetector capacitance for all channels is shown inFig. 10. For the E1 channel, the most one criticalbecause of its large detector capacitance, also the

1CA47 commissioning run at CELSIUS/TSL, November 11–

17, 2002.

calculated noise is shown (the same calculation asin Fig. 7). The requirement of in-UHV operationimplies that there may be considerable slowthermal gain drifts. This is because only coolingof the chips by conduction is possible. Moreover,chip-to-chip process variations will lead to differ-ences in the response even if they were observed tobe small for the CHICSi Mk2 chips (see Fig. 9).

It follows that the electronic gain of eachdetector channel must be individually calibrated.The method presented in Ref. [2] was used forcalibrating the GSO/PD detectors whilst thestandard method of using the back bending points(see Fig. 19 in Ref. [2]) in the DE–E plots was usedfor calibrating the Si–Si combinations for lightparticles. In order to establish an absolutecalibration for each individual channel we proceedas follows:

* For each injection cycle of the storage ring, theelectronic gain response function of eachindividual channel is characterised from theADC conversion result applying to the testpulse input (Ctest in Fig. 6) a series of test pulsesgenerated under computer control by a DAC.

* To correct for the response function changesdue to temperature and (eventual) radiationdamage effects [2,8] we periodically determinethe absolute calibration by exposure of eachchannel to alpha particles from a radioactivesource.

From these two calibrations a dynamic calibra-tion database was made up of the look-up tables ofcalibration parameters for each spill.

3.5. Choice of chip technology

The requirement of in-vacuum operation of thereadout chip places strong technological demandson fabrication. In particular the chip must beunaffected by vacuum bake out with no powerapplied and the contacting technology must beUHV compatible. Si microelectronic technologies,where the chip is coated with a passivating glasslayer and conventional electrical contacting is byultrasonic bonding Al–1% Si wires to Al–Cu pads,is inherently UHV compatible because of the lowvapour pressure materials. The power-off thermal

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Fig. 9. The pulse amplitude vs. the input energy of channels E1 and E2-high gain (upper, left) E2-low gain and E4 (upper, right), E3

(lower, left). The (lower, right) figure represents the analogue time (TAC) signal vs. input time.


budget of such chips is 350–400�C and governedby the alloying of the Al-metallisation.

It was decided to realise the preamplifier feed-back resistances in high resistivity poly-Si ratherthan using an MOSFET that has poor linearity.Although it is quite possible to overcome the non-linearity [9,10] with current mirror techniques, theextra circuitry is complex and consumes chip area.A Bi-CMOS technology from AMS [6] with0:8 mm minimum drawn gate length and highresistivity poly-Si layer was chosen. This allowson-chip capacitors to be fabricated. The gatelength and 12 GHz Ft for this process enabled an

effective combination of low-power mixed modeCMOS with fast bipolar circuits.

4. The Grand Mother Board (GMB)

The GMB of area 450� 45 mm2 houses detec-tor telescopes on one side and VLSI chips on theother. It also provides all necessary electricalconnections between the internal and external partof the readout system. Figs. 11a and b showphotos of the chip-side and the telescope-side ofthe GMB. The present version of CHICSi contains

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Fig. 10. Input equivalent noise as a function of the input equivalent capacitance. Points represent data and the dashed curve represents

calculations. Arrows show the detector capacitance.


28 GMBs; each comprised of 18 telescope mod-ules. The total system has rotational symmetryaround the beam axis to form a barrel-shapedarray of detectors [1]. The circulating beam passesalong the axis of this barrel and all individualdetector telescopes are directed towards the inter-section between this beam and the cluster-jet targetbeam.

The GMB is fabricated from a standardmaterial for printed circuit boards, FR-4, whichis an epoxy resin, reinforced by glass fibres [1].This material makes the multi-layer GMB rigidenough to allow proper positioning of the tele-scopes, by fixing them into holes in the board. TheGMBs are in their turn mounted onto the CHICSisupport skeleton by 0:5 mm thick stainless steel

bars which provide high mechanical stability fordetectors and also serve as passive cooler andtemperature stabilising elements, to minimiseelectronic drift in detector signal amplitudes. TheGMB is electrically insulated from the metalholder by a separate FR4 sheet of the same sizeas the board itself. A detailed description ofmechanical structures is found in Ref. [1].

The relatively large dimensions and the longsignal- and power lines on the GMB make thedesign sensitive to pickup and cross talk. Inparticular the weak analogue detector signals canbe influenced by transitions of the digital outputsignals. It was therefore decided that the GMBshould be made as a multi-layer (six layers) modewhere power and ground lines are distributed by

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Fig. 11. Photos of the electronics side (a), and the telescope side (b) of the GMB. The photo in (c) shows the GMB top layer.


broad copper polygons and the analogue anddigital powers and grounds are kept separated.The signal lines are sandwiched between groundplanes and sensitive weak signal leads are made asshort as possible. Extensive use of decouplingcapacitors, placed close to the power pins of theVLSI chips, helps to reduce the switching noise onthe power lines. The GMB top layer is shown inFig. 11c while the contents of each layer ispresented in Fig. 12.

All detector signals are transferred to theVLSI chip via individual bias-resistor protectiondiode networks on the GMB. Due to the strongvacuum constraints, all surface mounted compo-nents are glued to the GMB with the EPO-TEKH20E, UHV compatible silver epoxy [1]. TheVLSI chips are glued and bonded directly to theGMB without any cover or any kind of inter-mediate test board. This facilitated replacement ofbad chips by simply mounting a new chip on topof a bad one and then re-bonding. This procedurewas successfully utilised for about two chips perGMB.

Each row of 18 chips, corresponding to oneGMB, is connected to a single bus cable with onlyone chip sending data at a given time. This activechip is defined by a travelling token signal asdiscussed in Section 3.1. The active chip clocks outthe analogue and digital readout signals onto theproper bus, timed with the readout strobe. Thisprocess is repeated until the token has passed all

the chips in the row. This daisy-chain organisationof the token is illustrated in Fig. 13.

The chip-on-board mounting of detectors to theMB and the MB to the GMB make use of contactsprings. This solution was found to be reliable andrequires no additional area or height. Gold-platedcontact springs are used to make connection to thecontact pads of the detector telescopes. Each MB,made from 1 mm thick ceramic (alumina) has five-conductor MB—GMB contacts made from U-shaped, Au-coated, Cu springs, fixed in roundslots through the GMB. These slots are open onone side for MB contact with the Au-metallisation.

Flexible printed cables for 25 standard and eightshielded lines per GMB serve two adjacent GMBsand connect to a common 50-pin DSUB-typeUHV feedthrough connector on the main CHICSiflange. This cable consists of three layers of FR-4material surrounded by metal (Cu) shielding. Thissolution provides good screening for the noisesensitive lines both from external pickup andcross-talk. One end of this flexible cable has a50-pin DSUB connector that is attached to thefeedthrough flange while the other end is split intotwo 34-line parts each serving one GMB.

5. External readout modules

The GMBs are grouped in pairs with a common50-pin DSUB-shaped feedthrough. The external

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Fig. 12. The principle contents of each layer of the CHICSi GMB.


side of each feedthrough flange (Fig. 1) containsfive 50-pin DSUB connectors [1] attached to avertical Power Distribution Board (PDB). ThisPDB transports signals to the next level ofprocessing, the ADC board. Each ADC boardthus handles one pair of GMBs and consequently36 CHICSi telescopes. The data flow from thisADC board is buffered event-by-event into a localdual-ported FIFO memory. The output of thismemory is connected to a flat-cable bus, controlledby a master module described below. Connectionsfor trigger signals, busy signals and communica-tion of the CHICSi chip parameters are introducedvia a separate communication module (Combox,

see Section 5.4), which is also connected to the flat-cable bus. All these external readout units and theVME-based Data Acquisiton system (CHICSi-DAQ, see chapter 6) are described below. TheADC boards are linked to each other and to theCHICSiDAQ VME system in the way schemati-cally shown in Fig. 1.

5.1. The power distribution board (PDB)

The multi-layer PDB, transfers digital andanalogue signals between the GMB and theexternal electronics. In order to minimise pick upof spurious electronic noise the PDB is mounted

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within a separate shielding box. Thus, the noisyenvironment of the ADC board is avoided. ThePDB houses the following units:

* Connections between the ADC board and theGMB.

* Voltage stabilisers.* Power line filters.* Test pulse connectors.

Fig. 13. A schematic view of the daisy-chain organisation of

the token of the VLSI chips.

Clock,Dig.Bus,Adr.Bus,

AMP

ADC

Pow

er D

istr

ibut

ion

Boa

rd (12 bits)

Pµ

4bitID

T1,Alw.,Reset,PUR,R/W

Fig. 14. A block scheme of the electro

* Detector bias voltage connectors.* HIT and EVENT differential line receivers.

Thus, the PDB provides each GMB pair withcommon power stabilisers (72:0 V analogue,72:0 V digital and 72:0 V reference voltage),detector biases, test pulse inputs and ground. Allevent signals and chip control parameters aretransferred between the GMB and the ADC boardby the PDB.

5.2. The ADC board

Each ADC board (Fig. 14) serves two GMBs.Its function is based on a 20 MHz; PIC16F877microprocessor. This initialises the ð2� 18Þ CHIC-Si chips at power-up-reset and provides theirindividual threshold settings, stored in its internalElectrical Erasable Programmable Read OnlyMemory (EEPROM) unit. It then polls the eventtrigger input for the fastest possible start-up ofevent treatment. ‘‘Mail’’ for chip parametersetting, transferred via the Combox (see below),can cause interrupts during this polling but notduring event treatment.

All ADC boards in the fully equipped CHICSidetector are identical. Unique board identificationnumbers are assigned by means of a hexadecimal(four bits wide), rotary switch on each board.

When a trigger pulse is received the micropro-cessor takes the following action:

�

nics o

Generates CHICSi chip clock pulses.

2

Daisy chainto the next

slave

MasterDaisy chain

from theprevious slave

Rec.

I C Bus

&

Empty Flag

Rea

dout

Bus

12x2 diff. Driv.FIFO

FIFO Write

f the CHICSi ADC board.

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�
Sends the first token signal for each GMB. � If the chip signals valid data it:
3
constructs a unique telescope identifica-tion number from the ADC 4-bit id and
3
the chip counter (5 bits) and writes it intothe local 12 bit wide FIFO buffermemory,
3
clocks out the eight analogue levels andthe flags,
3
controls the 12-bit successive approxima-tion ADC,
3
transfers the ADC output to the FIFObuffer and
3
writes a byte with the eight binary flagscollected from the chip.
�
If the chip does not signal valid data it: 3 does not write any output to the FIFOmemory (zero suppression on telescopelevel).
�
If no chip signals valid data it: 3 writes a unique ‘‘empty-data’’ identifica-tion number for this ADC board to theFIFO memory.
�
Signals ‘‘finished’’ on the daisy-chain of theADC boards.
Some examples of ‘‘mail’’ are:

* ‘‘Change values for thresholds!’’* ‘‘Send power-up reset!’’* ‘‘Shut-down a single (ringing) chip!’’* ‘‘Set ALWAYS for one particular GMB!’’* ‘‘Set condition bit’’!

The I2C (Inter-IC) bus (see Fig. 14), developedby Philips Semiconductors, provides a two-wire,bi-directional interface. The outputs of the FIFOsare connected to a 34-line flat cable bus viadifferential drivers. This cable also carries controlsignals and the I2C connection for the ‘‘mail’’communication.

A very important signal for the overall timing ofthe system is the T1 signal (Section 3.1). This isgenerated externally from a fast shaper and thentransferred from the ADC board precisely 1 msafter an event is registered. The microprocessorcontrols the entire readout sequence by synchro-nous control of the ADC, FIFO and chip readoutclock sequence. A particular feature is that the

serial readout speed can be higher for low multi-plicity events, where only a few chips are fired.This is achieved by a rapid clocking through all thechips in the chain (10 ms per chip). If the chip hasfired (E2 noise threshold discriminator triggered)the clock frequency is slowed down to B100 msper chip to achieve adequate selectivity for thedata to be converted accurately by the ADC. Thisenables readout of the entire CHICSi array in320 ms for multiplicity one and B1 ms for highmultiplicity events. This corresponds to a deadtime less than 10% at a maximum event rate,estimated to be 100 events/s. On-line suppressionof null data (see above) is simply achieved by notwriting null data into the FIFO.

5.3. The Combox

The flat-cable bus is connected to a simplemodule for connection of the trigger, the I2C busand the busy signal. The busy signal is generatedby a TTL flip-flop register at the reception of thetrigger signal or by the master during ‘‘mail’’communication. It is reset by the master-modulewhen asked for a new event or after finishing a‘‘mail’’ communication.

The Combox also houses a microprocessor,used as an interface for communication betweenthe CHICSi internal mail I2C bus and a standardRS232 serial communication link (Fig. 1). Sincethe main purpose for this communication isthreshold settings requiring 2� 18� 7 bytes forone ADC board, the mail source is normally a PCwhere text files of parameters are edited, storedand transmitted.

5.4. The master module

The 34-line flat cable bus connects in parallel allthe ADC boards to the master board. When all the14 ADC boards have completed readout anddelivered either at least one set of valid data(including identification number) or an ‘‘empty-data’’ identification word, the master moduletransfers the data from the FIFOs to the destina-tion on the DAQ.

Two kinds of master boards have been devel-oped. One version has a microcontroller that

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handles the bus transfer and delivers data as TCP/IPdatagram packages to a local thinwire Ethernet.Any suitable receiver, such as a PC running underWindows or Linux, can be used for storage,monitoring and display of data. This version hasnormally been used for laboratory tests withCHICSi as a stand-alone device. The secondversion, used in full-scale experiments, contains asimple ‘‘Industry pack (IP) module’’, 2 i.e., a piggy-back board carried by a Motorola VME CPUmodule. Here the bus traffic is handled by aMotorola MC68020 microprocessor, delivering datato a dual-ported memory in a VME communicationmodule, which is linked by an optical fibre to themain DAQ system. This system was used duringcommissioning periods of CHICSi at CELSIUS.

6. Data acquisition system

The complete readout system, including dataacquisition, was presented in Fig. 1. The mastermodule, described above, is an example of a dataserver, which can handle simple test and develop-ment situations with few parameters recorded, aswell as complicated in-beam experiments. In thelatter case, several detector telescopes can betriggered and provide high multiplicity (event-by-event) data.

During the test runs performed at CELSIUS,the R-Quant Data analysis Studio [11] on aLINUX-operated system has been the client. Afterestablishing connection with the CHICSi master,for true experiments at CELSIUS, single-eventdatagrams have been saved on disc, sorted anddisplayed conventionally. Since CHICSi experi-ments require the possibility of on-line control andmonitoring of thousands of detectors, a specialCHICSi control client is developed to performdata sorting. This utilises the full power of theROOT framework [12], a modern and advancedobject-oriented facility for data sorting, visualisa-tion and presentation. The first version of CHIC-SiDAQ with a ROOT-based event logger andR-Quant has been used in the in-beam tests and

2 IndustryPack and IP are trademarks of GreenSpring

Computers Inc.

commissioning at CELSIUS. R-Quant is a specialROOT-based integrated development environ-ment (IDE) for large-scale on/off line dataanalysis. The R-Quant programs are able to collectdata from all detector telescopes and display themon a screen as one- or two-dimensional graphs.Spectra from the CHICSi detector array can theneither be shown in real time mode, with contin-uous updating on the screen or just be collectedand stored. In either case the spectrum can beexamined in detail using zooming, cutting, etc.routines, or by comparing on-line sorted spectrawith stored reference spectra.

During early experiments, CHICSi data havealso been monitored and collected with thestandard TSL acquisition, the SVEDAQ system[13]. This system includes the event builder VMEcrate, the tape server VME crate and a CAMACcrate. Two independent ETHERNET LANs areused during the operation—for control and fordata transfers. A SUN Ultra-10 workstation isused for the system control and the on-line datavisualisation. The event builder crate contains aboard with Motorola 68040, 25 MHz CPU run-ning the main on-line data acquisition programunder the real-time VxWorks operating system.Two LAN communication modules, the serialinterface and the CAMAC branch driver areplaced in the same crate. The CAMAC branchdriver provides communication between the CPUand the CAMAC crate controller to read out theCAMAC modules accumulating data from ‘‘aux-iliary’’ systems of the experiment. The SBS-414communication board, linking SVEDAQ toCHICSiDAQ via the fiber optics cable, wasplugged into the event builder crate. The tapeserver crate contains a board with Motorola 88000RISC CPU. The CPU runs with custom-made OS,it receives the event data blocks from the eventbuilder via LAN and records them to the Exabytetape. The Ethernet communication modules, theserial interface, the SCSI interface and the harddisk with the CPU OS are embedded in this crate.The Exabyte tape drive is connected to the CPUvia the SCSI interface.

In recent experiments, taking coincident datafrom CHICSi and its auxiliary systems [1], theCHICSi master acted as a server. The auxiliary

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systems use CAMAC standard and SVEDAQ isthus incorporating the CHICSi VME informationwith this CAMAC information. A block scheme,presenting this mode of operation, is shown inFig. 15.

The main lines of the protocol are normally,

* The client asks for an event by writing a VME-bus destination buffer address in the master’smailbox.

* The master acknowledges the mail by returningthe address negated into the mailbox and startsto poll the CHICSi event-delivered flag.

* The master transfers the data from the FIFOchain to the VME destination buffer.

* The master signals Event-finished by writingzero in the mailbox.

* The master waits for a non-zero value in themailbox.

An extrapolation of the observed data collectionrate from the first combined experiment, withlimited number of telescopes, to an experiment

CPU serial interface

detectors systemsfrom "auxiliary"

CPU

controldataether.

dri

RS-232

ethernet

event b

brn

Data LAN

Control LAN

CAMAC modules

SUN workstation

VM

CA

SCSI

ethrcntr

RS232

ether.data

CPU systemHDD

Exabyte tape

VME tape server

Fig. 15. The linked CHICSi VME - SV

with the full CHICSi set-up, shows a rateof B200 kbyte=s and in no expected experiment> 1 Mbyte=s: This corresponds to an upper limitof the event rate of 1� 103 s�1:

A next generation data acquisition system,based on the VME embedded Motorola PowerPCCPU running LynxTM real time operating systemis under development [14]. This system uses Cþþprogramming paradigm, which provides state-of-art object-oriented, software utilising networking,multithreading and resource sharing UNIX tech-niques. This system is designed to supportsimultaneously auxiliary systems using CAMACand VME standards and CHICSi using VMEstandards alone.

7. Concluding remarks

A readout system that is based on a VLSI in-ultra-high vacuum (UHV) front-end chip andseveral external data transferring modules has

to CHICSi

Master trigger to SVEDAQ

"Computer busy"to the trigger circuit of the setup

414verSBS

fiberopt.

uilder crate

ch

E

MAC

CCA2

contr.crate

VMECHICSi crate

CPUmastermodule

414SBS

opt.fiber

EDAQ VME acquisition mode.

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been developed for the CHICSi, high granularity,DE–E detector telescope array.

By careful consideration of noise and distur-bance propagation it has been possible to combinehigh-resolution spectroscopy electronics with fastdigital trigger electronics on the same chip. Eachchip of this kind reads out one CHICSi telescopecontaining an ultra-thin (10–12 mmÞ Si detector, a300 mm Si detector and alternatively a GSO/PDdetector or a second 300 mm Si detector.

A daisy chain readout architecture has beenused for the modular GMBs, that house 18telescopes and associated readout chips. Usingnull data suppression for low multiplicity eventsallowed a high readout speed to be achieved for ahigh granularity detector array for low multiplicityevents.

A simple scheme for handling global and localpile-up has been devised that allows globalpileup to be gated away without loss of eventdata.

After passing the UHV-to-air feedthrough,signals are transferred to the ADC board via thePDB which carries the power lines. From all 14ADC boards, each serving two GMB, the data aretransferred to the data acquisition.

Data are transmitted via a fibre optics link tothe general data acquisition system SVEDAQ.

The complete readout system has proven towork well during commissioning at the CELSIUSstorage ring where data from CHICSi and itsauxiliary systems have been stored in a coincidentmode on event-by-event basis. Recently a completeexperiment was also carried out successfully.

Acknowledgements

The CHICSi project has been funded by theKnut and Alice Wallenberg Foundation, for whichwe are deeply grateful. Funds for travellingbetween Lund and Uppsala have been providedby the Swedish Natural Science Research Council(now the Swedish Research Council).

References

[1] L. Westerberg, et al., Nucl. Instr. and Meth. A 500 (2003)

84.

[2] P. Golubev, et al., Nucl. Instr. and Meth. A 500 (2003) 96.

[3] A.V. Kuznetsov, et al., Nucl. Instr. and Meth. A 452

(2000) 525.

[4] A. Budzanovski, et al., Nucl. Instr. and Meth. A 482

(2002) 528.

[5] E. Nyg(ard, Ph.D. Thesis, U. Oslo Internal Report, No.

230, 1997.

[6] Austria Mikrosysteme International, Data Sheet BYB/

BYE, 0:8 mm BiCMOS Process, ver. B, July 1995.

[7] P. Golubev, Fil. Lic. Thesis, Lund University, April 2001.

[8] H.J. Whitlow, et al., Nucl. Instr. andMeth. B 135 (1998) 523.

[9] M.A. Abdalla, C. Fr .ojd, C.S. Peterson, Proceedings of the

Seventh IEEE Conference on Electronics Circuits and

Systems (ICECS 2K), Lebanon, December 2000.

[10] M.A. Abdalla, Ph.D. Thesis, The Royal Institute of

Technology, Stockholm, September 2001, p. 24.

[11] QuantNet Ltd., 2003, information on www.smartquant.-

com

[12] Rene Brun & Fons Rademakers (1995–2003), information

on root.cern.ch

[13] T. Sundqvist, J. Nyberg, in: A. Ingemarsson (Ed.), TSL

Progress Report, 1996–1997, p. 21.

[14] A. Fokin, J. Nyberg, T. Sundqvist, in: A. Ingemarsson

(Ed.), TSL Progress Report, 1998–1999, p. 17.

http://www.smartquant.com

http://www.smartquant.com

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