chemical mechanical planarization historical review and...

Chemical Mechanical PlanarizationHistorical Review and Future Direction

Gautam Banerjee

Air Products 1331 Houston Avenue

Gilbert, AZ 85233, USA.

Contact: [email protected]

Robert L. Rhoades

Entrepix2315 West Fairmont Drive

Temp, AZ 85282, USA.

Contact: [email protected]

2 9th International Symposium on Chemical Mechanical Polishing (CM9th International Symposium on Chemical Mechanical Polishing (CMP)P)

INTRODUCTIONINTRODUCTION


Definition and HistoryDefinition and History

CMP = Chemical Mechanical Planarization (or Polishing)Adapted from optical lens polishing methods, i.e. telescope mirrors

Timeline:

1983 – Process invented at IBM Base Technology Lab in East Fishkill, NY

1986 – Oxide CMP development and pilot line

1988 – Tungsten CMP development (East Fishkill and Yorktown Heights)

1988 – Sematech CMP project launched

1992 – CMP first included in SIA roadmap

1995 – Industry embraces CMP. Ramping in numerous fabs.

CMP is now accepted as a “mainstream” process in fabs worldwide


Early Adopters and SuppliersEarly Adopters and Suppliers

Early Device Manufacturers (after IBM)– Intel, Micron, Motorola, Texas Instruments, National, Rockwell

Equipment OEM’s– Westech (later IPEC, then Speedfam-IPEC, now Novellus)– Strasbaugh – 2nd wave included Ebara, Speedfam, Cybeq, Applied Materials, etc.

Consumable Suppliers (Market share leaders)

– Slurries: Cabot, Rodel, and several homebrews (IBM, Intel, etc.)

– Pads: Rodel (Rohm&Haas), Thomas West, Universal Photonics


Life Before CMPLife Before CMP

Topography at ILD levels (some severe)Sloped wall vias generally limited designers to only 2 or 3 levels of metalEven for fabs that adopted tungsten plugs and SOG, stacked plugs were generally not allowed due to cumulative topography


Life After CMPLife After CMP

Topography under controlCMP enabled multiple levels of metalStacked plugs no longer an issueShallow trench isolation widely adoptedDrove several generations of shrinks and more complicated stacks

However … this technology also started to run out of steam for the most advanced CMOS devices


Cu CMPCu CMP

Dual damascene process integration for patterning Cu lines and viasPrimary process issues: Robust clear, defect density, dishing, erosionThe fastest growing CMP application for past few years, but still smaller than oxide and tungsten in terms of overall annual revenue

IBM PC603 microprocessor(circa 1998)


Various film stacks polished using CMP in Various film stacks polished using CMP in CMOS TechnologyCMOS Technology

… and CMOS is no longer the only device technology using CMP !!


CMP Technical DriversCMP Technical Drivers

The original drivers for CMP were (and often continue to be) related to issues in other process modules or with the overall process integration.

Oxide CMP- Driver #1: Depth of focus at photo

- Worse as linewidths shrank below 0.35 um

- Worse with additive topography of MLM

- Driver #2: Metal step coverage- Metal thinning on steep sidewalls- Topography induced etch effects- Inconsistent line resistance

Tungsten CMP- Alternative to plasma etchback- Solves severe plug recess from overetch- Enables stacked vias- Lowers defectivity

Shallow Trench Isolation CMP- LOCOS isolation hit physical limits- Shrinks below 0.35 um required new

isolation- Original integration used reverse mask etch

- Very sensitive alignment- Very expensive

- Direct STI CMP required years of slurry innovation and process development

Copper CMP- Driven by lack of acceptable Cu metal etch- Early difficulties with electroplating profiles- Cu/barrier metal forms electrochemical cell- Introduction of low-k dielectric complicates

an already difficult materials system


CMP Enabling Intel TechnologiesCMP Enabling Intel Technologies

Reference: J. M. Steigerwald; Microelectronic Applications of Chemical Mechanical Planarization; Ed. Y. Li, 2008, pp 651-685, © J. Wiley & Sons, Inc.


Various factors responsible for achieving Various factors responsible for achieving successful CMP resultssuccessful CMP results


Relative Sizes in CMPRelative Sizes in CMP

Upscaled CMP

Microelectronics and CMP if 1 micron were enlarged to 1 inch

Item Approximate equivalent

Slurry particle 0.1 micron 0.1 inch BB or large grain of sand

Pad asperity 10-40 micron 10-40 inches Basketball to laundry basket

Pad pores (IC1000) 50-100 micron 50-100 inches Small hot tub

Diamond on a conditioning disk 80-150 micron 7-12 feet Compact car

Oxide planarization length (typical) 4 mm 333.33 feet Length of a soccer field

Device - minimum feature size 65 nm 0.065 inch Diameter of a toothpick

Device - metal line thickness 600 nm 0.6 inch Diameter of a grape

Device - bond pad 100 micron 8.33 feet Tool shed footprint

Width of one average die 12 mm 1000 feet 3.3 soccer fields end-to-end

200 mm Wafer 200 mm 3.16 miles Area covered by average airport

300 mm Wafer 300 mm 4.73 miles Area covered by large airport

Polishing pad diameter 20-30 inches 8.00 miles Area covered by a small city

ActualSize

Upscaled Size


Comparison between conventional Al Comparison between conventional Al interconnect and Cu dual damasceneinterconnect and Cu dual damascene


Basic failure modes for Cu CMPBasic failure modes for Cu CMP


CMP ApplicationsCMP Applications

OxideSTI

TungstenCopper/Barrier/Low k


Step height as a function of oxide CMP polish time Step height as a function of oxide CMP polish time for structures with differing pattern densitiesfor structures with differing pattern densities


Process SequenceProcess Sequence

1. Deposit desired film or film stack onto the device side of wafer

2. Load unprotected wafer into rotating carrier (device side down)

3. Flow slurry (mixture chemicals and trillions of suspended particles) onto large diameter rotating polymer pad

4. Lower wafer onto pad and apply a controlled pressure ranging from roughly 50 lbs to several hundred pounds

5. Polish until sufficient amount of the film stack has been removed

6. Clean up mess left behind on wafer surface


Output metric interactions with process Output metric interactions with process recipe settings recipe settings

weakweakdon't caredon't careConditioner speed

ModerateweakweakweakConditioner force

weakModeratenonlinearnonlinearSlurry flow, SF

weakweakModerateweakCarrier speed, CS

STRONGModerateweakSTRONGTable speed, TS

weakweakModerateweakBack pressure, BP

STRONGModerateweakSTRONGDown force, DF

PlanarizationDefectivityUniformityRateProcess Settings

CMP Process Metrics


Pad

Hei

ght

Pad Height Probability DensityPad Lateral Dimension

Top Down View of 3-D pad Surface

Pad Asperities – Critical to Process Stability

Courtesy: Rohm and Haas Electronic Materials


Process Based Defect Improvement of W CMPProcess Based Defect Improvement of W CMP

(Top: No Coring; Bottom: Coring)(Top: No Coring; Bottom: Coring)


Schematic representation of 3 key steps in Schematic representation of 3 key steps in the modern Cuthe modern Cu--CMP processCMP process


Atomic Force Profile of a pattern wafer (MIT 854) after barrier Atomic Force Profile of a pattern wafer (MIT 854) after barrier CMP showing fang formation in the trenchesCMP showing fang formation in the trenches


Atomic Force Profile of a pattern wafer (MIT 854) after barrier Atomic Force Profile of a pattern wafer (MIT 854) after barrier CMP, showing no fang formation in the trenchesCMP, showing no fang formation in the trenches


Killer DefectsKiller Defects

Post CMP, several important defects are likely to appear on the surface of the wafer such as:

– Scratches– Cu lift off (due to underlying voids which

only show up after CMP process)– Slurry particles (large/small)– Organic deposits/organic particles– Corrosion pits on metal surface– Interfacial galvanic corrosion between

dissimilar meta//alloy/dielectric films– Water marks on low-k dielectric surface– k shift of porous ultra low-k films


Defect Reduction through CleaningDefect Reduction through CleaningPost CMP cleaning is an effective way to reduce many of the killer defects.Cleaning cannot remove the scratches, Cu lift off/voids, pre-existing corrosionBut post CMP cleaning does clean particles, organic and inorganic materials from the wafer surface very effectivelyPost CMP cleaning can also reduce or eliminate water marks from the low-k or ultra low-k surface very effectively without affecting k valuesProperly designed post CMP cleaning formulation should also not cause any kind of corrosion problem on the wafer surface


Post CMP Clean Performance on Wafers Post CMP Clean Performance on Wafers Polished with Two Different Barrier SlurriesPolished with Two Different Barrier Slurries

Aci

dic

Slu

rry

Alk

alin

e S

lurry


Effect of Post CMP Cleaning on Porous DEMS FilmEffect of Post CMP Cleaning on Porous DEMS Film


FTIR Spectra of FTIR Spectra of CoppeReadyCoppeReady®® CP72B on CP72B on PDEMSPDEMS®® (k=2.2)(k=2.2)


Post CMP cleaning performance Post CMP cleaning performance comparison on Cu waferscomparison on Cu wafers


Performance of Same New Cleaner on Pattern Performance of Same New Cleaner on Pattern Wafers Wafers –– Helping fabs integrate new processesHelping fabs integrate new processes

Cu/Ta Cu/Ru


New ApplicationsNew Applications

Analog/Mixed Signal/Power Devices

MEMS/NEMS

T(hrough) S(ilicon) V(ias)

Advanced Packaging


With each new dielectric or barrier film, it is often necessary to develop a new generation of slurries, pads and post CMP cleans. However, there is common refrain from the user community about the high cost of consumables and tools alike. Meanwhile suppliers complain about relentless downward price pressure combined with rising expectations for data and support!Strong competition requires development of new device technologies on ever-shorter timelines placing even more demand on available resources.

Future DirectionsFuture Directions


One way to increase efficiency of the CMP process is to have more throughput per tool, and the latest generation of CMP tools show some promise in that directionThe difficulty for consumable vendors is that more efficient tools generally use less of each consumable product per wafer passWith less being consumed and prices being driven lower simultaneously, vendors will have to find ways to minimize cost of product development and improve efficiency of manufacturing/distributionIn addition, some alternative technologies in development may eliminate or reduce the need for CMP in the long run, especially as quantum wire or quantum dot devices reach volume manufacturing

I like the “Only the fittest will survive” text block – nice touch!


While large fabs have the financial resources and existing infrastructure to develop new CMP processes and achieve an economical scale of manufacturing, smaller fabs or companies trying to integrate CMP into new devices generally find it difficult to invest large $$ to develop a CMP process without knowing if there will be adequate returns.Alternatives such as a “Fab-Lite” model or outsourcing CMP process development / small scale manufacturing have become very popular in recent years to meet the needs of this market segment.


AcknowledgementsAcknowledgements

The authors would like to acknowledge contributions from the following companies in terms of discussions/data/consumables to generate data which helped make this presentation possible

–Rohm and Haas Electronic Materials–Fujimi Corporation–Cabot Microelectronics Corporation–Entrepix, Inc.–Air Products and Chemicals, Inc.

Thank youThank you

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