Characterization Presentation

OFDM implementation and performance test

Performed by: Tomer Ben Oz Ariel Shleifer

Guided by: Mony Orbach

Duration: Semester

motivation

• Tera-Santa project in the Technion needs implementation.

• FPGA implementation of OFDM receiver will enable performance test and identification of architecture bottlenecks.

Project goals

• Implementation of an OFDM receiver on a FPGA.

• Give a good base and tools for future bottlenecks and capability testing.

Working environment

• Simulink via Matlab• Xilinx ISE 12.2• Modelsim

Top Level Block diagram

Demodulator Block diagram

Phase multiplier – Shifts the phase of the signal back to its original phase.Inputs: Q in, I in – Current sample’s values; A,B – Correction factors

outputs: Q out, I out – The correct signals values.Look Up Table(Qam4) – Translate the signal back to data in bits.

Inputs: Q, I – The correct signals values.outputs: QAM4_OUT – The translated data

Qam 16 modulation example

Phase Multiplier Block diagram

IQ multiplier– Shifts the phase of the signal back to its original phase. Inputs: Q in, I in – Current sample’s values; A,B – Correction factors

outputs: Q out, I out – The correct signals values.TDD– Time Domain DemuxInputs: 8 bits.outputs: D0-3 –each output channels the input data in an upwards order.

TDM– Time Domain muxInputs: D0-3 - 8 bits each.outputs: The output channels the input data in an upwards order.

IQ multiplier Block diagram

Output I Corrected output Q Corrected outputSignal Correction

(I+Qj) (A+Bj) = [I A-Q B]+[I B+Q A] j

IQ multiplier– Shifts the phase of the signal back to its original phase.First degree (multiplication) Delay is 3 cycles

Second degree (adder) Delay is 1 cycleHence we chose TDD and TDM to have 4 inputs\outputs

FFT Testing

Sinc function

XUP5

Testing environment

Dram XC5VLX110T Dram Data outData In

counter counter

Gant Diagram

1.4 – 15.4 16.3 – 31.3 1.3 – 15.3 16.2 – 28.2 1.2 – 15.2 13.1 – 31.1

Studying Work environment

Blocks Design

Blocks simulation

FPGA integration

FPGA simulation