chapter8 slides

8/8/2019 Chapter8 Slides

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Digital Integrated Circuits2nd Design Methodologies

Jan M. Rabaey

Anantha Chandrakasan

Borivoje Nikolic


One die

Wafer

From http://www.amd.com

Up to 12 (30cm)


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Numberoftransistors

101 K

1970 year1980 1990 2000

10

10

10

10

10

10

10

10

3

4

5

6

7

8

9

10

11

4 K16 K

64 K

256 K

1 M

4 M

64 M

256 M

1 G

intel microprocessorsstatic memory

The number of

transistors andresistors on a chipdoubles every 18months[Gordon Moore, 1964]

where N=digital estimation of complexity

In other words:The complexity growthrate of an IC is

proportional to itscomplexity at the

moment


Intel 4004 Intel Pentium (II)


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Source: sematech97A growing gap between design complexity and design productivity

1981

Logic Transistors per Chip (K) Produ

19831985198719891991199319951997199920012003200520072009

58%/Yr. compoundComplexity growth rate

21%/Yr. compoundProductivity growth rate

10

100

1,000

10,000

100,000

1,000,000

10,000,000

1

XX

X XX

X

x

100

1,000

10,000

100,000

1,000,000

10,000,000

100,000,000

10

2.5

.35

.10 Transistor/Staff Month


System

Register-Transfer

Gate

Circuit

Device

Accumulator

Command Register

Command Counter

Add

Input

+1

& & 1

JCK

TT

n+

p+n

n+p


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Define circuit function,inputs and outputs

hand calculations and circuitdevelopment

Circuit simulation

Meetsrequirements?

Design

Circuit placing (Layout)

Circuit re-simulation

Meetsrequirements?

Test chip preparation

Testing and evaluation

Fabrication

No No No

No

Yes

YesYes

Problem

solving circuit Preparation

Meetsrequirements?


ReliabilityStabilityAreaParameters Switching speed (delay) Leakage power Fan in, fan out Noise Immunity


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- Bipolar

* with saturated transistors- TTL, I2L

* with non-saturated transistors -

ECL

- Unipolar

* FET* NMOS, PMOS, CMOS

- Bipolar CMOS


- Cost of non-recurrent engineering, NRE

* Design and mask preparation

* Cost factor of one time action

- Cost of recurrent engineering

* Semiconductor manufacturing,

packaging and testing(i) Proportional to size

(ii) Proportional to IC area


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0,05 0,1 0,15 0,2 Process Geometry

(Micron)

0

1

2

3

Mask Costs(SM)

70nm ASICs will have $4MNRE

Exploding NRE / MaskCosts


0.00000010.000001

0.00001

0.0001

0.001

0.01

0.11

1982 1985 1988 1991 1994 1997 2000 2003 2006 2009 2012

cost:-per-transistor

Fabrication capital cost per transistor (Moores law)


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where Nt, Ng total number and number of yield ICs onone wafer respectively

CW, CD - wafer and die cost respectively

Dw wafer diameter, Addie area


MEMORY

DATAPATH

CONTROL

INPUT-OUTPUT

INPUT/OUTPUT


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Courtesy: Philips


EnergyEfficiency(inMOPS/mW)

Flexibility

(or application scope)

0.1-1

1-10

10-100

100-1000

None Fully

flexible

Somewhat

flexible

Hardwiredcustom

Config

urable/Parameterizable

Domain-specificprocessor

(e.g.

DSP)

Embeddedmicroprocessor


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Design process traverses iteratively between three abstractions:behavior, structure, and geometry

More and more automation for each of these steps


Custom

Standard CellsCompiled Cells Macro Cells

Cell-based

Pre-diffused(Gate Arrays)

Pre-wired(FPGA's)

Array-based

Semicustom

Digital Circuit Implementation Approaches


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Intel 4004

Courtesy Intel

Digital Integrated Circuits2nd Design MethodologiesCourtesy Intel


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Routing channel

requirements are

reduced by presence

of more interconnectlayers

Functionalmodule(RAM,multipl ier,)

Routingchannel

Logic cellFeedthrough cell


[Brodersen92]


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Cell-structure

hidden under

interconnect layers


3-input NAND cell

(from ST Microelectronics):C = Load capacitance

T = input rise/fall time


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Digital Integrated Circuits2nd Design MethodologiesCourtesy Acadabra

Initial transistor

geometries

Placed

transistors

Routed

cell

Compacted

cell

Finished

cell


x0 x1 x2

ANDplane

x0x1x2

Product terms

ORplane

f

0f

1


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Inverting format (NOR-

NOR) more effective

Every logic function can be

expressed in sum-of-products

format (AND-OR)

minterm


f0

f1

x0

x0

x1

x1

x2

x2

Pull-up devices Pull-up devices

VDD GNDAnd-Plane Or-Plane


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River PLAs A cascade of multiple-outputPLAs. Adjacent PLAs are connected via river routing.

PRE-CHARGE

PRE-

CHARGE

PRE-CHARGE

PRE-CHARGE

BUFFER

BUFFER

BUFFER

BUFFER

PRE-CHARGE

PRE-CHARGE

BUFFER

BUFFER

PRE-CHARGE

PRE-

CHARGE

BUFFER

BUFFER

No placement and routing needed. Output buffers and the input buffers

of the next stage are shared.

Courtesy B. Brayton


Layout of C2670

Network of PLAs,

4 layers OTC

River PLA,

2 layers no additional routing

Standard cell,

2 layers channel routing

Standard cell,

3 layers OTC

0.2

0.6

1

1.4

0 2 4 6 area

delay

SC NPLA RPLA

Area:RPLAs (2 layers) 1.23

SCs (3 layers) - 1.00,NPLAs (4 layers) 1.31

DelayRPLAs 1.04SCs 1.00

NPLAs 1.09Synthesis time: for RPLA , synthesis time equals design time;

SCs and NPLAs still need P&R.

Also: RPLAs are regular and predictable


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25632 (or 8192 bit) SRAMGenerated by hard-macro module generator

Digital Integrated Circuits2nd Design MethodologiesSynopsys DesignCompiler


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A Protocol Processor for Wireless


HDL

Logic Synthesis

Floorplanning

Placement

Routing

Tape-out

Circuit Extraction

Pre-Layout

Simulation

Post-Layout

Simulation

Design Capture


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Digital Integrated Circuits2nd Design MethodologiesCourtesy Synopsys

Iterative Removal of Timing Violations (white lines)


Physical Synthesis

RTL (Timing) Constraints

Place-and-Route

Optimization

Artwork

Netlist with

Place-and-Route Info

Macromodules

Fixed netlists


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Pre-diffused(Gate Arrays)

Pre-wired(FPGA's)

Array-based


rows of

cells

routing

channel

uncommitted

VDD

GND

polysilicon

metal

possiblecontact

In1 In2 In3 In4

Out

Uncommited

Cell

CommittedCell(4-input NOR)


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NMOS

PMOS

Oxide-isolation

PMOS

NMOS

NMOS

Using oxide-isolation Using gate-isolation

Digital Integrated Circuits2nd Design MethodologiesFrom Smith97


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Random Logic

Memory

Subsystem

LSI Logic LEA300K

(0.6 m CMOS)

Courtesy LSI Logic


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The imagecannot bedisplayed.Yourcomputermay not haveenoughmemory toopen theimage, or theimage may

The imagecannot bedisplayed.Yourcomputermay nothave enoughmemory toopen the

metal-5 metal-6

Via-programmable cross-point

programmable via

Via programmable gate array(VPGA)

[Pileggi02]

Exploits regularity of interconnect


Classification of prewired arrays (or field-

programmable devices):

Based on Programming Technique Fuse-based (program-once) Non-volatile EPROM based RAM based

Programmable Logic Style Array-Based Look-up Table

Programmable Interconnect Style Channel-routing Mesh networks


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antifuse polysilicon ONO dielectric

n+ antifuse diffusion

2l

From Smith97

Open by default, closed by applying current pulse


PLA PROM PAL

I5 I4

O0

I3 I2 I1 I0

O1O2O3Programmable AND array

ProgrammableOR array I5 I4

O0

I3 I2 I1 I0

O1O2O3Programmable AND array

Fixed OR array

Indicates programmable connectionIndicates fixed connection

O0

I3 I2 I1 I0

O1O2O3Fixed AND array

ProgrammableOR array


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f0

1 X2 X1 X0

f1NANA: programmed node


programmable AND array (2i 3 j k) k macrocells

j -wide OR array

j

macrocell

productterms

D Q

A

1

j

B

CLK

OUT

C i i inputs

i inputs, j minterms/macrocell, k macrocells


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F

A 0

B

S

1

Configuration

A B S F=

0 0 0 0

0 X 1 X

0 Y 1 Y

0 Y X XY

X 0 Y

Y 0 X

Y 1 X X1 Y

1 0 X

1 0 Y

1 1 1 1

XY

XY

X

Y


A

B

SA Y

1

C

D

SB

1

S0

S1

1


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Out

l n 1 l n 2

I n Out

00 00

01 1

10 1

11 0

Digital Integrated Circuits2nd Design MethodologiesCourtesy Xilinx

D4

C1....C4

xxxxxx

D3D2D1

F4F3F2F

1

Logicfunction

ofxxx

Logicfunction

ofxxx

Logicfunction

ofxxx

xx

xx

4

xxxxxx

xxxxxxxx

xxx

xxxx xxxx xxxx

HP

Bitscontrol

Bitscontrol

Multiplexer Controlledby Configuration Program

x

xx

x

xx

xxx xxxxxx

x

xxxxxx

xx

x

xx

xxx

xx

Xilinx 4000 Series

Figure must beupdated


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Input/output pinProgrammed interconnection

InterconnectPoint

Horizontaltracks

Vertical tracks

Cell

M


Switch Box

Connect Box

Interconnect

Point

Courtesy Dehon and Wawrzyniek


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Digital Integrated Circuits2nd Design MethodologiesCourtesy Dehon and Wawrzyniek


Use overlayed mesh

to support longer connections

Reduced fanout and reducedresistance

Courtesy Dehon and Wawrzyniek


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MacrocellPrimary inputs

Courtesy Altera



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LAB2

PIA

LAB1

LAB6

tPIA

tPIA

row channelcolumn channel

LAB

Courtesy Altera

Array-based

(MAX 3000-7000)

Mesh-based

(MAX 9000)


I/O Buffers

Program/Test/Diagnostics

I/O Buffers

I/OBuffers

I/OBuffers

Vertical routes

Rows of logic modulesRouting channels

Standard-cell like

floorplan


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2

12843

2

3

CLB

8 4 8 4

QuadSingleDoubleLong

DirectConnect

DirectConnect

Quad Long GlobalClock

Long Double Single GlobalClock

CarryChain

Long12 4 4

Courtesy Xilinx


Xilinx XC4000ex

Courtesy Xilinx


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Array Size: 8x8 (2 x 4LUT)

Power Supply: 1.5V &0.8V

Configuration: Mapped asRAM

Toggle Frequency:125MHz

Area: 3mm x 3mm


1-mm 2-metalCMOS tech

1.2 x 1.2 mm2 600k transistors 208-pin PGA fclock = 50 MHz

Pav = 3.6 W @ 5V Basic Module: Datapath

PADDI-2 (UC Berkeley)


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RAM

500 k Gates FPGA

+ 1 Gbit DRAM

Preprocessing

Multi-

Spectral

Imager

Csystem

+2 Gbit

DRAMRecog-

nition

Analog

64 SIMD Processor

Array + SRAM

Image Conditioning

100 GOPS

Embedded applicationswhere cost,performance,

and energy are the realissues!

DSP and control intensive Mixed-mode Combines programmable

and application-specific

modules

Software plays crucial role


Reuse comes in generations

Generation Reuse element Status1st Standard cells W ell established2nd IP blocks Being introduced3rd Architecture Emerging4th IC Early research

Source: Theo Claasen (Philips) DAC 00


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Silicon System Platform Flexible architecture for hardware and software Specific (programmable) components Network architecture Software modules Rules and guidelines for design of HW and SW

Has been successful in PCs Dominance of a few players who specify and control architecture

Application-domain specific (difference in constraints) Speed (compute power) Dissipation Costs Real / non-real time data


A platform is a restriction on the space of possible implementationchoices, providing a well-defined abstraction of the underlyingtechnology for the application developer

New platforms will be defined at the architecture-micro-architectureboundary

They will be component-based, and will provide a range of choicesfrom structured-custom to fully programmable implementations

Key to such approaches is the representation of communication inthe platform model

Source:R.Newton


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0.25um 6-level metal CMOS 5.2mm x 6.7mm1.2 Million transistors40 MHz at 1V2 extra supplies: 0.4V, 1.5V

1.5~2 mW power dissipationInterface

Reconfigurable

Data-path

FPGA

ARM8 Core


Xilinx Vertex-II Pro

Courtesy Xilinx

High-speed I/O

Embedded PowerPc

Embedded memories

Hardwired multipliers

FPGA Fabric


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Digital CMOS Design is kicking and healthy Some major challenges down the road

caused by Deep Sub-micron Super GHz design Power consumption!!!! Reliability making it workSome new circuit solutions are bound to emerge

Who can afford design in the years to come?Some major design methodology change inthe making!

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