chapter three - jordan university of science and technologyyahya-t/cs351/ch3.pdf · — conventions...
TRANSCRIPT
2©2004 Morgan Kaufmann Publishers
• Bits are just bits (no inherent meaning)— conventions define relationship between bits and numbers
• Binary numbers (base 2)0000 0001 0010 0011 0100 0101 0110 0111 1000 1001...decimal: 0...2n-1
• Of course it gets more complicated:numbers are finite (overflow)fractions and real numbersnegative numberse.g., no MIPS subi instruction; addi can add a negative number
• How do we represent negative numbers?i.e., which bit patterns will represent which numbers?
Numbers
3©2004 Morgan Kaufmann Publishers
• Sign Magnitude: One's Complement Two's Complement000 = +0 000 = +0 000 = +0001 = +1 001 = +1 001 = +1010 = +2 010 = +2 010 = +2011 = +3 011 = +3 011 = +3100 = -0 100 = -3 100 = -4101 = -1 101 = -2 101 = -3110 = -2 110 = -1 110 = -2111 = -3 111 = -0 111 = -1
• Issues: balance, number of zeros, ease of operations• Which one is best? Why?
Possible Representations
4©2004 Morgan Kaufmann Publishers
• 32 bit signed numbers:
0000 0000 0000 0000 0000 0000 0000 0000two = 0ten0000 0000 0000 0000 0000 0000 0000 0001two = + 1ten0000 0000 0000 0000 0000 0000 0000 0010two = + 2ten...0111 1111 1111 1111 1111 1111 1111 1110two = + 2,147,483,646ten0111 1111 1111 1111 1111 1111 1111 1111two = + 2,147,483,647ten1000 0000 0000 0000 0000 0000 0000 0000two = – 2,147,483,648ten1000 0000 0000 0000 0000 0000 0000 0001two = – 2,147,483,647ten1000 0000 0000 0000 0000 0000 0000 0010two = – 2,147,483,646ten...1111 1111 1111 1111 1111 1111 1111 1101two = – 3ten1111 1111 1111 1111 1111 1111 1111 1110two = – 2ten1111 1111 1111 1111 1111 1111 1111 1111two = – 1ten
maxint
minint
MIPS
5©2004 Morgan Kaufmann Publishers
• Negating a two's complement number: invert all bits and add 1
– remember: “negate” and “invert” are quite different!
• Converting n bit numbers into numbers with more than n bits:
– MIPS 16 bit immediate gets converted to 32 bits for arithmetic
– copy the most significant bit (the sign bit) into the other bits0010 -> 0000 0010
1010 -> 1111 1010
– "sign extension" (lbu vs. lb)
Two's Complement Operations
6©2004 Morgan Kaufmann Publishers
• Just like in grade school (carry/borrow 1s)0111 0111 0110
+ 0110 - 0110 - 0101
• Two's complement operations easy– subtraction using addition of negative numbers
0111+ 1010
• Overflow (result too large for finite computer word):– e.g., adding two n-bit numbers does not yield an n-bit number
0111+ 0001 note that overflow term is somewhat misleading,1000 it does not mean a carry “overflowed”
Addition & Subtraction
7©2004 Morgan Kaufmann Publishers
Arithmetic
• Where we've been:– Performance (seconds, cycles, instructions)
• What's up ahead:– Implementing the Architecture
32
32
32
operation
result
a
b
ALU
8©2004 Morgan Kaufmann Publishers
Constructing an ALU (Arithmetic Logic Unit)
• ALU is a device that performs the arithmetic operations like addition and subtraction, or logical operations like AND and OR.
• An ALU can be constructed from four hardware building blocks: AND gate, OR gate, Inverter, and Multiplexor. (What is the truth table of each?)
• The Multiplexor: If S == 0 then C = A else C = BSelects one of the inputs to be the output, based on a control input. S
CAB
01
9©2004 Morgan Kaufmann Publishers
• Let's build an ALU to support the andi and ori instructions– We'll just build a 1 bit ALU, and use 32 of
them because MIPS word is 32 bits wide
b
a
operation
result
op a b res
ALU (Cont.)
11©2004 Morgan Kaufmann Publishers
• Not easy to decide the “best” way to build something– Don't want too many inputs to a single gate– Don’t want to have to go through too many gates– for our purposes, ease of comprehension is important
• Let's look at a 1-bit ALU for addition:
• How could we build a 1-bit ALU for Add, AND, and OR?• How could we build a 32-bit ALU?
Different Implementations
S u m
C a r r y I n
C a r r y O u t
a
b
• A full adder or a (3,2) adder has three inputs (a, b, & Cin) and two outputs (Sum & Cout).
• A half adder or a (2,2) adder has only 2 inputs (a & b) and 2 outputs (Sum & Cout).
12©2004 Morgan Kaufmann Publishers
Input and Output Specification for 1-bit Adder
1111101011011011000101110100101010000000
SumCarryOutCarryInbaOutputsInputs
13©2004 Morgan Kaufmann Publishers
Values of the Inputs when CarryOut is a 1
• CarryOut = (b . CarryIn) + (a . CarryIn) + (a . b) + (a . b . CarryIn)• If a . b . CarryIn is true, then all of the other terms must be true,
so we leave out the last term.• cout = a b + a cin + b cin
111011101110
CarryInbaInputs
14©2004 Morgan Kaufmann Publishers
Adder Hardware for the Carry Out Signal
• The above Hardware was constructed from the following equation: CarryOut = (b . CarryIn) + (a . CarryIn) + (a . b)
CarryIn
a
b
CarryOut
15©2004 Morgan Kaufmann Publishers
The Sum bit
• The Sum bit is set to 1 when exactly one input is 1 or when all three inputs are 1.(check Truth Table on slide 7).
• Sum = (a . b’ . CarryIn’) + (a’ . b . CarryIn’) + (a’ . b’ . CarryIn) + (a . b . CarryIn)
• Sum = a XOR b XOR cin
• Draw the logic circuit? (Left as exercise).
16©2004 Morgan Kaufmann Publishers
A 1-bit ALU that Performs AND, OR, & Addition
b
0
2
R e s u lt
O p e ra t io n
a
1
C a r ry In
C a r ry O u t
17©2004 Morgan Kaufmann Publishers
A 32 bit ALU Constructed from 32 1-bit ALUs.
R e s u l t 3 1a 3 1
b 3 1
R e s u l t 0
C a r r y I n
a 0
b 0
R e s u l t 1a 1
b 1
R e s u l t 2a 2
b 2
O p e r a t i o n
A L U 0
C a r r y I n
C a r r y O u t
A L U 1
C a r r y I n
C a r r y O u t
A L U 2
C a r r y I n
C a r r y O u t
A L U 3 1
C a r r y I n
Ripple carry: CarryOut of the less significant bit is connected to the CarryIn of the more significant bit.
18©2004 Morgan Kaufmann Publishers
• Two's complement approach: just negate b and add.• How do we negate?
• A very clever solution:
What about subtraction (a – b) ?
0
2
Result
Operation
a
1
CarryIn
CarryOut
0
1
Binvert
b
19©2004 Morgan Kaufmann Publishers
• No overflow when adding a positive and a negative number• No overflow when signs are the same for subtraction• Overflow occurs when the value affects the sign:
– overflow when adding two positives yields a negative – or, adding two negatives gives a positive– or, subtract a negative from a positive and get a negative– or, subtract a positive from a negative and get a positive
• Consider the operations A + B, and A – B– Can overflow occur if B is 0 ?– Can overflow occur if A is 0 ?
Detecting Overflow
20©2004 Morgan Kaufmann Publishers
• An exception (interrupt) occurs– Control jumps to predefined address for exception– Interrupted address is saved for possible resumption
• Details based on software system / language– example: flight control vs. homework assignment
• Don't always want to detect overflow— new MIPS instructions: addu, addiu, subu
note: addiu still sign-extends!note: sltu, sltiu for unsigned comparisons
Effects of Overflow
21©2004 Morgan Kaufmann Publishers
• More complicated than addition– accomplished via shifting and addition
• More time and more area• Let's look at 3 versions based on grade school algorithm
1000 (multiplicand)__x_1001 (multiplier)
10000000
00001000
1001000 (Product)• If we ignore the sign bits, the length of the multiplication of
an n-bit multiplicand and an m-bit multiplier is a product that is n + m bits long.
• That is, n + m bits are required to represent all possible products.
Multiplication
22©2004 Morgan Kaufmann Publishers
Multiplication
• Each step of multiplication is simple:1. Just place a copy of the multiplicand
(1 x multiplicand) in the proper place if the multiplier digit is 1, or
2. Place 0 (0 x multiplicand) in the proper place if the digit is 0.
• Negative numbers: convert and multiply– there are better techniques, we won’t look at
them.
23©2004 Morgan Kaufmann Publishers
Multiplication: Implementation
DatapathControl
MultiplicandShift left
64 bits
64-bit ALU
ProductWrite
64 bits
Control test
MultiplierShift right
32 bits
32nd repetition?
1a. Add multiplicand to product andplace the result in Product register
Multiplier0 = 01. TestMultiplier0
Start
Multiplier0 = 1
2. Shift the Multiplicand register left 1 bit
3. Shift the Multiplier register right 1 bit
No: < 32 repetitions
Yes: 32 repetitions
Done
24©2004 Morgan Kaufmann Publishers
First Version of the Multiplication Hardware
• The Multiplicand register, ALU, and Product register are all 64 bits wide, with only the Multiplier register containing 32 bits.
• We will need to move the multiplicand left one digit each step as it may be added to the intermediate products. So, over 32 steps a 32-bit multiplicand would move 32 bits to the left. Hence we need a 64-bit Multiplicand register, initialized with the 32-bit multiplication in the right half and 0 in the left half.
• The multiplier is shifted in the opposite direction at each step.• The Product register initialized to 0.• Control decides when to shift the Multiplicand and Multiplier
registers and when to write new values into the Product register.
25©2004 Morgan Kaufmann Publishers
Final Version
Multiplicand
32 bits
32-bit ALU
ProductWrite
64 bits
Controltest
Shift right
32nd repetition?
Product0 = 01. TestProduct0
Start
Product0 = 1
3. Shift the Product register right 1 bit
No: < 32 repetitions
Yes: 32 repetitions
Done
What goes here?
•Multiplier starts in right half of product
26©2004 Morgan Kaufmann Publishers
Multiply in MIPS
• MIPS provides a separate pair of 32-bit registers to contain the 64-bit product, called Hi and Lo.
• To produce a properly signed or unsigned product, MIPS has two instructions: multiply (mult) and multiply unsigned (multu).
27©2004 Morgan Kaufmann Publishers
Floating Point (a brief look)
• We need a way to represent– numbers with fractions, e.g., 3.1416– very small numbers, e.g., .000000001– very large numbers, e.g., 3.15576 × 109
• Representation:– sign, exponent, significand: (–1)sign × significand × 2exponent
– more bits for significand gives more accuracy– more bits for exponent increases range
• IEEE 754 floating point standard: – single precision: 8 bit exponent, 23 bit significand– double precision: 11 bit exponent, 52 bit significand
28©2004 Morgan Kaufmann Publishers
IEEE 754 floating-point standard
• Leading “1” bit of significand is implicit
• Exponent is “biased” to make sorting easier– all 0s is smallest exponent all 1s is largest– bias of 127 for single precision and 1023 for double precision– summary: (–1)sign × (1+significand) × 2exponent – bias
• Example:
– decimal: -.75 = - ( ½ + ¼ )– binary: -.11 = -1.1 x 2-1
– floating point: exponent = 126 = 01111110
– IEEE single precision: 10111111010000000000000000000000
29©2004 Morgan Kaufmann Publishers
Floating point addition
•
Still normalized?
4. Round the significand to the appropriatenumber of bits
YesOverflow orunderflow?
Start
No
Yes
Done
1. Compare the exponents of the two numbers.Shift the smaller number to the right until itsexponent would match the larger exponent
2. Add the significands
3. Normalize the sum, either shifting right andincrementing the exponent or shifting left
and decrementing the exponent
No Exception
Small ALU
Exponentdifference
Control
ExponentSign Fraction
Big ALU
ExponentSign Fraction
0 1 0 1 0 1
Shift right
0 1 0 1
Increment ordecrement
Shift left or right
Rounding hardware
ExponentSign Fraction
30©2004 Morgan Kaufmann Publishers
Floating Point Complexities
• Operations are somewhat more complicated (see text)• In addition to overflow we can have “underflow”• Accuracy can be a big problem
– IEEE 754 keeps two extra bits, guard and round– four rounding modes– positive divided by zero yields “infinity”– zero divide by zero yields “not a number”– other complexities
• Implementing the standard can be tricky• Not using the standard can be even worse
– see text for description of 80x86 and Pentium bug!
31©2004 Morgan Kaufmann Publishers
Chapter Three Summary
• Computer arithmetic is constrained by limited precision• Bit patterns have no inherent meaning but standards do exist
– two’s complement– IEEE 754 floating point
• Computer instructions determine “meaning” of the bit patterns• Performance and accuracy are important so there are many
complexities in real machines • Algorithm choice is important and may lead to hardware
optimizations for both space and time (e.g., multiplication)
• You may want to look back (Section 3.10 is great reading!)