chapter 8: main memory

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Chapter 8: Main Chapter 8: Main MemoryMemory

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Chapter 8: Memory Chapter 8: Memory ManagementManagement

BackgroundBackground

Swapping Swapping

Contiguous Memory AllocationContiguous Memory Allocation

PagingPaging

Structure of the Page TableStructure of the Page Table

SegmentationSegmentation

Example: The Intel PentiumExample: The Intel Pentium

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ObjectivesObjectives

To provide a detailed description of various To provide a detailed description of various ways of organizing memory hardwareways of organizing memory hardware

To discuss various memory-management To discuss various memory-management techniques, including paging and segmentationtechniques, including paging and segmentation

To provide a detailed description of the Intel To provide a detailed description of the Intel Pentium, which supports both pure Pentium, which supports both pure segmentation and segmentation with pagingsegmentation and segmentation with paging

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BackgroundBackgroundA program must be brought (from disk) into A program must be brought (from disk) into memory and placed within a process for it to be runmemory and placed within a process for it to be run

Main memory and registers are the only storage Main memory and registers are the only storage CPU can access directlyCPU can access directly

Register access is in one CPU clock (or less)Register access is in one CPU clock (or less)

Main memory can take many cyclesMain memory can take many cycles

CacheCache sits between main memory and CPU sits between main memory and CPU registersregisters

Protection of memory required to ensure correct Protection of memory required to ensure correct operationoperation

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Base and Limit RegistersBase and Limit RegistersA pair of A pair of basebase andand limitlimit registers registers define the logical address spacedefine the logical address space

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Binding of Instructions and Data to MemoryBinding of Instructions and Data to MemoryAddress binding of instructions and data to memory Address binding of instructions and data to memory addresses can happen at three different stagesaddresses can happen at three different stages Compile timeCompile time:: If memory location known a priori, If memory location known a priori, absolute absolute

codecode can be generated; must recompile code if starting can be generated; must recompile code if starting location changeslocation changes

Load timeLoad time:: Must generate Must generate relocatable coderelocatable code if memory if memory location is not known at compile timelocation is not known at compile time

Execution timeExecution time:: Binding delayed until run time if the Binding delayed until run time if the process can be moved during its execution from one memory process can be moved during its execution from one memory segment to another. Need hardware support for address segment to another. Need hardware support for address maps (e.g., base and limitmaps (e.g., base and limit registers)registers)

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Multistep Processing of a User Multistep Processing of a User Program Program

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Logical vs. Physical Address SpaceLogical vs. Physical Address SpaceThe concept of a logical address space that is The concept of a logical address space that is bound to a separate bound to a separate physical address spacephysical address space is is central to proper memory managementcentral to proper memory management Logical addressLogical address – generated by the CPU; also – generated by the CPU; also

referred to as referred to as virtual addressvirtual address Physical addressPhysical address – address seen by the memory unit– address seen by the memory unit

Logical and physical addresses are the same in Logical and physical addresses are the same in compile-time and load-time address-binding compile-time and load-time address-binding schemes; logical (virtual) and physical addresses schemes; logical (virtual) and physical addresses differ in execution-time address-binding schemediffer in execution-time address-binding scheme

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Memory-Management Unit (Memory-Management Unit (MMUMMU))

Hardware device that maps virtual to physical Hardware device that maps virtual to physical addressaddress

In MMU scheme, the value in the relocation In MMU scheme, the value in the relocation register is added to every address generated by register is added to every address generated by a user process at the time it is sent to memorya user process at the time it is sent to memory

The user program deals with The user program deals with logicallogical addresses; addresses; it never sees the it never sees the realreal physical addresses physical addresses

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Dynamic Relocation Using a Dynamic Relocation Using a Relocation RegisterRelocation Register

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Dynamic LoadingDynamic LoadingRoutine is not loaded until it is calledRoutine is not loaded until it is called

Better memory-space utilization; Better memory-space utilization; unused routine is never loadedunused routine is never loaded

Useful when large amounts of code are Useful when large amounts of code are needed to handle infrequently needed to handle infrequently occurring casesoccurring cases

No special support from the operating No special support from the operating system is required - implemented system is required - implemented through program designthrough program design

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Dynamic LinkingDynamic LinkingLinking postponed until execution timeLinking postponed until execution time

Small piece of code, Small piece of code, stubstub, used to locate the , used to locate the appropriate memory-resident library routineappropriate memory-resident library routine

Stub replaces itself with the address of the Stub replaces itself with the address of the routine, and executes the routineroutine, and executes the routine

Operating system needed to check if routine is in Operating system needed to check if routine is in processes’ memory addressprocesses’ memory address

Dynamic linking is particularly useful for librariesDynamic linking is particularly useful for libraries

System also known as System also known as shared librariesshared libraries

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Swapping Swapping


PagingPaging




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SwappingSwappingA process can be swapped temporarily out of A process can be swapped temporarily out of memory to a backing store, and then brought back memory to a backing store, and then brought back into memory for continued executioninto memory for continued execution

Backing storeBacking store – fast disk large enough to – fast disk large enough to accommodate copies of all memory images for all accommodate copies of all memory images for all users; must provide direct access to these users; must provide direct access to these memory imagesmemory images

Roll out, roll inRoll out, roll in – swapping variant used for – swapping variant used for priority-based scheduling algorithms; lower-priority priority-based scheduling algorithms; lower-priority process is swapped out so higher-priority process process is swapped out so higher-priority process can be loaded and executedcan be loaded and executed

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SwappingSwapping

Major part of swap time is transfer time; Major part of swap time is transfer time; total transfer time is directly proportional to total transfer time is directly proportional to the amount of memory swappedthe amount of memory swapped

Modified versions of swapping are found Modified versions of swapping are found on many systems (i.e., UNIX, Linux, and on many systems (i.e., UNIX, Linux, and Windows)Windows)

System maintains a System maintains a ready queueready queue of of ready-to-run processes which have ready-to-run processes which have memory images on diskmemory images on disk

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Schematic View of SwappingSchematic View of Swapping

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Swapping Swapping


PagingPaging




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Contiguous AllocationContiguous Allocation

Main memory usually is separated into two Main memory usually is separated into two partitions:partitions: Resident operating system, usually held Resident operating system, usually held

in low memory with interrupt vectorin low memory with interrupt vector User processes then held in high User processes then held in high

memorymemory

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Contiguous AllocationContiguous Allocation

Relocation registers are used to protect Relocation registers are used to protect user processes from each other, and from user processes from each other, and from changing operating-system code and datachanging operating-system code and data A base register contains the value of A base register contains the value of

smallest physical addresssmallest physical address A limit register contains the range of A limit register contains the range of

logical addresses – each logical address logical addresses – each logical address must be less than the limit register must be less than the limit register

MMU maps logical address MMU maps logical address dynamicallydynamically

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Hardware Support for Relocation and Hardware Support for Relocation and Limit RegistersLimit Registers

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Contiguous Allocation (Cont)Contiguous Allocation (Cont)Multiple-partition allocationMultiple-partition allocation HoleHole – a block of available memory; holes of – a block of available memory; holes of

various size are scattered throughout memoryvarious size are scattered throughout memory When a process arrives, it is allocated When a process arrives, it is allocated

memory from a hole large enough to memory from a hole large enough to accommodate itaccommodate it

The operating system maintains information The operating system maintains information about:about:a) allocated partitions a) allocated partitions

b) free partitions (hole)b) free partitions (hole)

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Contiguous Allocation (Cont)Contiguous Allocation (Cont)

OS

process 5

process 8

process 2

OS

process 5

process 2

OS

process 5

process 2

OS

process 5

process 9

process 2

process 9

process 10

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Dynamic Storage-Allocation ProblemDynamic Storage-Allocation Problem

First-fitFirst-fit: Allocate the : Allocate the firstfirst hole that is big enough hole that is big enoughBest-fitBest-fit:: Allocate the Allocate the smallestsmallest hole that is big enough; hole that is big enough; must search entire list, unless ordered by size must search entire list, unless ordered by size Produces the smallest leftover holeProduces the smallest leftover hole

Worst-fitWorst-fit:: Allocate the Allocate the largestlargest hole; must also search hole; must also search entire list entire list Produces the largest leftover holeProduces the largest leftover hole

How to satisfy a request of size n from a list

of free holes

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Dynamic Storage-Allocation Dynamic Storage-Allocation ProblemProblem

First-fit and best-fit work better than worst-fit in terms of speed and storage utilization

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FragmentationFragmentation

External FragmentationExternal Fragmentation – total memory space – total memory space exists to satisfy a request, but it is not exists to satisfy a request, but it is not contiguouscontiguous

Internal FragmentationInternal Fragmentation – allocated memory – allocated memory may be slightly larger than requested memory; may be slightly larger than requested memory; this size difference is memory internal to a this size difference is memory internal to a partition, but not being usedpartition, but not being used

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FragmentationFragmentation

Reduce external fragmentation by Reduce external fragmentation by compactioncompaction Shuffle memory contents to place all free Shuffle memory contents to place all free

memory together in one large blockmemory together in one large block Compaction is possible Compaction is possible onlyonly if relocation is if relocation is

dynamic, and is done at execution timedynamic, and is done at execution time I/O problemI/O problem

Latch job in memory while it is involved in I/OLatch job in memory while it is involved in I/O

Do I/O only into OS buffersDo I/O only into OS buffers

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Swapping Swapping


PagingPaging




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PagingPaging

Logical address space of a process can be Logical address space of a process can be noncontiguous; process is allocated physical noncontiguous; process is allocated physical memory whenever the latter is availablememory whenever the latter is available

Divide physical memory into fixed-sized blocks Divide physical memory into fixed-sized blocks called called framesframes (size is power of 2, between 512 (size is power of 2, between 512 bytes and 8,192 bytes)bytes and 8,192 bytes)

Divide logical memory into blocks of same size Divide logical memory into blocks of same size called called pagespages

Keep track of all free framesKeep track of all free frames

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PagingPaging

To run a program of size To run a program of size nn pages, need to pages, need to find find nn free frames and load program free frames and load program

Set up a page table to translate logical to Set up a page table to translate logical to physical addressesphysical addresses

Internal fragmentationInternal fragmentation

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Address Translation SchemeAddress Translation SchemeAddress generated by CPU is divided into:Address generated by CPU is divided into: Page number (Page number (pp)) – used as an index into a – used as an index into a pagepage tabletable which contains which contains

base address of each page in physical memorybase address of each page in physical memory

Page offset (d)Page offset (d) – combined with base address to define the physical – combined with base address to define the physical memory address that is sent to the memory unitmemory address that is sent to the memory unit

For given logical address space 2For given logical address space 2m m and page sizeand page size 22nn

page number page offset

p dm - n n

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Paging HardwarePaging Hardware

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Paging Model of Logical and Paging Model of Logical and Physical MemoryPhysical Memory

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Paging ExamplePaging Example

32-byte memory and 4-byte pages

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Free FramesFree Frames

Before allocation After allocation

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Implementation of Page TableImplementation of Page Table

Page table is kept in main memoryPage table is kept in main memory

Page-table base register (PTBR)Page-table base register (PTBR) points to the points to the page tablepage table

Page-table length register (PRLR)Page-table length register (PRLR) indicates indicates size of the page tablesize of the page table

In this scheme every data/instruction access In this scheme every data/instruction access requires two memory accesses. One for the requires two memory accesses. One for the page table and one for the data/instruction.page table and one for the data/instruction.

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Implementation of Page TableImplementation of Page Table

The two memory access problem can be The two memory access problem can be solved by the use of a special fast-lookup solved by the use of a special fast-lookup hardware cache called hardware cache called associative associative memorymemory or or translation look-aside translation look-aside buffers (TLBs)buffers (TLBs)

Some TLBs storeSome TLBs store address-space address-space identifiers (ASIDs)identifiers (ASIDs) in each TLB entry – in each TLB entry – uniquely identifies each process to provide uniquely identifies each process to provide address-space protection for that processaddress-space protection for that process

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Associative MemoryAssociative MemoryAssociative memory – parallel search Associative memory – parallel search

Address translation (p, d)Address translation (p, d) If p is in associative register, get frame # outIf p is in associative register, get frame # out Otherwise get frame # from page table in Otherwise get frame # from page table in

memorymemory

Page # Frame #

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Paging Hardware With TLBPaging Hardware With TLB

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Effective Access TimeEffective Access TimeAssociative Lookup = Associative Lookup = time unit time unit

Assume memory cycle time is 1 microsecondAssume memory cycle time is 1 microsecond

Hit ratioHit ratio – percentage of times that a page – percentage of times that a page number is found in the associative registers; ratio number is found in the associative registers; ratio related to number of associative registersrelated to number of associative registers

Hit ratio = Hit ratio = Effective Access TimeEffective Access Time (EAT)(EAT)

EAT = (1 + EAT = (1 + ) ) + (2 + + (2 + )(1 – )(1 – ))

= 2 + = 2 + – –

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Memory ProtectionMemory ProtectionMemory protection implemented by associating Memory protection implemented by associating protection bit with each frameprotection bit with each frame

Valid-invalidValid-invalid bit attached to each entry in the bit attached to each entry in the page table:page table: ““valid” indicates that the associated page is in valid” indicates that the associated page is in

the process’ logical address space, and is thus the process’ logical address space, and is thus a legal pagea legal page

““invalid” indicates that the page is not in the invalid” indicates that the page is not in the process’ logical address spaceprocess’ logical address space

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Valid (v) or Invalid (i) Bit In A Page Valid (v) or Invalid (i) Bit In A Page TableTable

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Shared PagesShared Pages

Shared codeShared code One copy of read-only (One copy of read-only (reentrantreentrant) code ) code

shared among processes (i.e., text editors, shared among processes (i.e., text editors, compilers, window systems).compilers, window systems).

Shared code must appear in same location Shared code must appear in same location in the logical address space of all processesin the logical address space of all processes

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Shared PagesShared Pages

Private code and dataPrivate code and data Each process keeps a separate copy of Each process keeps a separate copy of

the code and datathe code and data The pages for the private code and data The pages for the private code and data

can appear anywhere in the logical can appear anywhere in the logical address spaceaddress space

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Shared Pages ExampleShared Pages Example

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Swapping Swapping


PagingPaging




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Structure of the Page TableStructure of the Page TableHierarchical PagingHierarchical Paging

Hashed Page TablesHashed Page Tables

Inverted Page TablesInverted Page Tables

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Hierarchical Page TablesHierarchical Page TablesBreak up the logical address space Break up the logical address space into multiple page tablesinto multiple page tables

A simple technique is a two-level A simple technique is a two-level page tablepage table

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Two-Level Page-Table SchemeTwo-Level Page-Table Scheme

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Two-Level Paging ExampleTwo-Level Paging ExampleA logical address (on 32-bit machine with 1K page size) A logical address (on 32-bit machine with 1K page size) is divided into:is divided into: a page number consisting of 22 bitsa page number consisting of 22 bits a page offset consisting of 10 bitsa page offset consisting of 10 bitsSince the page table is paged, the page number is Since the page table is paged, the page number is further divided into:further divided into: a 12-bit page number a 12-bit page number a 10-bit page offseta 10-bit page offset

wherewhere p p1 is an index into the outer page table, and 1 is an index into the outer page table, and p2p2 is the is the displacement within the page of the outer page tabledisplacement within the page of the outer page table

page #page # page offsetpage offset

p1 - 12 bitsp1 - 12 bits p2 - 10 bitsp2 - 10 bits d - 10 bitsd - 10 bits

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Address-Translation SchemeAddress-Translation Scheme

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Three-level Paging SchemeThree-level Paging Scheme

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Hashed Page TablesHashed Page Tables

Common in address spaces > 32 bitsCommon in address spaces > 32 bits

The virtual page number is hashed into a page The virtual page number is hashed into a page tabletable This page table contains a chain of elements This page table contains a chain of elements

hashing to the same locationhashing to the same location

Virtual page numbers are compared in this chain Virtual page numbers are compared in this chain searching for a matchsearching for a match If a match is found, the corresponding physical If a match is found, the corresponding physical

frame is extractedframe is extracted

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Hashed Page TableHashed Page Table

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Inverted Page TableInverted Page TableOne entry for each real page of memoryOne entry for each real page of memory

Entry consists of the virtual address of the page Entry consists of the virtual address of the page stored in that real memory location, with stored in that real memory location, with information about the process that owns that information about the process that owns that pagepage

Decreases memory needed to store each page Decreases memory needed to store each page table, but increases time needed to search the table, but increases time needed to search the table when a page reference occurstable when a page reference occurs

Use hash table to limit the search to one — or Use hash table to limit the search to one — or at most a few — page-table entriesat most a few — page-table entries

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Inverted Page Table Inverted Page Table ArchitectureArchitecture

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Swapping Swapping


PagingPaging




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Memory-management scheme that supports Memory-management scheme that supports user view of memory user view of memory A program is a collection of A program is a collection of segmentssegments A segment is a logical unit such as:A segment is a logical unit such as:

main program procedure main program procedure function methodfunction methodobject local variablesobject local variables

global variables common blockglobal variables common blockstack symbol tablestack symbol tablearraysarrays

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User’s View of a ProgramUser’s View of a Program

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Logical View of SegmentationLogical View of Segmentation

1

3

2

4

1

4

2

3

user space physical memory space

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Segmentation Architecture Segmentation Architecture Logical address consists of a two tuple:Logical address consists of a two tuple:

<segment-number, offset>,<segment-number, offset>,Segment tableSegment table – maps two-dimensional physical addresses; – maps two-dimensional physical addresses; each table entry has:each table entry has: basebase – contains the starting physical address where the – contains the starting physical address where the

segments reside in memorysegments reside in memory limitlimit – specifies the length of the segment– specifies the length of the segment

Segment-table base register (STBR)Segment-table base register (STBR) points to the segment points to the segment table’s location in memorytable’s location in memory

Segment-table length register (STLR)Segment-table length register (STLR) indicates number of indicates number of segments used by a program;segments used by a program;

a segment number a segment number ss is legal if is legal if ss < < STLRSTLR

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Segmentation Architecture Segmentation Architecture ProtectionProtection With each entry in segment table associate:With each entry in segment table associate:

validation bit = 0 validation bit = 0 illegal segment illegal segment

read/write/execute privilegesread/write/execute privileges

Protection bits associated with segments; code Protection bits associated with segments; code sharing occurs at segment levelsharing occurs at segment level

Since segments vary in length, memory allocation is Since segments vary in length, memory allocation is a dynamic storage-allocation problema dynamic storage-allocation problem

A segmentation example is shown in the following A segmentation example is shown in the following diagramdiagram

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Segmentation HardwareSegmentation Hardware

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Example of SegmentationExample of Segmentation

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Swapping Swapping


PagingPaging




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Example: The Intel PentiumExample: The Intel PentiumSupports both segmentation and segmentation Supports both segmentation and segmentation with pagingwith paging

CPU generates logical addressCPU generates logical address Given to segmentation unitGiven to segmentation unit

Which produces linear addresses Which produces linear addresses Linear address given to paging unitLinear address given to paging unit

Which generates physical address in main Which generates physical address in main memorymemory

Paging units form equivalent of MMUPaging units form equivalent of MMU

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Logical to Physical Address Logical to Physical Address Translation in PentiumTranslation in Pentium

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Intel Pentium SegmentationIntel Pentium Segmentation

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Pentium Paging ArchitecturePentium Paging Architecture

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Linear Address in LinuxLinear Address in LinuxBroken into four parts:

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Three-level Paging in LinuxThree-level Paging in Linux

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End of Chapter 8End of Chapter 8

chapter 8: main memory

Documents

memory addresses

memory location

memory unitlogical

lessmain memory

runmain memory

memory segment

address maps

logical address space