Chapter 4 -- Modular Combinational Logic

L S B

M S B

D eco d e rn - to -2 n

x 0

x 1

y 0

y 1

x n-1y 2n -1

Decoders

m 0

m 1

m 2

m 3

(a ) (b )

(c )

L S B A

M S B Bm 0

m 1

m 2

m 3

m 1

m 0

m 2

m 3

L S B A

M S B B

L S B A

M S B B

Decoder Realization

C AB

(a )

(b )

(c )

m 0 = C B A

m 1 = C B A

m 2 = C B A

m 3 = C B A

m 5 = C B A

m 4 = C B A

m 6 = C B A

m 7 = C B A

B

BA

A

m 0

m 1

m 2

m 3

m 4

m 5

m 6

m 7

C

D

ABL S B

M S B

k0

k1

k2

k3

m 0

m 4

m 8

m 1 2

2 -to -4

A

AA

A

A

AB

B

C

C

m 1

m 5

m 9

m 1 3

m 2

m 6

m 1 0

m 1 4

m 3

m 7

m 11

m 1 5

l0 l3l1

l2

2 -to -4

More complex decoders

P

X

Q

(a ) (b )

A

B

C f(Q , X , P )

0

1

2

3

4

5

6

7

P

X

Q

A

B

C f(Q , X , P )

0

1

2

3

4

5

6

7

Example 4.1 -- Realize f(Q,X,P) = m(0,1,4,6,7) = M(2,3,5)

(c ) (d )

f(Q , X , P )

A

B

C f(Q , X , P )

0

1

2

3

4

5

6

7

P

X

Q

A

B

C

0

1

2

3

4

5

6

7

P

X

Q

Example 4.1 (concluded)

SN 74138 Decoder Module

1 6 1 5 1 4 1 3 1 2 11 1 0 9

(a )

G 1

A

B

C

(1 )

(2 )

(3 )

(4 )

(5 )

(6 )

G 2 AG 2 B

(1 5 )

(1 4 )

(1 3 )

(1 2 )

(1 1 )

(1 0 )

(9 )

(7 )

Y 0

Y 1

Y 2

Y 3

Y 4

Y 5

Y 6

Y 7

A

B

C

G 1

G 2 A

G 2 B

0

1

2

3

4

5

6

7

HHHHHHHHL

LLLLLLLLH´

LLLLHHHH

LLHHLLHH

LHLHLHLH

LHHHHHHHHH

HLHHHHHHHH

HHLHHHHHHH

HHHLHHHHHH

HHHHLHHHHH

HHHHHLHHHH

HHHHHHLHHH

HHH

HH

HHLHH

E n ab le S e lec t

O u tp u ts

G 1 G 2 * ABC Y 0 Y 1 Y 2 Y 3 Y 4 Y 5 Y 6 Y 7

In p u ts

(c )

S e lec t E n ab le

B

V cc Y 0 Y 1 Y 2 Y 3 Y 4 Y 5

A C G 2 BG 2 A G 1

7654321

Y 7O u tp u t

Y 6

8

G N D

Y 0 Y 1 Y 2 Y 3 Y 4 Y 5

Y 6

B C G 2 A G 2 B G 1 Y 7

A

D atao u tp u ts

(b )

(d ) (e )

1

2

3

01234567

(1 )

(2 )

(3 )

(6 )

(4 )

(5 )

'1 3 8B IN /O C T

E N

A

B

C

G 1

G 2 A

G 2 B

&

(1 5 )

(1 4 )

(1 3 )

(1 2 )

(1 1 )

(1 0 )

(9 )

(7 )

Y 0

Y 1

Y 2

Y 3

Y 4

Y 5

Y 6

Y 7G 2 * = G 2 A + G 2 B

(a )

Y4 -to -1

M u ltip le x e r

Y

B A

B

0011

A

0101

(b )

(c )

0 1 2 3

2 -to -4D e co d e r

D 0

D 1

D 2

D 3

Y

D 0D 1D 2D 3

D 0

D 1

D 2

D 3

B A

Y

(d )

D 0

D 1

D 2

D 3

B A

S elec t io n co d e

Four-to-one multiplexer design

(a )

(b )

V C C

C AB Yfx 1 x 3x 2

x 1 x 3x 2

01234567

00001111

00110011

01010101

10110100

D 0 = 1D 1 = 0D 2 = 1D 3 = 1D 4 = 0D 5 = 1D 6 = 0D 7 = 0

C B A

YW

7 4 1 5 1 A

f(x 1 , x 2, x 3)

i D 0D 1D 2D 3D 4D 5D 6D 7G

S e lec tio n co d e

Use a 74151A multiplexer to Realizef(x1,x2,x3) = m(0,2,3,5)

Figure 4.30

Half Adders

H A

(a )

(b )

(c )

x i y i

x i y i

c i s i

c i s i

0011

0101

0001

0110

y i

x i

s i

c i

Figure 4.35 (a) -- (c)

Full Adders

(d )(e )

(f)

(g )

x i y i c i-1

00001111

00110011

01010101

00010111

01101001

c i s i

F A

x i y i

c i s i

c i-1

s i

c i

c i-1

y i

x i

c i-1

y i

x i

s i

Figure 4.35 (d) -- (g)

Ripple Carry Adder

y n-1 c 1x 1 y 1 c 0 x 0 y 0

z 1 z0

c n-1

zn-1

(e n d ca rry )

F A H A

c n-2x n-1

F A

zn

Figure 4.36

Addition Time for a Basic Ripple-Carry Adder

Let tgate = the propogation delay through a typical logic gate

Half adder propagation delays tadd = 3 tgate

tcarry = 2 tgate

Full adder propagation delaystadd = 3 tgate

tcarry = 2 tgate

Ripple-Carry Adder (n-bits) tadd = (n - 1)2 tgate + 3 tgate = (2n + 1) tgate

SN7482 Two-Bit Pseudo Parallel Adder Module

1 4 1 3 1 2 11 1 0 9 8

7654321

A 2 B 2 S 2 G N D N C N CC 2

A 2B 2 S 2

S 1A 1 B 1 C 0

(a )A 1 B 1S 1 V C C N C N CC 0

C 2

Package Pin Configuration

SN7482 Pseudo Parallel Adder -- Truth Table

A 2 A 1 C 2 S 2 S 1

LLLLLLLLHHHHHHHH

LLLLHHHHLLLLHHHH

LLHHLLHHLLHHLLHH

LHLHLHLHLHLHLHLH

LLLLLLLHLLHHLHHH

LLHHLHHLHHLLHLLH

LHLHHLHLLHLHHLHL

LLLHLLHHLHHHHHHH

LHHLHHLLHLLHLLHH

HLHLLHLHHLHLLHLH

B 2 B 1 C 2 S 2 S 1

W h en C 0 = HW h en C 0 = L

O u tp u tsIn p u ts

(b )

SN7482 Pseudo Parallel Adder -- Logic DiagramC 0

A 1

B 1

A 2

B 2

C 1

C 2

S 2

S 1

(c )

SN7482 Two-Bit Adder -- Logic Equations

C1 = C0A1 + C0B1 + A1B1 (4.20)

1 = C0C1 + A1C1 + B1C1 + A1B1C0 = C1(C0 + A1 + B1) + A1B1C0 = (C0+A1)(C0+B1)(A1+B1) (C0 +A1+B1) +A1B1C0 = (C0+ A1B1)(A1+B1)(C0 +A1+B1) +A1B1C0 (4.21) = [C0(A1+B1)+ C0A1B1](A1+B1)+A1B1C0 = C0A1B1+C0A1B1+C0A1B1+A1B1C0 = C0 A1 B1

Similarly

C2 = C1A2 + C1B2 + A2B2 (4.22)

2 = C1 A2 B2

Add Time for SN7482 Adder Circuits

SN7482 propagation delays

t1 = 5 tgate

tC1 = 2 tgate

t2 = 6 tgate

tC2 = 4 tgate

SN7482-based ripple-carry adder (n-bits)

tadd = (2n + 2) tgate

SN7483 Four-Bit Adder Module

1 6 1 5 1 4 1 3 1 2 11 1 0

7654321

9

8

B 4 S 4 C 4 G N DC 0

V C C

A 1B 1 S 1

A 3 S 2 A 2B 2S 3

(a )

B 3A 4

S 4 C 4 C 0 A 1B 1

A 3 S 2 B 2S 3 B 3

S 1

A 2A 4

B 4

Package Pin Configuration

SN7483 Four-Bit Adder Module -- Logic Diagram

B 4

S 4

C 4

A 4

B 3

A 3

B 2

A 2

B 1

A 1

C 0

P 4

S 3

C 3

P 3

S 2

C 2

P 2

S 1

C 1

P 1

C 0

(b )

SN7483 Four-Bit Adder -- Logic Equations

Pi = (BiAi)(Ai + Bi) = (Ai + Bi)(Ai + Bi) = Ai Bi (4.24)

i = Pi Ci-1 = Ai Bi Ci-1 (4.25)

C1 = [C0(A1B1) + (A1 + B1)] = [C0(A1B1)](A1 + B1) = (C0+(A1B1))(A1 + B1) = C0A1 + C0B1 + A1B1 (4.26)

Similarly

Ci = Ci-1Ai + Ci-1Bi + AiBi

Add Times for SN7483 Adder Circuits

SN7483 propagation delays

t1 = 3 tgate

t2 = t3 = t4 = 4 tgate tC1 = tC2 = tC3 = tC4 = 3 tgate

SN7483-based Ripple-Carry Adder (n-bits)

tadd = (3m + 1) tgate

where m = n/4.

Fully Parallel Three-Bit Adder c0 = x0y0 (4.30) s0 = x0 y0

c1 = x1y1c0’+x1y1c0+x1y1’c0+x1’y1c0

= x1y1+(x1y1)c0

= x1y1+(x1y1)(x0y0) (4.31)s1 = x1y1c0

= x1y1 x0y0

c2 = x2y2+(x2y2)c1

= x2y2+(x2y2)[x1y1+(x1y1)(x0y0)] = x2y2+(x2y2)(x1y1)+(x2y2)(x1y1)(x0y0) (4.32)s2 = x2y2c1

= x2y2[x1y1+(x1y1)(x0y0)]

Add Time for a Fully Parallel Adder

Assuming a three-level realization

tadd = 3 tgate

However, the fan in requirements become impractical as n increases.

Carry Look-Ahead Adders -- Basic Idea

Recall that ci = xiyi + xici-1 + yici-1

= xiyi + xiyici-1 + xiyici-1 + xiyici-1 + xi yici-1

= xiyi + xiyici-1 + xi yici-1

= xiyi + (xiyi + xi yi)ci-1

= xiyi + (xi yi)ci-1

Let gi = xiyi [carry generate] (4.33)

pi = xi yi [carry propagate] (4.34)

Then ci = gi + pi ci-1

si = pi ci-1 (4.38)

Carry Look-Ahead Adders -- Three-Bit Example

c0 = g0 (4.35)s0 = p0

c1 = g1 + p1c0

= g1 + p1g0 (4.36)s1 = p1 c0

c2 = g2 + p2c1

= g2 + p2(g1 + p1g0) = g2 + p2g1 + p2p1g0 (4.37)s2 = p2 c1

Carry Look-Ahead Adder Design

(a ) (b )

x i y i c i

g i p i s i

g 2 p 2 g 1 p 1 g 0

c 1 c 0

x 2 y 2

g 2 s 2

c 2 c 1 c 0

p 2 g 1 s1p 1 g 0 s 0

p 0

x 1 y 1 x 0 y 0 0

c 2

A d d er

C L A circu it

A d d er A d d er

(c)

Figure 4.39

Add Times for Carry Look-Ahead Adders

Adder modules

tg = tp = ts = tgate

CLA module

tc = 2 tgate

Overall

tadd = tgate + 2 tgate + tgate

= 4 tgate

Binary Subtraction Circuits

Recall that (R)2 = (P)2 - (Q)2

= (P)2 + (-Q)2

= (P)2 + [Q]2

= (P)2 + (Q)2 + 1

For an SN7483 adder

()2 = (A)2 + (B)2 + (C0)2 (4.39)

where = 4321, A = A4A3A2A1, and B = B4B3B2B1

If C0 = 0, A = P, and B = Q, then ()2 = (P)2 + (Q)2 .

If C0 = 1, A = P, and B = Q, then ()2 = (P)2 - (Q)2 .

Two’s Complement Adder/SubtracterQ = (q 3 q 2 q 1 q 0)2

P = (p 3 p 2 p 1 p 0) 2

4 A 3 A 2 A 1 B4 B 2 B3 BSG

C 0C 4

S e lec t

R = (r 4 r 3 r 2 r 1)2

R = P + Q

R = P + Q + 1

0

1

S elec t F u n c tio n

1 A

1 Y2 Y3 Y4 Y

A 4 A 3 A 2 A 1 B 4 B 3 B 2 B 1

S 4 S 3 S 2 S 1

M U X (7 4 1 5 7 )

A D D E R (7 4 8 3 )

Figure 4.41

Arithmetic Overflow Detection

an-1 bn-1 cn-2 cn-1 sn-1 V

0 0 0 0 0 00 0 1 0 1 10 1 0 0 1 00 1 1 1 0 01 0 0 0 1 01 0 1 1 0 01 1 0 1 0 11 1 1 1 1 0

Overflow Detection Circuits

(a )

(b )

F A

a n -1 b n -1 a n -2 b n -2

c n -2c n -1

s n -1 s n -2

V

c n -3F A

F A

a n -1 b n -1 a n -2 b n -2

c n -2

c n -1

s n -1 s n -2

V

c n -3F A

Figure 4.42