CHAPTER 30HOT AIR LEVELING

Sherry GoodellTeledyne Electronic Technologies, Halco

Londonderry, New Hampshire

30. 1 INTRODUCTION

Hot air solder leveling (HAL) is a reliable technique for ensuring printed wiring board (PWB)solderability during fabrication and through assembly. HAL provides protection of solderablesurfaces from corrosion and contamination with the application of eutectic solder (SnPb) oralternative solder compositions (no lead) to the exposed solderable surface on a PWB. HALprovides protection of the entire copper surface of a panel or selective areas for product typessuch as solder mask over bare copper (SMOBC). With SMOBC product, solder mask coverscopper surfaces not requiring solder connections at assembly and leaves solderable sitesexposed. Typical shelf life for PWBs coated with HAL is 12 months under normal storageconditions.

30.2 HISTORY

HAL has existed in various forms since the mid 1970s. Several beneficial features of HAL areexcellent shelf life, shorter solder wetting times at assembly, high mechanical durability, and theformation of an intermetallic bond prior to the PWB assembly process. HAL as we know ittoday has evolved from early processes known as roll tinning whereby a very thin layer ofsolder was transferred to the panel from hot tinned rolls. This was followed by early verticalprocesses that typically immersed PWBs vertically into a molten solder pot before the excesssolder was removed with high-pressure air. The vertical process has been refined over the yearsand has overcome many of its initial problems of cosmetics and blocked holes. Horizontal HALwas introduced in the late 1970s and by the mid 1980s offered many benefits and increasedcapabilities over the vertical processes. The 1990s have continued to be a time of PWBdevelopment requiring improved process capability. Fine-pitch products from 0.015 to 0.050 in(0.4 to 1.25 mm) have challenged the process, with very acceptable results being achieved.Current challenges include 0.008 to 0.01 in (0.2 to 0.25 mm) pitch features. Horizontal HALhas addressed concerns related to vertical HAL. These include improved solder thicknesscontrol, uniformity, reduced thermal shock, reduced copper dissolution, and a reducedintermetallic compound (IMC) layer.

30.3 PROCESS FLOW

Panels presented for HAL typically have solder mask applied over the surface of all areas of thePWB that will not receive solder; that is, conductors, ground shields, and other areasnonessential for component assembly. If the entire panel requires solder, there will be no solder

mask applied before HAL. This is the exception rather than the rule. The process flow at HALconsists of a preclean cycle, preheating, flux coating, solder coating, leveling with hot air knives,cooling, and a postclean section (Figs. 30.1 through 30.3). The vertical and horizontalprocesses are essentially the same sequence, except the vertical process is usually not an in-lineprocess and may not include the preheat and cool-down sections.

FIGURE 30.1 Process flow

Conveyor direction

30.3.1 Preclean

The Preclean employs a microetch, water rinse, and hot air dry. Some lines have an additionalacid rinse following the microetch chamber, prior to the water rinse. The microetch is typicallyrequired to remove 0.75 to 1.0 mm (30 to 40 in) of copper to ensure that organic surfacecontaminants are sufficiently removed. Available chemistries offer a variety of surfacetopographies and process compatibilities. Many variables from prior manufacturing steps affectthe requirements and effectiveness of preclean, such as solder mask and solder strip. These willbe discussed in more detail in Sec. 30.4.1. The preferred method of preclean is an in-lineconveyorized system. The chemistries are sprayed onto the panel and transported at acontrolled rate to achieve a consistent etch and production rate. The horizontal process requiresthese controls for best results. Many vertical lines use off-line batch cleaning. This isaccomplished by a horizontal precleaner or by immersing the panels in a tank of chemistry,repeating the procedure for rinsing, and followed by a hot air dryer. Many process variables areintroduced with this process, and time between preclean and solder coat is typically notcontrolled. Reoxidation of the panel is inevitable, which reduces solderability.

30.3.2 Preheat

Preheating varies with the equipment being used. A preheater serves two main functions: itreduces thermal shock and helps prevent blocked or reduced holes. Efficient use of preheatminimizes thermal shock to the PWB when immersed in the molten solder. Some verticalprocesses do not use preheat. However, solder dwell times are increased to compensate,especially with thicker panels over 0.062 in (1.6 mm). Typically, the panel is heated byadditional dwell time in molten solder at 490°F to 510°F (254°C to 266°C). Some horizontaland vertical processes use convection ovens to prebake the panels as a preheat. The mostcommon horizontal system uses an infrared (IR) conveyorized preheater in line with variableintensity and speed to control heating. The exit temperature should be monitored for process

Preclean Preheat Flux Solder Air knife Cool Down Postclean

control and product consistency. A typical 0.062 in (1.6 mm) thick panel temperature exitingpreheat should be 291°F to 345°F (144°C to 174°C) when measured at the surface. Efficientheat transfer to the core of the PWB is important when processing panels of high aspect ratiosor inner layer connections that serve as heat sinks. Applying heat at a preheat stage allows forreduced dwell times in the solder. Solder being cleared from the holes is more easilyaccomplished when panel temperature is elevated. Recent horizontal processes have revealedthat preheating prior to applying flux to the panel is more beneficial than preheating after fluxcoat. Postflux preheating causes the flux to lose some of its active ingredients and, with aconveyorized IR preheater, it is a safety concern for potential combustion. With flux applicationafter preheating the panel, these concerns are minimized. Common process options used are:

1. Flux, heat, coat2. Heat, flux, coat3. Batch heat, coat4. Batch heat followed by no. 1 or no. 2 (Note that this sometimes is used for thick

backplanes or multilayers.)

30.3.3 Flux

Flux application may vary somewhat by immersion or coating brush/nap rolls. Many solder-leveling fluxes are available. The viscosity and acidity requirements are very much product-,process-, and equipment-dependent. Horizontal HAL typically requires a much lower viscosityflux than the vertical processes. The reduced dwell time in the molten solder of the horizontalprocess requires the flux to disperse quickly to allow for adequate solder wetting. Flux selectionmust take into consideration requirements such as surface insulation resistance (SIR), ionics, anduniformity as well as product characteristics that affect flux performance. Product characteristicsinclude coverage issues, solder mask type, base materials such as nickel/gold, and no-leadsolder alloys.

30.3.4 Solder Coating

Solder coating is accomplished by total immersion of the PWB in molten solder. A glycol-basedoil blanket, with chemistry compatible to the flux, limits dross formation on the solder. Inhorizontal equipment, it protects dross formation on any moving parts that would otherwise beexposed to the atmosphere. In the most commonly used horizontal equipment today, PWBs areconveyorized on a level plane through the solder by tapered rolls that hold the panel flat for asolder dwell time of two seconds. Other horizontal systems use various conveyor mechanismsto transport panels through the solder. These range from rolls to mesh conveyors, with somesystems using conveyors that are angled. The panels are bent slightly as they are processedthrough the solder.

In all HAL, the previously applied flux is displaced by the solder. An intermetallic (IMC) bond(Cu6Sns) is formed between the base copper and the solder. The horizontal soldering process

should be complete in less than two seconds if there are no contaminates interfering with thedirect contact of the solder to the copper. The vertical process dwell times vary from the top ofthe panel to the bottom of the panel with PWB thickness. Some types of copper contaminationcan be displaced with additional time in the molten solder. Increasing solder dwell times must beconsidered carefully, as this also increases the thickness of the IMC layer. The IMC layer is nota solderable surface and must have sufficient eutectic solder thickness overcoating after levelingto ensure solderability.

30.3.5 Leveling

Leveling actually takes place directly after solder coat. With molten solder coating the PWB, itis passed through pressurized hot air knives to remove excess solder and level the remainingdeposits, as well as to clear the holes of excess solder. The air is supplied via commercialcompressors through a heat source and then to the air knife. Typical air temperatures are 400°Fto 500°F (204°C to 260°C) at the knife. Air pressures range from 12 to 30 psi dynamic,depending on the equipment used, board thickness, hole aspect ratio, and knife distance fromthe PWB.

Leveling results are controlled by air knife configurations and setup parameters. Criticalparameters include panel-off contact (distance from panel to air knife), air knife angle, dynamicair pressures (in psi), panel SMT feature orientation, and speed through the air knife. Thevertical HAL process is at a major disadvantage at this stage. Panel fixturing limits off-contactdistances and, due to the panel being vertical, produces a natural tendency for solder to sag orpuddle on the lower edge of a component pad, surface mount pad, or plated through-hole(PTH), which can affect hole size.

Once the molten solder is leveled, it must solidify before cleaning. Solidification takes only a fewseconds. Cool-down takes on different forms for different applications. Some applicationsrequire only that the solder solidify during cool-down, but others require the panel to reach acertain temperature to prevent panel warpage or thermal shock when entering postclean liquids.The horizontal process can accommodate these variations in line using an air table concept. Thepanel floats on a bed of air. Most vertical processes require the panel to be manually removedfrom the solder coat fixture and racked on an accumulator or placed on an off-line cool-downmodule.

30.3.6 Postclean

Postclean is the final stage of the HAL process. Customer and application requirements cover awide range at this stage. Depending largely on product type and application, postclean can be asimple removal of flux residuals to very tight specifications for ionic contamination levels(IONICS) and surface insulation resistance (SIR) requirements. The most common variables atpostclean are the chemistries used and their concentrations. Water quality, water with adetergent, water with board cleaners, and solvents used along with flood, high pressure, and

brush chambers affect the final results. Telecommunications applications typically have thehighest standards of cleanliness. The water rinse can be tap or DI. Variables that apply tochambers are bath temperature, water flow rates and recirculation (conductivity sensors), andcontact time.

30.4 CAPABILITIES

30.4.1 Preclean

Preclean operations at HAL are intended for, and capable of, oxidation removal from thesurface of the base copper metal. Preclean requirements and success are dependent on theproduct supplied for HAL. Contaminants remaining from uncontrolled or incomplete processingat prior processes will not be removed in a mild microetch and will impair the solder coatingresults. Figure 30.4 shows the common sources of contamination and a simple oxide disclosuretest procedure for testing copper cleanliness and solderability troubleshooting after each of theseprocesses.

Common variables at preclean are:

• Type of chemistry

• Concentration of active ingredients (oxidizer, acid)

• Copper concentration of etchant

• Temperature

• Contact time

Several of these are shown with typical microetch ranges used and the effect each has onprocess results. Table 30.1 shows the most common chemistries used. Pre-clean bath life isoften dictated by copper concentrations. One method of controlling copper concentrations inthe bath is use of a bleed-and-feed system. This adds fresh chemistry by using a controller thatanalyzes for copper concentration using a copper colorimeter.

FIGURE 30.4 Contamination and oxide disclosure (courtesy of Pratta).

Tank 1 20% ebonol C-50 Tank 2 80% water (ambient temperature)

Procedure: Dip panel into tank 1. Soak two minutes.

Rinse in tank 2.

Air dry. Inspect for uniform blackening.

• Uneven blackening indicates that an organic is hindering the coat of this blackeningmaterial.

• Once the organic is cured to the copper, it is nearly impossible to remove byconventional pre-cleaning in microetches.

• The test is nondestructive.• Remove blackened surface by conventional precleaning.

TABLE 30.1 The Most Common Preclean Chemistries

Chemistry Etch rate* Ferric chloride 30-70 µin

Sodium persulfate 30-70 µin Peroxide sulfuric 30-70 µin

* Actual etch rate required varies with product.

There are many theories as to the effect different preclean chemistries have on solderdistribution. One study evaluated hydrogen peroxide/sulfuric acid, sodium persulfate, potassiummonopersulfate, and ferric chloride. Approximately 60 µin (1.5 µm) of copper was removedfrom each sample. The micrographs in Figs. 30.5 through 30.14 show the copper surfacetopography by SEM at 1,000x and 2,000x magnification. Table 30.2 shows the solderdistribution on the surface after HAL. Microetch chemistry shows no strong effect on solderdistribution across surface mount pads, even though there are noticeable differences in thecopper surface topography produced by the different chemistries.

Adequate copper preparation is essential for preferred results at solder coat. Any organicresidue remaining on the surface will delay or prohibit solder coating in that area. The precleanoperation at HAL is not intended to or capable of removing contaminants on the surface as aresult of incomplete processing at prior operations. An easy oxide test can be done at eachoperation to identify the source of contamination. The procedure is shown in Figure 30.4, withcommon sources of contamination shown in the troubleshooting guide.

TABLE 30.2 Preclean Solder Distribution Effects (courtesy of Pratta)*

Measuring points Ferric chloride Sodium persulfate Peroxide/sulfuric 1 0 0 0 2 52 55 58 3 52 50 65 4 105 100 125

5 280 300 265 6 255 280 250 7 0 0 0 X 148.8 157.0 152.6

* The thickness of solder and its distribution across the pads did not change significantly withthe different microetch chemistries, as shown by the solder thickness graphs of averagemeasurements. All measurements are in microinches.

30.4.2 Preheat

A minimum PWB surface temperature is required for IMC formation and soldering to takeplace. A process balanced for preheat and dwell time is needed. Pre-heat at HAL is intended toheat the core of the PWB to prevent blocked or reduced holes and minimize thermal shock.While prevention of blocked and reduced holes can be a process variable, the minimization ofthermal shock can be a function of board integrity.

Some HAL processes do not include preheat. The holes are heated by increasing the soak(dwell) times in the molten solder. This substitute is effective in allowing air to clear most holes atthe air .knife, provided the panel is not too thick and the holes are not too small (aspect ratio).Excessive soak time can be detrimental to the PWB quality, causing conditions such asdelamination and high IMC thickness, which can be detrimental to solderability at assembly.

Thermal shock has always been a concern associated with the HAL process. Controlled use ofpreheat minimizes the thermal shock subjected on a PWB (Fig. 30.15). Vertical processes thatuse a preheat and then stage the panels prior to solder coat cannot control the temperature inwhich a panel enters the solder. The panel is preheated but cools for an undetermined time atuncontrolled temperature conditions. Therefore, process controls are lost.

30.4.3 Flux

Flux can be applied by immersion, rolls, or spray. Complete coverage and uniform coating areimportant. Flux selection can be difficult and confusing, depending on the products beingprocessed and the equipment being used. The proper flux selection will provide adequatelubrication to the panel, promote coverage, wetting of the solder and, when applicable, becompatible with oil blankets on the solder. When cleanliness requirements are measured, theflux must also be readily removed without leaving residuals.

The type of chemistry is sometimes dictated by the customer. Some applications require rosin-based fluxes or other specialty fluxes. However, the most common fluxes used are watersoluble, glycol-based. These give the best results and are easier to remove after HAL withoutsolvents.

Fluxes used for HAL are typically acid-activated using HC1 or HBr. Some citric and otheracids are being evaluated. Concentrations vary and are somewhat product dependent. Highlyactive fluxes increase effectiveness to break down flash oxidation on copper to promote soldercoverage. Lower flux activity tends to provide cleaner soldered boards with less corrosive ionicsalts and residues.

The last variable to be discussed here is flux viscosity. This too is very much product andprocess dependent. Higher-viscosity fluxes provide better laminate and solder mask protection(lubricity) from solder sticking. Lower viscosity fluxes promote faster solder wetting andcoverage as well as better rinsing in the postcleaner.

During operation, flux properties may vary with each system. Some equipment types use fluxrecirculators that expose flux to preheated panels. This repeated exposure to heat will alter theoriginal flux viscosity and volatile content. Flux level, viscosity, and volatile content can becontrolled with the use of a flux-replenishing system. A replenishing system will containelectronics and sensors to balance the flux reservoir by addition of replacement flux orreplenisher flux, which is a high-volatile version of the original flux.

30.4.4 Solder Coating

Solder coating is the actual application of solder. Solder coating should be accomplished in aslittle time as required to provide adequate solder wetting with a thin layer of IMC. This isnormally accomplished in less than two seconds with in-line preheating. IMC is the tin andcopper migration that creates the metallic bond between the copper feature and surface solder.While a layer of IMC is essential to the process, it should be kept as thin as possible (Fig.30.16). The IMC layer will continue to grow as copper migrates toward the surface, The rate ofgrowth is slow during normal storage conditions; however, growth is rapidly accelerated witheach thermal cycle the panel experiences. Table 30.3 shows a comparison of IMC thicknessestypically obtained using a horizontal process and a vertical process. Although the solder dwelltimes are both considered to be two seconds, in a vertical process, the leading edge of the panelgoing into the solder is also the trailing edge on withdrawal. This varies the dwell time across thepanel and the IMC thickness. The horizontal process removes this variable as the first end in isthe first end out, yielding a uniform dwell time across the panel. Panel size or thickness has noeffect.

TABLE 30.3 IMC Thickness Comparison by Process

Horizontal vs. Average Maximum Vertical µin µm µin µm

Horizontal (1 pass)

6.0 0.15 15.3 0.38

Horizontal 10.8 0.27 39.9 1.00

(2 pass) Vertical A

(1 pass) 15.0 0.37 51.0 1.27

Vertical B (1 pass)

12.5 0.31 48.0 1.20

Vertical C (1 pass)

17.5 0.44 75.0 1.88

Vertical D (1 pass)

13.0 0.33 49.0 1.20

IMC thickness becomes important when surface mount thickness specifications are addressed.Horizontal HAL with a two-second solder dwell time shows an average of 6 µin (0.152 µm).The vertical process shows an average range of 12.6 to 17.6 µin (0.31 to 0.44 µm), dependingon equipment used. The maximum IMC thickness shown is approximately 20 µin (0.5 µm) forthe horizontal process and over 70 µin (1.75 µm) on the vertical process. The high range ofIMC thickness on the vertical process is due to the variation of dwell time across the panel. Asshown in Fig. 30.17, the IMC thickness almost doubles with exposure to a second cycle sincethe IMC layer itself is not eutectic SnPb and is nonsolderable at assembly. A sufficient layer ofeutectic solder over the IMC layer is necessary to ensure solderability. Minimum solderthickness specifications typically take this into consideration and specify minimums sufficient tomatch the number of assembly thermal cycles required.

30.4.5 Leveling

Solder leveling is the removal of excess solder from the PWB. Capabilities of leveling varygreatly with equipment and process controls. The following capabilities are based on horizontalprocessing using a Unicote® system. Figure 30.18 shows some comparison data from othersystems. The horizontal systems are the latest generation of HAL and therefore show muchimproved capability. The above capabilities are based on a uniform two-second dwell time anda specific process system using the Unicote® machine. These capabilities may vary with otherHAL processes.

30.4.6 Postclean

Postclean is the removal of processing fluids from the surface of the PWB. The primary concernis removal of any flux from the surface of the PWB after leveling. Typical postclean operationshave a detergent wash followed by a water rinse.

Because HAL fluxes are water soluble, this is adequate for general cleaning applications.

Some applications require more stringent cleanliness standards. These require measurements ofionic contamination levels as well as surface insulation resistance.

Typical SIR requirements are 3 x 109 f2 at 24 hours, 95°F (35°C) and 85 percent RH afterHAL. Typical ionic requirements are 6.5 µg/cm2. Several proprietary chemistries are availableto help achieve these requirements. Many factors contribute to ionic and SIR levels, and oftenan entire process must be reviewed. The use of DI water and extended length of rinse chambersis sometimes required (Tables 30.4 through 30.7).

Surface insulation resistance after HAL

Dept: Screening --- without s/m

HAL X with s/m Type s/m: Deso Temperature: 95° F to 104°F

(35°C to 40°C) RH: 85% min. Time: 24 hours

Test conditions: Volts: 50 No. test points: 32 IRA: 7.4 × 103 R. min.: 4.0 × 103

TABLE 30.4 Combination Pattern vs. Entire Board* (courtesy of Pratta) Date Process Pattern Average P/F Log no.

08/02/94 PI/SS/DI CD GH 1.0012

pass 370 comb only: DI No HAL 08/03/94 PI/HAL CD GH 25510 pass 376 comb only: DI 90°F std.

08/05/94 PI/HAL CD GH 3.3710

pass 378 comb only: DI 125°F 08/07/94 PI/HAL CD GH 7.569 pass 382 comb only: DI 90°F new sox

08/12/94 PI/HAL ABCDEFGH 7.3210

pass 385 comb only: 125°F new sox

08/02/94 PI/SS AB EF 1.0012

pass 369 comb only: no DI no HAL

08/03/94 PI/HAL AB EF 1.9310

pass 374 comb only: no DI 90°F std. 08/05/94 PI/HAL AB EF 0.539 pass 377 comb only: no DI 125°F 08/07/94 PI/HAL AB EF 1.949 fail 381 comb only: no DI 90°F new sox

08/02/94 PI/SS/DI CD GH 7.6511

pass 372 entire board: DI no HAL

08/03/94 PI/HAL CD GH 5.9810

pass 374 entire board: DI 90°F

08/05/94 PI/HAL CD GH 4.6610

pass 380 entire board: DI 125°F

08/07/94 PI/HAL CD GH 2.0210

pass 384 entire board: DI 90°F new sox

08/02/94 PI/SS AB EF 8.4711

pass 371 entire board: no DI no HAL 08/03/94 PI/HAL AB EF 4.199 pass 373 entire board: no DI 90°F 08/05/94 PI/HAL AB EF 4.389 pass 379 entire board: no DI 125°F 08/07/94 PI/HAL AB EF 8.149 pass 383 entire board: no DI 90°F new sox

* Comb only = no mask over remaining board for lots with mask in honeycomb area. Typicalhoneycomb pattern on both types.

Entire board = mask covering legs and honeycomb.

TABLE 30.5 SIR Test Results--Finish A Solder Mask*

Reading no. Resistance (ΩΩ ) Log10 of resistance 1 6.009 9.7781513 2 7.009 9.845098 3 7.409 9.8692317 4 6.009 9.7781513

5 9.0010

10.945243 6 6.509 9.8129134 7 9.709 9.9867717 8 6.109 9.7853298 9 9.509 9.9777236 10 9.809 9.9912261

11 1.3010

10.113943

12 1.8010

10.255273

13 1.6010

10.20412

14 1.4010

10.146128

15 1.3010

10.113943

16 1.4010

10.146128 17 5.909 9.770852 18 7.509 9.8750613 19 6.709 9.8260748 20 3.909 9.5910646 21 8.809 9.9444827 22 8,909 9,94939 23 8.809 9.9444827 24 8.109 9.908485 25 3.309 9.5185139 26 2.809 9.447158 27 2.209 9.3424227 28 1.209 9.0791812 29 5.709 9.7558749 30 6.709 9.8260748 31 6.109 9.7853298 32 6.309 9.7993405

10 average of longs 7565151221 Minimum resistance (Ω) 9.07918125 Maximum resistance (Ω) 10.9542425

Process sampled Finish B--Vacrel Date sampled 09/13/94 Line width (25 mil nominal) 25 Line spacing (50 mil nominal) 50 Pass/fail pass* Courtesy of Pratta

TABLE 30.6 SIR Test Results--Finish B Solder Mask*

Reading no. Resistance (El) Log10 of resistance 1 6.2010 10.792392 2 8.3010 10.919078 3 6.9010 10.838849 4 1.2010 11.079181 5 5.0010 10.69897 6 3.8010 10.579784 7 4.5010 10.653213

8 8.708

8.9395193 9 2.1010 10.322219 10 3.7010 10,568202 11 4.3010 10.633468 12 7.5010 10.875061 13 1.9010 10.278754 14 1.5010 10.176091 15 4.0010 9.60260 16 4.7010 10.672098 17 2.7010 10.431364 18 3.1010 10.491362 19 2.4010 10.380211 20 2.0010 10.30103 21 4.3010 10.633468 22 2.6010 10.414973 23 1.8010 10.255273 24 1.6010 10.20412 25 6.6010 10.819544 26 7.9010 10.897627 27 5.6010 10.748188 28 4.8010 10.681241 29 7.2010 10.857332 30 6.4010 10.80618 31 4.7010 10.672098

32 8.0010 10.90309

10 average of longs 3.42921 o Minimum resistance (Ω) 8.93951925 Maximum resistance (Ω) 11.0791812 Process sampled Finish A--Probimer 52 Date sampled 09/13/94 Line width (25 mil nominal) 25 Line spacing (50 mil nominal) 50 Pass/fail pass * Courtesy of Pratta

30.5 TROUBLESHOOTING

Please refer to Appendix 1 for a troubleshooting guide.

30.6 INDUSTRY STANDARD SPECIFICATION GUIDELINES

These specification guidelines have been compiled to establish and standardize achievablesolder thickness requirements and measurement techniques. All information, requirements, andtechniques given are based on the results of extensive testing and production through thecomponent assembly process. The coating of eutectic solder (Sn63) was applied on coppersurfaces of the printed wiring board using the Unicote® horizontal process for the evaluations.

30.6.1 Terminology

The following definitions are to clarify terms used in these guidelines:

Mean Average thickness for a given number of thickness readings

Crest Highest point for a given feature (pad)

Center Middle of a feature (pad); some geometries will have crests at thecenter, some may not

Data group Data collected to show thickness deviation within a single feature size ordifferent feature sizes at given measurement locations

Coplanarity Levelness from pad to pad over entire board, or within certain featuresize groups

Measure the crests of all features as one data group. Measure thecenters (minimum) of all features as your second data group. Donot mix data groups. This will show two planes

Uniformity Levelness from pad to pad within a single featureMeasure one geometry only (i.e.: all 0.025 in (0.64 mm) pitch quadflat packs (QFPs). Measure crests in one data group. Measurecenters (minimum) in a separate data group. Note that for QFPs,measure North, East, South, West in rotation or patterns North,South, East West to show any directional dependency. Do not mixdata groups. Repeat procedure for each geometry required bycustomer. If only one geometry is measured, it will be the mostcritical feature.

Distribution Levelness within a padTo determine the range of solder thickness over a feature (pad), aminimum of five points should be measured over the feature.Distance to edge of pad should be 0.010 in (0.25 mm) minimum.The number of data points required will usually be determined bythe end user, but a minimum of 24 data points per data group isrecommended.

TABLE 30.7 SIR after HAL

Hours 24 hours Hours 24 hours A l&2 4.7 x 103 E l&2 8.0 x103

2&3 4.3 x 103 2&3 7.2 x 103

3&4 5.0 x 103 3&4 8.4 x 103

4&5 4.0 × 103 4&5 8.4 x 103

B l&2 5.1 x 103 F l&2 1.1 × 104

2&3 4.4 × 103 2&3 1.5 ×104

3&4 5.0 × 103 3&4 1.3 x 104

4&5 5.9 x 103 4&5 1.6 × 104

C l&2 6.0 x 103 G l&2 1.5 x 104

2&3 6.0 x 103 2&3 1.4 x 104

3&4 5.5 x 103 3&4 1.6 x 104

4&5 5.4 × 103 4&5 1.2 ×103

D l&2 6.2 x 103 H l&2 1.0 x 104

2&3 6.4 x 103 2&3 7.6 x 103

3&4 5.0 × 103 3&4 5.2 x 103

4&5 5.6 × 103 4&5 7.8 x 103

30.6.2 Process Variables

Copper surface The copper surface must be clean, free of organic contaminates, andoxidation that restrict solder distribution within a feature or prevent solder from adhering tothe copper (see Secs. 30.3.1 and 30.4.1). Other metal surfaces to be soldered have thesame requirements; however, they are not covered in this document.

Feature geometry The geometry of a feature will affect the thickness results at a given setup.Large features tend to be thinner than small features on the same side of the panel.

30.6.3 Equipment and Setup

Grouping data The most meaningful data is obtained when it is grouped, usually by geometryand measurement location. When establishing process control and checking machine setup,only one feature size should be measured per data group. This method of grouping willprovide thickness results that relate to assembly placement by component [i.e. 0.025 in(0.64 mm) pitch QFPs versus 0.100 in (2.54 mm) pitch or 1206 chip sites]. This alsoallows the tightest uniformity control when setting up the equipment and establishing processcontrol. Using this method, a three sigma process can be accomplished as discussed later.

• Other methods of grouping data can be meaningful tools for gathering information orconfirming ranges like entire panel coplanarity. However, it is important that the value ofthese be understood and used as inspection tools rather than setup and controlprocedures. Because this is a geometrically dependent process, combined data willhave a larger process window and will vary with board technology.

30.6.4 Most Critical Feature

The most critical feature, usually defined by the end user, represents the feature with the tightestsolder thickness requirement. This is usually the finest pitch or smallest SMD feature on thepanel, and it has a tight tolerance at assembly. The most critical feature will be used forestablishing the thickness and uniformity as described previously. Remaining features may bethinner or thicker, depending on panel geometry, feature size, and orientation on card.

30.6.5 Method of Measurement

Measurements are typically taken using X-ray fluorescence (XRF) equipment. There are manyXRF equipment manufacturers, and each instrument has specific, unique features. We willdiscuss general requirements here, and all examples will be based on the Seiko XRF ModelSTX 3000.

The goal is for the collimator diameter or width to be less than one-half of the pad width.Measurement times will vary with equipment manufacturer and thickness of calibration range. Itis important to test and gain confidence in the equipment used. Measurements taken outside thecalibration thickness range will result in false readings.

Panel orientation is important, especially for fine-pitch QFP features. Many XRF units arecapable of measuring small features in only one direction. When measuring small features (i.e.0.020 in [0.51 mm] pitch and finer), compare east/west measurements with north/southmeasurements. Rotate panel 90° and repeat measurements. Monitor for differences in result. Ifa large difference is detected, the accuracy of one direction should be verified by cross sectionand panel rotated as necessary for accuracy. Collimator size is important, especially on smallfeatures (Table 30.8). The larger collimators are more accurate at shorter measurement times.The larger the collimator, the larger the sample area. However, it is important to ensure that thecollimator (or sample area) does not extend beyond the area to be measured. Alignmentaccuracy of machine and operator must be considered. The feature must be focused properly inthe z-axis to ensure accuracy. If these conditions are not met, the accuracy is greatlycompensated.

TABLE 30.8 Typical Collimators Used

Feature size Collimator>0.025 in (0.64 mm) 0.008 in (0.20 mm) circular0.015 to 0.025 in (0.33 to 0.64 mm) 0.004 in (0.10 mm) circular0.005 to 0.015 in (0.13 to 0.38 mm) 0.001 x 0.016 in (0.02 mm × 0.41 mm) rectangular

Measurement times are determined by collimator size, thickness range, and calibration. It isimportant that the proper calibration is used for the thickness range being measured. Calibrationcurves should be reviewed to determine the best one for the product. Many XRF modelscalculate the suggested times for accuracy. As a rule, the smaller the collimator, the longer themeasurement time. Typical times will range between 10 to 30 seconds. Inadequatemeasurement times will result in false readings.

30.6.6 Thickness Capability Specification

If the criteria for measuring uniformity and most critical feature is followed, then a processwindow of 70 µin (1.75µm) minimum and 800 µin (20 µm) maximum at crests on surfacefeatures is achievable on standard SMT panels. For 20 mil (0.5 mm) pitch and greater, panelswere processed through both the HSL-175 and HSL-350. For panels with less than 20 milpitch, panels were processed through HSL-175 (Table 30.9).

Critical feature. For 0.020 in (0.5 mm) pitch or greater QFP geometries, a nominal thickness

of 250 to 500 µin (6.25 to 12.5 µm) with 3 sigma deviation is achievable.

For 0.015 in (0.4 mm) pitch and small QFP geometries, a nominal thickness specification willvary by customer assembly practices. Ranges we have run successfully to date include thefollowing:

TABLE 30.9 Process Windows at Crest (Panel Uniformity)

1. 20 mil (0.5 mm) pitch 70 to 800 µin (1.75 to 30 µm)2. 15 mil (0.4 mm) pitch 70 to 1500 µin (1.75 to 37.5 µm)

3 sigma deviation Mean ± [(3) (std. dev.)] = window range

1. Mean thickness 400 to 600 µin (10 to 15 µm)3 sigma minimum of 100 µin (2.5 µm)3 sigma maximum of 1000 µin (25 µm)

2. Mean thickness 500 to 800 µin (12.5 to 20 µm)3 sigma minimum of 200 µin (5 µm)3 sigma maximum of 1200 µin (30 µm)

Other features Chip sizes up to Standard 1206

Crest measurement: Mean average between 100-600 µin (2.5-15.0 µm)Minimum average at center: HSL-350: 30 µin (0.75 µm)

HSL-175: 70 µin (1.75 µm)

Other features Plated holesMaximum hole reduction 0.003 in (0.76 mm) max. from copper: 0.001-0.002 in (0.025-0.051 mm) typical

30.6.7 Intermetallic Compounds

Intermetallic compound (IMC) growth can be minimized, depending on process parametersused. Typical IMC growth is 6 to 12 µin (0.152 to 0.30 µm) average.

30.7 EFFECTS OF CONTAMINANTS IN EUTECTIC SOLDER

Soldering processes, by nature, are considered complicated and involved due to the variousfactors that must be maintained and monitored. Most of these factors are indigenous to theprocess, such as pot temperature, dwell times, and contamination levels. Items such astemperature and dwell times are readily measured, adjusted, and understood, making themsome of the more comfortable aspects of the soldering process. Solder contamination, on theother hand, tends to be a less understood phenomenon. To accurately determine trace

contamination levels in solder requires very specific analytical equipment and precise analyticalmethods. Most solder suppliers provide multi-element analysis beyond tin, lead, and copper.Once levels of contaminants have been determined, interpretation of these results may requireassistance based on your particular problem.

Typically, copper contamination and tin concentration were targeted as the gauges of therelative health of a solder bath. This was born of the fact that varying levels of other tracecontaminants were considered normal and, as they could not be removed anyway, would not beproductive in terms of process impact. With the advent of electrolytic-grade solders, there isnow a need to better understand the potential effects of these trace contaminants on solderperformance.

30.7.1 Copper

Copper, being the most typical contaminant, is probably the best understood in solderingcircles. Manifesting itself as an intermetallic along with tin, it is necessary to deal with it. Anormal by-product of the formation of the solder bond on the board surface, it migratesoutward from the board into the solder pot, where it typically becomes soluble andhomogeneous. There are two forms of this material, Cu3Sn and CusSn6, of which the latter ismore prevalent. There will come a point in the lifetime of any solder bath where the solubility ofthe copper/tin intermetallic will be at or near the saturation point. Boards processed under theseconditions [approximately 0.30 percent by weight at 470°F (243°C)] will show a pronouncedgritty appearance. The reason for this is that the intermetallic, being less dense than moltentin/lead, will migrate to the top of the deposit where the characteristic dendritic crystallinestructure will create the gritty surface.

This poses a problem, both in terms of esthetics and in solderability. The presence of aconcentrated copper in the relatively small volume of solder located on a pad will raise thethermal demand requirement on a local level, compromising the reflow characteristics of thesolder deposit.

30.7.2 Gold

Gold is another typical contaminant of a solder bath if it is being used to process boards thathave been previously tab plated. AuSn4 is another intermetallic that will form if solder is allowedto contact gold-plated surfaces. Utmost caution must be taken to avoid this occurrence,because gold is approximately six times more soluble than copper and can be even moredetrimental to the solder joint. Gold contamination will be visible as a frostiness of the solderdeposit with an accompanying embrittlement of the solder joint. A joint produced under theseconditions can be prone to failure under thermal cycling or high vibration environments.Adequate protection of the gold from solder contact or elimination of pre-gold plating are thekeys to controlling gold contamination. It can not be removed by any user-available methods--only by sophisticated metal treatment systems or solder bath replacement.

30.7.3 Tin

Variation of tin concentration can have a pronounced effect on solder performance, but there isa reasonable window in which to operate that is not difficult to maintain. Typically, mostprocesses will run well between 61.5 and 63.5 percent tin concentrations. The danger in runningabove or below this range is the change in melting points and subsequent variation in surfacetension characteristics. Surface mount processing poses particular problems primarily in thatsurfaces devoid of a hole demonstrate low surface-energy characteristics. As such, they resistthe efforts of fluxes and solder to achieve lower free-energy states and wet the copper surface.Sufficient deviation from the eutectic alloy ratio can affect later reflow performance in high-speed, low-temperature soldering applications.

An important factor to consider when examining the soldering of a board or a given area is that,although a pot might exceed the melting point of the solder deposit, there is a heat sink effect ofthe board and flux that will lower the overall amount of energy transferred to the board,decreasing the ability to melt the solder deposit. The physical scale we are dealing with in termsof thermodynamics is small enough to deviate from what we would consider correct and toforce us to reevaluate our way of troubleshooting and investigating problems.

30.7.4 Antimony

The element antimony as an intentional addition to solder alloys has become the subject of muchdebate. The rationale behind the addition is prevention of tin decomposition. Thisdecomposition, commonly referred to as tin pest, is in actuality a phenomenon associated withpure tin rather than its alloys. In fact, any significant level of contamination of tin will inhibit theallotropic transformation of beta-phase tin to alpha-phase tin. Antimony was initially chosenbecause it was not known at the time to adversely affect the soldering process.

The soldering technology of that time did not include the manufacturing of printed circuit boardsand did not anticipate stricter technical requirements. Today, we know that antimony has apronounced effect on the wetting function of solders onto copper. Previously, specificationsindicated that levels up to and including 0.50 percent by weight were allowable but, with theadvent of SMT, negative effects on wetting are being noted at significantly lower levels. Again,surface tension and flee surface energy criteria are illuminating deficiencies in established normsof material specification. Revisions of the specifications for incoming material purchases arebeing modified to allow the stricter requirements of this new technology to be satisfied.

30.7.5 Trace Materials

Up to this point, we have examined the effects of contaminants typical to the soldering processas either a natural by-product or as an intentional addition. We will now turn our attention toelements that are indigenous to the solder material itself by virtue of the procedures used to

produce it. As tin and lead are products of ore-refining procedures, there are bound to bevarying levels of trace or residual materials in the finished solder product. These tracecontaminants have the potential to disrupt the soldering process, depending on which ones arepresent and in what quantity.

One group of elements that pose a problem consists of aluminum (A1), cadmium (Cd), and zinc(Zn). These elements exhibit common characteristics in that they all increase the amount ofdrossing of the solder by contributing to the accelerated oxidation of the tin component. Notonly oxidation, but dewetting, grittiness, and dull or frosty solder deposits result from thepresence of any of these materials.

30.7.5.1 Iron and nickel. Iron and nickel are similar in that they both can cause adeterioration of the solder deposit that is akin to that of copper contamination. Both of thesematerials are surface active so that a grittiness and dullness of the solder will result if thesematerials are present in sufficient quantity.

Additionally, like copper, these materials can be removed from the functioning solder pot to alimited degree. This is accomplished by cooling the solder pot to near eutectic temperatures andallowing the low-density intermetallic to rise to the surface of the solder pot.

30.7.5.2 Silver. Silver, like gold, produces a dullness on the solder deposit that will rapidlychange to a sluggish cold appearance if allowed to reach high concentration levels.

30.7.5.3 Arsenic and phosphorous. Arsenic and phosphorous are grouped together due totheir similar effects on wetting. Relatively small amounts of these materials will significantlyincrease the time required to establish a sound solder joint and will compromise the integrity ofthe copper-to-solder adherence.

30.7.5.4 Sulfur. Sulfur is possibly the most critical of the contaminants, as it is chemicallyreactive with both the tin and lead components of solder and has the ability to degrade wettingseverely at only parts per million levels. Every effort should be made to avoid this contaminant,which is best accomplished by stringent checks on incoming material quality.

30.7.5.5 Bismuth and indium. Bismuth and indium are both common contaminants that arenot typically associated with any particular negative impact on soldering or solderability. In fact,these materials have been intentionally added to solder used in touch-up and repair applications,as they can assist in wetting and will allow for low-temperature soldering. However, cautionmust be observed in considering these special formulations for mass soldering applications. Thebenefits of these materials can be realized only in small-site applications, as there is a significantdegree of brittleness associated with these joints, which would not be acceptable in mass circuitboard applications.

30.7.5.6 Stand-alone contaminants. Bismuth and indium are the last elements discussed, for

an important reason. As indicated, no negative aspects regarding soldering and solderability areassociated with them. But this applies only when each is considered as a stand-alonecontaminant.

Provided that bismuth is the only contaminant present, and all other factors are nominal, thereshould not be any soldering problems. In the presence, e.g., of zinc, the situation may changeradically. Intrude copper now, and the situation will deteriorate further. The point here is thatcombinations of any of the materials will have unpredictable results. Some combinations will bemore benign than others, but the fact still exists that there is no guide or reference that can assistin knowing what combinations in what ratios are acceptable.

For this reason, it is advisable to minimize trace materials and promote process controls thatallow for control of the levels of materials that are natural and yet detrimental to the process.

Table 30.10 provides a listing of elements and prudent limits on contaminants based on thequality of available solder. These limits will be reflected for both incoming materials and processoperation.

TABLE 30.10 Solder Contamination Limits*Element Incoming material

specificationsIn-processspecifications

Copper (Cu) 0.001 0.300Iron (Fe) 0.002 0.004Silver (Ag) 0.0005 0.010Antimony (Sb) 0.01 0.100Arsenic (As) 0.005 0.020Bismuth (Bi) 0.002 0.010Cadmium (Cd) 0.0005 0.002Nickel (Ni) 0.001 0.005Gold (Au) 0.0005 0.045Aluminum (AI) 0.0005 0.002Indium (In) 0.002 0.010Zinc (Zn) 0.0005 0.003Sulfur (S) 0.001Tin (Sn) 63.3 62.8-63.5*All values are in percent by weight. Lead in balance.

ACKNOWLEDGMENTS

The author would like to extend thanks to the following individuals:

John Adams, Quality Assurance Manager, Altron, 1 Jewel Drive, Wilmington, MA

01887-3390Jack Fellman, R&D Director, Pratta Electronic Materials, Inc., 111 Zachary Road,

Manchester, NH 03109JoeWebb, Applications Development Manager, Dexter Electronic Materials, 144 Harvey

Road, Manchester, NH 03103Brian Raymond, Process Engineer, Hadco Derry, Manchester Road, Route 28,

Derry, NH 03038Martin W. Jawitz, Editor in Chief, and McGraw-Hill, Publisher, “Printed Circuit Board

Materials Handbook”, 1997.

APPENDIX 1TROUBLESHOOTING GUIDE

Problem Cause Corrective Action

Snow Lack of Lubricity 1. Increase oil circulation(solder smear) 2. Check solder flow

3. Check solder agitation4. Change flux5. Reduce preheat6. Decrease air pressure7. Check solder mask cure8. Reduce solder dwell

Dirt/mud Lack of lubricity 1. Same as snow

Dirty oil 1. Change oil2. Clean parts in contact with oil

Thin solder Excessive air pressure 1. Decrease air pressure(swept look)

Contaminated copper 1. Check etch rate2. Check for proper rinse3. Check dryer4. Check spray nozzles5. Do oxide test (Fig. 30.4)6. Check for solder mask7. Check for incomplete solder

stripping8. Decrease preheat9. Increase dwell time10. Use more active flux

Reduce air knife orifice 1. Clean air knife orifice2. Repair or replace air knife if

worn

Mixed geometries on 1. Reference Specificationpanel Guidelines, Sec. 30.7

Thick solder Insufficient air pressure 1. Increase air pressure

Air knife orifice too wide 1. Repair or replace air knifeor worn

Air leak in air hose or 1. Replace hoses and tighten orconnection replace connections as needed

Partially blocked air knife 1. Clean air knife orifice

Scratches on Mechanical contact with 1. Isolate unit causing scratches,panel panel remove and/or repair problem

area

Broken link(s) or burrs on 1. Inspect belts and conveyors formesh conveyor belts damage, replace or repair as

required

Handling 1. Instruct operators on correcthandling techniques

Cold solder Insufficient heat 1. Check preheat, increase if needed2. Check solder flow, increase as

needed3. Check air/air knife temperature

(425°F [218°C] typical)4. Check solder temperature (450°F-500°F [232°C-260°C]

typical)

Excessive solder contami- 1. Check solder analysis, maximumnation copper allowed typically is 0.3%

(see Sec. 30.7)2. Skim, dump, or dilute solder in

pot to reduce contaminant level

Touch marks Insufficient cool-down time 1. Increase cool-down time after airon solder knife and before postclean

2. Check alignment and nip line formechanical contact with panelafter the air knife and before thepostclean wash

Exposed copper Insufficient preclean 1. Check etch rate

2. Check rinse chambers; clean bath,clean nozzles, bath levels, and/orspray pressure

Excessive preheat 1. Reduce surface temperature of panel during preheat

Flux 1. Replenish or replace old spentflux with fresh flux

2. Replace with lower viscosityand/or higher acid flux (see Sec. 30.4.3)

Contaminated oil 1. Replace oil

Low solder flow 1. Increase per manufacturer's instructions

Low flow in fluxer 1. Increase flow or level in fluxerper manufacturer's instructions

Contamination on copper 1. Inspect for visible contaminationsurface using 10x or 30x magnification

2. Using cupric chloride test (Fig. 30.4) or black oxide, test for contamination

3. Identify source and clean coppersurface

Dewetting Contaminated copper 1. Check etch rate2. Check for proper rinse3. Check dryer4. Check spray nozzles5. Do oxide test (Fig. 30.4)6. Check for solder mask7. Check for incomplete solder

stripping8. Decrease preheat9. Increase dwell time10. Use more active flux

High organics in copper 1. Check copper plating parametersfrom plating