chapter 3 single-stage amplifierslibvolume3.xyz/.../singlestageicamplifiertutorial2.pdf ·...

Chen Xiaofei CMOS Chapter3 1

Chapter 3Single-Stage Amplifiers

Chen Xiaofei2010 HUST


Overview

• Reading

– Chapter 3• Introduction

In this lecture, we study the low-frequency behavior of single-stage CMOS amplifiers. Analyzing both the large-signal and the small-signal characteristics of each circuit, we develop intuitive techniques and models that prove useful in understanding more complex systems.

Following a brief review of basic concepts, we describe in this chapter four types of amplifiers:

---Common-Source Amplifier---Common-Gate Amplifier---Source Followers---Cascode


Table of Content

• Analog Design

• Common-Source Amplifier

• Source Followers

• Common-Gate Amplifier

• Cascode


Single-Stage Amplifiers


3.1 Analog Design

Tradeoffs

Most of these parameterstrade with each other. Such trade-offs lead to many challenges in thedesign of high performanceamplifiers.


DC and ac Analysis

• DC Analysis (Large-Signal Analysis)--- Determine the exact biasing.

• ac Analysis (Small-Signal Analysis)--- Obtain the expression of the voltage gain,

small-signal input and output impedance.


3.2 Common Source


Common-Source Amplifier Table of Content

• Common Source (CS) with Resistive Load

• CS stage with diode-connected MOS load

• CS with Current Source Load

• CS with Triode Region Load

• CS with source degeneration


3.2.1 Common Source (CS) with Resistive Load

• Resistive Load is often used in high-speed circuit because of the linearity of resistance, and also the output voltage swing may reach up to VDD.

Fig. 3.1 (a) CS Stage; (b) input-output characteristic; (c) equivalent circuit in deep triode region


DC Analysis

• DC Analysis (Large-Signal Analysis)(1) When V in < VTH , M1 is in cut-off region, Id=0, Vout=VDD-IdRD=VDD

(2) When V in > VTH , and V in < V in1 , M1 is in saturation region.

DTHinoxn

DDout RVVLWCVV 2)(

2−−=

μ

Here we have neglected channel length modulation.

DTHinoxn

DDTHin RVVL

WCVVV 211 )(

2−−=−

μ

From which Vin1-VTH and hence Vout can be calculated.

(3) When Vin − VTH = Vout , M1 is at the boundary of saturation and triode regions.

HTDD

in VV

V +−+

=α

α2

1411 where DPNDoxn R

LWkR

LWC )(

21)(

21

== μα

oxP Ck μ= ....Technology parameter


DC Analysis (Cont.)

(4) For Vin > Vin1, M1 is in the triode region,

])(2[2

2outoutTHinD

oxnDDout VVVVR

LWCVV −−−=

μ

As VGS has less control on Id when transistor M1 works in triode region, we usually leave M1 in saturation for a large voltage gain.

If Vin is high enough to drive M1 into deep triode region. Vout<<2(Vin-VTH),and,

In very deep triode range, Ron→0, Vout →0

)(1 THinDoxn

DD

Don

onDDout

VVRLWC

VRR

RVV−+

=+

=μ


AC Analysis

• AC Analysis (Small-Signal Analysis)(1) Derivation at the operation point

Assuming that the transistor is biased in strong inversion, active region

Taking the derivative of Vout with respect to Vin, we get,

DmTHinoxnDin

outv RgVV

LWCR

dVdVA −=−−== )(μ

DTHinoxn

DDout RVVLWCVV 2)(

2−−=

μ


AC Analysis (Cont.)

(2) Finding the gain using the small-signal equivalent circuit

Fig. 3.2 (a) CS Stage; (b) small-signal equivalent circuit


AC Analysis (Cont.)

Dmv RgA −=

This result can be directly derived from the observation that M1 converts an input voltage change ΔVin to a drain current change gmΔVin , and hence an output voltage change - gmRDΔVin .

(3) Intuitive observation


AC Analysis (Cont.)

• Taking the effect of channel length modulation in M1 into account, the small-signal equivalent circuit is modified as following,

)( oDmv rRgA −=

Fig.3.3 small-signal equivalent circuit including the output resistance of M1


Intrinsic Gain

• Intrinsic Gain

If RD=∞, then

called the “intrinsic gain” of a transistor, this quantity represents the maximum voltage gain that can be achieved using a single device. For ideal long-channeldevice, ro→∞, intrinsic gain →∞; however, in today’s Fig 3.4

CMOS technology, intrinsic gain of short-channel deviceis between roughly 10 and 30. Thus, we usually assume 1/gm << ro .

Question?: In Fig.3.4, Kirchhoff’s current law (KCL) requires that ID1 = I1. Then, how can Vin change the current of M1 if I1 is constant?

omv rgA −=


3.2.2 CS stage with diode-connected MOS load

A MOST can operate as a small-signal resistor if its gate and drain are shorted, called “diode-connected”.

• what is the impedance of the following circuit seen from the source side of transistor M1?


The small-signal equivalent resistance of diode-connected MOS load

sdsmbm

sdssmbsm

dsssbmbgsms

vgggvgvgvg

gvvgvgi

)( ++=++=

+−−=

mbmdsmbmmin gggggy

r+

≈++

==111

Seen from source terminal, the small signal conductance is given by

or, the resistance is

)( dsmbms

sin ggg

viy ++==

(1/gm << ro)


Gain (Av)

Av = −gm1 1

gm2 + gmb2= −

gm1

gm2

11 +η

Av = −(W / L)1

(W / L)2

11 + η

Av = −un (W / L)1

up (W / L)2

Gain is independent of bias current!


Voltage swing constraint

Av = −un (W / L)1

up (W / L)2

=| VGS2 − VTH2 |(VGS1 − VTH1)

∴= ,21 DD II

This implies substantial voltage swing constraint.

unWL

⎛ ⎝

⎞ ⎠

1(VGS1 − VTH1)2 =up

WL

⎛ ⎝

⎞ ⎠

2(VGS2 − VTH2)2


Advantage of CS with diode-connected load

• Advantage of CS with diode-connected load: linearity

Av = −(W / L)1

(W / L)2

11 + η

This equation imply: if the variation of ηwith the output voltage is neglected, the gain is independent of the bias currents and voltages (so long as the M1 stays in saturation. In other words, as the input and output signal levels vary, the gain remains relatively constant, indicating that the input-output characteristic is relatively linear.

• Homework: Please do large-signal analysis of this circuit to

determine the biasing range.


Large-signal analysis

VoutVout,max

=VDD-VTH

Vout,swing

Vout,min=Vin,max-VTH

VTH Vin,max’Vin,swing

Vin

Vout=Vin-VTH

P

maxin TH out outV V V V− ≤ ≤

( )2

1 ,max1

12 n OX in TH

WI C V VL

μ ⎛ ⎞= −⎜ ⎟⎝ ⎠

2,min

1

12 n OX out

WC VL

μ ⎛ ⎞= ⎜ ⎟⎝ ⎠

( )22 1 2

2

12 n OX GS TH

WI I C V VL

μ ⎛ ⎞= = −⎜ ⎟⎝ ⎠

( )2

,min2

12 n OX DD out TH

WC V V VL

μ ⎛ ⎞= − −⎜ ⎟⎝ ⎠

max,ininTH VVV ≤≤

At point P,


Example: CS with any type of load


Example: CS with any type of load (cont.)

• Loads in series :


Example: CS with any type of load (cont.)

• Loads in parallel :


Example 3.3

What is the voltage gain of the amplifier ?


3.2.3 CS with Current Source Load

Av = −gm ro1 || ro2

Assuming ro2 large,

Av = −gmro1 = − 2μnCox IDWL

⎛

⎝

⎜ ⎜ ⎜

⎞

⎠

⎟ ⎟ ⎟

1

1λID


CS with Current Source Load (cont.)

• Discussions:(1) Gain increasing:a) increase ro1 and ro2 ,

so increase L is an effective method.b) increase gm1,

Increasing W while keeping the Vov and L constant, gm1 increases.Note: increasing Vov is no use, as

11

oD

rIλ

=1L

λ ∝ oD

LrI

∝

1 ( )m n ox GS THWg C V VL

μ= −

2( )D GS THI V V∝ −



• (2) Design consideration:a) When requiring a large voltage gain, we usually design the

device with a large L2 of load M2 and a large W1 of M1, large L1 is not must.

b) If L1 is scaled by a factor n (>1), then W1 may need to be scaled proportionally as well. This is because, if W1 is not scaled, the overdrive voltage increases, limiting the output voltage swing.



• Classroom Exercise: Please do large-signal analysis of this circuit to determine the biasing range.

• Advantage of CS with current source Load : the output impedance and the minimum required VDS of M2 are less strongly coupled than the value and voltage drop of a resistor.


3.2.4 CS with Triode Region Load

Av = −gmRON2

|)|(1

2

2THPbDDL

WoxpON VVVC

R−−

=⎟⎟⎠

⎞⎜⎜⎝

⎛μ


CS with source degeneration

• The transconductance of the circuit---Gm

• The small-signal equivalent circuit（ Assuming λ =γ = 0 ）• Linearity discussion• Intuitive analysis and large-small characteristic• Example 3.5• Gm （ λ ≠ 0 ，γ≠ 0 ）• Output Resistance• Gain (Av)• Example 3.6


3.2.5 CS with source degeneration

• In some applications, the square-law dependence of the drain current upon the overdrive voltage introductions excessive nonlinearity, making it desirable to “soften” the device characteristic.

• In 3.2.2, we noted the linear behavior of a CS stage using a diode-connected load, but this topology has substantial voltage swing constraint.

• Some other method?


The transconductance of the circuit---Gm

GS GSD Dm m

in GS in in

V VI IG gV V V V

∂ ∂∂ ∂= = ⋅ =

∂ ∂ ∂ ∂

GS in D SV V I R= −

1 1GS DS m S

in in

V I R G RV V

∂ ∂= − = −

∂ ∂

( )1m m m SG g G R= − 1m

mm S

gGg R

=+

1m D

V m Dm S

g RA G Rg R

= − = −+

•Define: Gm----the transconductance of the circuit when the output is shorted to ground.


The small-signal equivalent circuit

If we ignore λ and γ :


Linearity discussion

• With source degeneration, the transconductance is more linear !!As Rs increases, Gm becomes a weaker function of gm and hence the

drain current.


Intuitive analysis and large-small characteristic

Sm

D

Sm

Dmv Rg

RRg

RgA+

−=+

−=

/1

1

Drain current and transconductance of a CS device (a) without and (b) with source degenaration.


Example 3.5

• Assuming λ =γ = 0 for both M1 and M2. Calculate the small signal gain.


Example 3.5 (cont.)

• Recall the result from common source stage with source degeneration :


Gm of CS with source degeneration

• What is the transconductance of the circuit (Gm) if we do not ignore λand γ ?


Gm of CS stage with source degeneration (cont.)

osmbms

omm rRggR

rgG])(1[ +++

=or,


Output Resistance

osombmout rRrggr +++= ])(1[

•Another importance consequence of source degeneration is the increase of the output impedance of the stage.


Gain (Av)

osmbmosD

Dom

in

outv rRggrRR

RrgvvA

)( ++++−==

) ||( outDmv rRGA −=

Lemma: In a linear circuit, the voltage gain is equal to -GmRout


Example 3.6

|| outDmv rRGA −=

}])(1{[|| || osombmoutD rRrggrR +++∞=

Av = −gmro !

Gm =gmro

RS + [1+ (gm + gmb )RS ]ro

Why? Please explain this result.


Homework2

• Exercises: 3.1 3.2 3.3 3.12 3.14

• Reading: Chapter3 3.3


Table of Content

• Analog Design




• Cascode


3.3 Source Follower (Common Drain Amplifiers)

• Our analysis of the CS stage indicates that, to achieve a high voltage gain with limited supply voltage, the load impedance must be as large as possible. If such a stage is to drive a low-impedance load, then a “buffer” must be placed after the amplifier so as to drive the load with negligible loss of the signal level. The source follower (also called the common-drain stage) can operate as a voltage buffer.

• The common drain stage exhibits high input impedance and low output impedance. After an analysis of relevant port characteristics, we will discuss some potential applications andalso drawbacks of this circuit.


Source Follower (cont.)

Input terminal: gate; output terminal: source.


Large signal behavior

• Large signal behavior

• When Vin<VTH, M1 is off, and Vout is 0.

• When Vin>VTH, M1 turns on in saturation. As Vin increases further, Vout follows Vin with a difference of VGS.

• When Vin increases to a certain voltage (exceeding VDD), M1 enters triode region, the output voltage flattens out and clips at VDD.


Small signal analysis

• Small signal analysis


Small signal analysis (cont.)


Small signal analysis (cont.)

• Interesting cases– Rs→∞, ro→∞, gmb=0

• PMOS, source tied to body, ideal current source

– Rs→∞, ro→∞, gmb≠0 • NMOS, ideal current source) (typically ≅ 0.8)

– ro→∞, gmb=0, Rs finite• PMOS, source tied to body, load resistor

bmdsLtot gg

RsR 11=

Ltotm

mv

Rg

gA 1+

=


Small Signal Output Resistance

• Small signal diagram for calculating output resistance


Small Signal Output Resistance (cont.)


Application 1: Level Shifter

• Output quiescent point is roughly VTH+Vov lower than inputquiescent point


Application 2: Buffer

• Low frequency voltage gain of the above circuit is ~gmRbig– Would be ~gm(Rsmall||Rbig) without CD buffer stage


Issues

• Several sources of nonlinearity– VTH is a function of Vo (NMOS, without S to B connection)– ID and thus Vov changes with Vo

! Gets worse with small RL

• Reduced input and output voltage swing– Consider e.g. VDD=1V, VTH=0.3V, VOV=0.2V

! CD buffer stage consumes 50% of supply headroom!– In low VDD applications that require large output swing, using a CD buffer is often not possible– CD buffers are more frequently used when the required swing is small

! E.g. pre-amplifiers or LNAs that turn μV into mV at the output


Homework 3

• Exercises: 3.15• Reading: Chapter3 3.4


Table of Content

• Analog Design




• Cascode


3.4 Common Gate Stage

Fig.1 CG stage with (a) direct coupling at input (b) capacitive coupling at input.

• In a common-gate amplifier, the input signal is applied to the source terminal, as is shown in Fig.1. It senses the input at the source and generate the output at the drain. The gate is connected to a dc voltage to establish proper operating conditions. Note that in Fig.1(b) the bias current of M1 flows through the input signal source.



• When Vin>VB-VTH, M1 is off, and Vout is VDD.• As Vin decreases, so does Vout, M1 is in saturation until

• After that, M1 is driven into the triode region.


Small signal analysis (1)---- CG Current Transfer

Define: gm’ = gm + gmb


CG Current Transfer (cont.)


Small signal analysis (2)---- Voltage Gain

DDSSombmo

ombm

in

outv R

RRRrggrrgg

vvA

++++++

==)(

1)(


Small Signal Input Resistance

Two interesting cases:

tstttsmbmtstotstD vvggiriR =+−+ ])([

)1()(

1)(1

o

D

mbm

ombm

oD

tst

tstin

rR

gg

rggrR

ivr

++

≈

+++

==

– RD<<ro:

– RD>>ro:

Thus,

(If (gm+gmb)ro>>1)

)(1

mbmin gg

r+

≈

ombm

Din rgg

Rr)( +

≈



oSombmout rRrggr +++= ])(1[

(Very high if (gm+gmb)RS>>1 !)


CG Summary

• Current gain is unity up to very high frequencies• Input impedance is very low

– At least when the output is also terminated with some reasonable impedance

• Can achieve very high output resistance• In summary, a common gate stage is ideal for turning a decent

current source into a much better one– Seems like this is something we can use to improve our

common source stage• Which is indeed nothing but a decent (voltage

controlled) current source


Homework 4

• Reading: Chapter3 3.4


Table of Content

• Analog Design




• Cascode


Overview

• We will cover different cascode amplifiers, including

– 1. Simple cascode amplifier

– 2. Multi-level cascode amplifier

– 3. Folded cascode amplifier


Simple cascode amplifier

Simple cascode amplifier

• Large signal behavior (Vin fixed to VG1, Vout (VDS) sweeping from 0 to 3V)

Region I: M1B and M2B both in triode; Region II, M1B in saturation, M2B in triode; Region III, M1B and M2B both in saturation



)]([ ])(1[

2221

21222

mbmoo

ooombmout

ggrrrrrggr

+≈+++=


Transconductance Gm

222

1

11 1

ombm

o

oinmout

rgg

r

rvgi

++

=

222

1

11 1

ombm

o

oinmout

rgg

r

rvgi

++

=

1 1 2 2 2

1 2 2 2 1 2

11

2 2 2 1

[ ( ) 1]( )

[1 ]

m o o m mbm

o o m mb o o

dsm

m mb ds ds

g r r g gGr r g g r r

ggg g g g

+ +=

+ + +

= −+ + +


Transconductance Gm (cont.)

• Observation: Compared with a single-transistor common source amplifier with a transconductance of |Gm|=gm1 (Note that Gm is the transcoducance of the amplifier, and gm is the transcoducance of the transistor), the transcoductance of cascode amplifier is slightly less, whose transconductance Gm is given by

• DC voltage gain (when the output is open)

11 1

2 2 2 1

[1 ] (90% ~ 99%)dsm m m

m mb ds ds

gG g gg g g g

= − =+ + +

1 1 2 2 2[( ) 1]m out m o m mb oAv G r g r g g r= − = − + +


Multi-level cascode amplifier

• Triple cascode amplifier

}])(1){[( 332122233 ooooombmmbmout rrrrrggggr +++++=

]1[1222

11

dsdsmbm

dsmm gggg

ggG+++

−−≈

]1)][()(1[ 33322211 ++++= ombmombmom rggrggrgAv


Supply Headroom Issue

• Even if we adjust VB suchthat VDS1 is small, adding a cascode reduces the available signal swing

• This can be a big issuewhen designing circuitswith VDD ≅ 1V

– Typically need each VDS > ~0.2V


Folded-cascode amplifier

Fig.1 (a) Simple folded cascode, (b) folded cascode with proper biasing, (c) folded cascode with NMOS input

• Why choose folded-cascode amplifier instead of telescopic configuration? – More freedom to choose the DC input voltage at vin (such as Fig. 1(a)). – Convenience in shorting the input and the output in feedback

configurations.



Fig. 2 Large-signal characteristics of folded cascode

• Suppose in Fig.1(b), I1 is the current flowing through M3 and is equal to the sum of ID1 and ID2.– Vin > VDD-|VTH1|, M1 is off and M2 carries all of I1, yielding Vout=VDD-I1RD. – For Vin<VDD-| VTH1 |, M1 turns on in saturation. – As Vin drops, ID2 decreases further, falling to zero if ID1=I1 (Vin=Vin1). – If Vin<Vin1, M1 enters triode.


Small signal Analysis

• The small-signal operation is as follows: If vin becomes more positive, |id1| decreases, forcing id2 to increase and hence vout to drop. The voltage gain and output resistance of the circuit can be obtained as calculated for the telescopic-cascode. This approximation approach is sufficient, because, in fact, currentsource Iss is a MOS constant current source and it’s output resistance is very large, while CG stage’s input resistance is relatively small, thus the shunting of Iss from the small-signal current can be ignored.


Folded-cascode amplifier summary

• Why choose folded-cascode amplifier instead of telescopic configuration? – More freedom to choose the DC input voltage at vin

(such as Fig. 1(a)). – Convenience in shorting the input and the output in

feedback configurations. • Disadvantages:

-- The total bias current in folded-cascode amplifier must be higher than that in telescopic configuration to achieve comparable performance.

-- Other disadvantages will be discussed in Chapter 6.


Homework 5

• Exercises: 3.19 (a) (d) 3.20 (a) (b) (c)3.21 (a) (b) (c) (d)3.24

• Reading: Chapter4 4.1 4.2

chapter 3 single-stage amplifierslibvolume3.xyz/.../singlestageicamplifiertutorial2.pdf ·...

Documents