53

CHAPTER 3

MODELING AND SIMULATION OF CASCADED

MULTILEVEL INVERTERS

3.1 INTRODUCTION

The converters have to be designed to obtain a quality output

voltage or a current waveform with a minimum amount of ripple content. In

high power and high voltage applications the conventional two level inverters,

however, have some limitations in operating at high frequency mainly due to

switching losses and constraints of the power device ratings. Series and

parallel combination of power switches in order to achieve the power

handling voltages and currents. The conventional two level inverters produce

THD levels around sixty percent even under normal operating conditions

which are undesirable and cause more losses and other power quality

problems too on the AC drives and utilities.

For high voltage applications, two or more power switches can be

connected in series in order to provide the desired voltage rating. However,

the characteristics of devices of the same type are not identical. For the same

OFF state current, their OFF state voltages differ. Even during the turn OFF

of the switches the variations in stored charges cause difference in the reverse

voltage sharing. The switch with the least recovered charge faces the highest

transient voltage. For higher current handling, the switches are connected in

parallel, however because of uneven switch characteristics the load current is

not shared equally. If a power switch carries more current than that of the

54

others, then the power dissipation in it increases, thereby increasing the

junction temperature and decreasing the internal resistance. This in turn

increases its current sharing and may damage the devices permanently which

is undesirable for critical applications.

In the conventional two level inverters the input DC is converted

into the AC supply of desired frequency and voltage with the aid of

semiconductor power switches. Depending on the configuration, four or six

switches are used. A group of switches provide the positive half cycle at the

output which is called as positive group switches and the other group which

supplies the negative half cycle is called negative group. A detailed

comparison is made between the conventional and multilevel inverter as

shown in Table 3.1.

The multilevel inverters perform power conversion in multilevel

voltage steps to obtain improved power quality, lower switching losses, better

electromagnetic compatibility and higher voltage capability. Considering

these advantages, multilevel inverters have been gaining considerable

popularity in recent years.

In the recent past, the multilevel inverters have drawn tremendous

attention in the field of high voltage and high power applications. In the

researches on multilevel inverters, determination of their respective control

strategies is the emerging topic which has been discussed in the previous

chapter. One of the most important problems in controlling a multilevel

voltage source inverter is to obtain a variable amplitude and frequency

sinusoidal output by employing simple control techniques. Indeed, in voltage

source inverters, non fundamental current harmonics cause power losses,

electromagnetic interference and pulsating torques in AC motor drives.

Harmonic reduction can then be strictly related to the performance of an

inverter with any switching strategy. In multilevel voltage source inverters,

55

various Pulse Width Modulation control schemes have been developed and

the same were analyzed in the previous chapter with respect to reduction in

power quality issues as discussed by Corzine et al (2003).

Multilevel inverter can increase the power by (m-1) times than that

of two level inverter through the series and parallel connection of power

semiconductor switches. Comparing this with two level inverter systems

delivering same power, multilevel inverter has the advantages that the lower

harmonic components on the output voltages can be eliminated and EMI

problem could be decreased. Due to these merits, many studies on multilevel

inverters have been performed at simulations and very few with the hardware

implementations.

3.2 TYPES OF MULTILEVEL INVERTERS

Figure 3.1 shows the classification of multilevel inverter topologies

which is existing in the area of power conversions

Figure 3.1 Classification of multilevel inverters

Multilevel Inverters

Separate DC

Sources

Common DC

Sources

Cascaded

Inverters

Diode clamped

Inverters

Flying Capacitor

Inverters

56

Despite, this work proposes a different control scheme, which is

fully pertained to cascaded multilevel inverters. Multilevel inverter topologies

are classified into three categories diode clamped inverters, flying capacitor

inverters and cascaded inverters.

Diode clamped inverters presented by Peng (2001), particularly the

three-level one, have taken much interest in motor drive applications because

it needs only one common voltage source and many simple and efficient

PWM algorithms have been developed, even if it has inherent unbalanced

DC-link capacitor voltage problem. However, it would be a limitation for

applications beyond four-level diode clamped inverters for the reason of

reliability and complexity considering DC link balancing and more number of

clamping diodes. On the other hand flying capacitor inverters as by Enjeti et

al (1992) needs more number of capacitors and also the capacitors are bulkier

for higher voltage ratings which are a critical problem on the sizing of the

inverter.

Cascaded inverters by Casadei et al (2008) have structurally not any

problem of DC-link voltage unbalancing or the requirement of the larger

capacitors but it requires many separated DC sources which is considered as a

major advantage with the present day rechargeable batteries. The batteries are

usually rated for 12V/24V, in order to build an inverter system for high

voltage motor drive applications for critical loads they are connected in series

to obtain the higher voltage ratings. The cascaded inverter has been largely

studied and used in the fields of SVC (Static VAR Compensators), voltage

stabilizers, HVDC transmission systems and so on. It may be noted that due

to other advantages of the modularized circuit layout and package, the

cascaded inverter could be selected as a good choice in high voltage motor

drive applications. In case of any device failure, the devices/failure unit can

be replaced without any difficulties.

57

Table 3.1 Comparison of conventional two level inverters and

multilevel inverters

S.No. Conventional Inverter Multilevel Inverter

1 Higher THD in output voltage Low THD in output voltage

2 More switching stresses on

devices

Reduced switching stresses on

devices

3 Not applicable for high voltage

applications

Applicable for high voltage

applications

4 Higher voltage levels are not

produced

Higher voltage levels are

produced

5 Since dv/dt is high, the EMI

from system is high

Since dv/dt is low, the EMI from

system is low

6

Higher switching frequency is

used hence switching losses is

high

Lower switching frequency can

be used and hence reduction in

switching losses

7 Power bus structure, control

schemes are simple

control scheme becomes

complex as number of levels

increases

8 Reliability is high

Reliability can be improved,

rack swapping of levels is

possible

3.2.1 Salient Features of Multilevel Inverter

1. Synthesis of higher voltage levels using power devices of

lower voltage ratings.

2. Increased number of voltage levels which leads to better

voltage waveforms and reduced total harmonic distortion in

output voltage.

58

3. Reduced switching stresses on the devices due to the

reduction of step voltages between the levels.

4. It not only solves harmonics and EMI problems, but also

avoids possible high frequency switching stress dv/dt.

5. Low switching losses and better electromagnetic

compatibility for high power application.

3.2.2 Comparison of Multilevel Inverter Topologies

Comparison of multilevel inverter is made based on the following

criteria:

• Number of semiconductor devices used per phase leg

• Number of DC bus capacitors used

• Number of balancing capacitors used per phase leg

• Amplitude of fundamental and dominant harmonic

components

• Total Harmonic Distortion of output voltage

• Control complexity based on voltage unbalances and power

switches

• Cost estimation in fabrication of power circuit and the

associated components

3.2.3 Key Notes

1. Diode clamped inverter needs (m-1) x (m-2) clamping diodes.

2. Flying-capacitor inverter needs (m-1) x (m-2) / 2 balancing

capacitors.

59

With the available facts, evidently we can conclude that cascaded

multilevel inverter is more efficient than other topologies of multilevel

inverter.

Table 3.2 Comparison of different multilevel inverter topologies

S.No. Topology Diode

Clamped

Flying

Capacitor Cascaded

1 Power semi conductor

switches

2(m-1) 2(m-1) 2(m-1)

2 Clamping diodes per

phase

(m-1)(m-2) 0 0

3 DC bus capacitors (m-1) (m-1) (m-1)/2

4 Balancing capacitors per

phase

0 (m-1)(m-2)/2 0

5 Voltage unbalancing Average High very small

6 Applications Motor drive

system,

STATCOM

Motor drive

system,

STATCOM

Motor drive

system, PV,

fuel cells,

battery system

When compared to diode clamped and flying capacitor inverters,

cascaded inverter requires the least number of components to achieve the

same number of voltage levels. The implementation costs of the FCMLI and

CMLI are almost same but lower by fifteen percentages than that of DCMLI.

From the overall comparison it is found that the cascaded multilevel inverter

topology is the most promising one. Cascaded inverters provide a

compounding of voltage levels leads to lower harmonic distortion avoids

60

single isolated voltage sources and constructed with the low rating power

devices which are commercially market ready.

3.3 CASCADED MULTILEVEL INVERTERS

There is a growing interest in multilevel topologies since they can

extend the application of power electronics systems to higher voltages and

power ratios. Multilevel inverters are the most attractive technology for the

medium to high voltage range, which includes motor drives, power

distribution, power quality and power conditioning applications. A cascaded

multilevel inverter by Corzine et al (1999) Liu et al (2006) consists of a series

of H-bridge inverter units. The general function of this multilevel inverter is

to synthesize a desired voltage from several separate DC sources, which may

be obtained from batteries, fuel cells, or solar cells. A particular advantage of

this topology is that the modulation, control and protection requirements of

each bridge are modular. The cascaded inverter has been largely studied and

used in the various fields such as drives, transmission system and power

conditioning Corzine et al (2002).

3.3.1 Special Features of Cascaded Multilevel Inverter

1. The series structure allows a scalable, modularized circuit

layout and packaging since each bridge has the same

structure.

2. Requires the least number of components among all

multilevel converters to achieve the same number of voltage

levels without no extra clamping diodes or voltage balancing

capacitors.

61

3. Soft switching techniques can be implemented which reduces

switching losses and device stresses.

4. Switching redundancy for inner voltage levels is possible

because the phase voltage output is the sum of each bridge’s

output.

5. Potential of shock is reduced due to the separate DC sources.

3.4 PRINCIPLE OF OPERATION OF CASCADED

MULTILEVEL INVERTER

A relatively new power converter structure, cascaded-inverters with

separate DC sources is introduced here. This new converter can avoid extra

clamping diodes or voltage balancing capacitors. Figure 3.2 shows the basic

structure of the cascaded inverters with SDC for three phase configuration.

Each SDC is associated with a single phase full bridge inverter. The AC

terminal voltages of different level inverters are connected in series. The

phase output voltage is synthesized by the sum of four inverter outputs. Each

single-phase full bridge inverter can generate three level outputs, +Vdc, 0, and

-Vdc. This is made possible by connecting the DC sources sequentially to the

AC side via the four semiconductor power devices.

Each level of the full bridge converter consists of four switches.

Using the top level as the example, by turning ON S1 and S4, yields

V1 = +Vdc. By Turing ON S2 and S3, yields V1 = -Vdc. Turning OFF all

switches yields Vdc = 0. Similarly, the AC output voltage at each level can be

obtained in the same manner. Minimum harmonic distortion can be obtained

by controlling the conducting angles of switches at different inverter levels.

62

Figure 3.2 Three phase Y-configured cascaded inverter

The simulation work mainly focuses on

1. The comparison between different levels of three phase

Cascaded Multilevel Inverters based on the proposed novel

SVPWM technique discussed in the previous chapter.

2. The comparison is done on the basis of output Total

Harmonic Distortion, fundamental and harmonic of the rms

voltage and input DC utilization.

3. Simulation of single phase CMLI inverter is not presented

since the proposed work mainly focuses on the three phase

inverter for high power industrial drive applications.

The most important aspect which sets the cascaded H Bridge apart

from other multilevel inverters is the capability of utilizing different DC

voltages on the individual H bridge cells.

In two level PWM, the switching frequency is always equal to the

carrier frequency for modulation indices less than unity. In the multilevel

63

PWM, the switching frequency can be less than or greater than the carrier

frequency and is a function of the displacement angle between the carrier set

and the modulation waveform discussed by Holmes et al (2001) Kim et al

(1995).

The general structure of the multilevel converter is to synthesize a

near sinusoidal voltage from several levels of DC voltages. As more steps are

added to the waveform, the harmonic distortion of the output wave decrease,

approaching zero as the number of levels increases.

3.5 DIFFERENT LEVELS OF SINGLE PHASE CMLI

TOPOLOGY

The single phase inverters find wide applications in low power

applications. It is not an economical solution to use multilevel inverters for

low power applications where square wave or quasi square wave inverters are

preferred. To understand the operating principle of cascaded multilevel

inverter different levels of single phase inverter is presented.

3.5.1 Single phase Three Level CMLI Topology

A single phase three level cascade multilevel inverter is constructed

as shown in Figure 3.3 by connecting two H bridges in series. The VDC1 and

VDC2 are the input DC sources, each separated DC source is connected to a

single phase full bridge inverter. The output phases of inverter 1 are

connected to the DC input points of the corresponding phase of inverter 2

switches. The AC output of each of the different level full bridge inverters are

connected in series such that the synthesized voltage waveform is the sum of

the individual inverter outputs. The phase voltage of any phase of inverter 2

attains a voltage of V02 when i) the top switch of that leg in inverter 2 is

turned ON, and ii) the bottom switch of the corresponding leg in inverter 1 is

turned ON.

64

Figure 3.3 Structure of single phase three level cascaded multilevel

inverter

Similarly, the phase voltage of any phase in inverter 1 attains a

voltage of V01 when i) the top switch of that leg in inverter 1 is turned ON,

and ii) the top switch of the corresponding leg in inverter 2 is turned ON.

Thus the switches Sa1,Sa4,Sa1’ and Sa4’are turned ON to get an output voltage

of VDC (i.e.VDC1+VDC2) and Sa3, Sa2, Sa3’, Sa2’ to get –VDC on the output. The

output voltages are

V=0: V=VDC/2: V=VDC (3.1)

3.5.2 Single Phase five Level CMLI Topology

In five level cascaded multilevel inverter, four separate DC sources

(n-1) are used. Thus four full bridge inverters are connected in series to obtain

the five levels of output as 0, VDC, 2VDC, 3VDC and 4VDC. The H bridges are

65

named as A, B, C and D. Figure 3.4 shows the structure of a single phase five

level cascaded multilevel inverter. The switching pattern of the power

switches in each H bridge is same as described for the single phase three level

cascaded inverter except the switches are progressed up to four bridges from

bridges A to D.

Figure 3.4 Structure of single phase five level cascaded multilevel

inverter

3.5.3 Single Phase Seven Level CMLI Topology

In seven level cascaded multilevel inverters a total of six separate

(n-1) DC sources are used. Six full bridge inverters are connected in series to

form the seven level structures. The output levels include 0, VDC/6, VDC/3,

VDC/2, 2VDC/3, 5VDC/6 and VDC

66

Figure 3.5 Structure of single phase seven level cascaded multilevel

inverter

3.6 THREE PHASE FIVE LEVEL CMLI

The three phase three level cascaded multilevel inverter is

constructed by combining the H bridges of (n-1) numbers. The three phase

output is obtained by combining the H bridges for individual phases as shown

in Figure 3.6.The individual H bridges are powered by separate DC sources.

Each SDC is associated with a single-phase full-bridge inverter. The AC

terminal voltages of different level inverters are connected in series.

67

Figure 3.6 Structure of three phase five level cascaded multilevel

inverter

The phase output voltage is synthesized by the sum of four H bridge

inverter’s outputs, i.e., Van = V1 + V2 + V3 +V4. Each single-phase full bridge

inverter can generate three level outputs, +VDC, 0, and -VDC. This is made

possible by connecting the DC sources sequentially to the AC side via four

power semiconductor power devices. Each level of the full-bridge inverter

consists of four switches, S1, S2, S3 and S4. Using the top level as the example,

turning ON S1 and S4, yields V1 = +VDC. Turing ON S2 and S3, yields V1 = -

VDC. Turning OFF all power switches yields VDC = 0. Similarly, the AC

output voltage at each level can be obtained in the same manner. Minimum

68

harmonic distortion can be obtained by controlling the conducting angles by

adopting correct control scheme at different inverter levels.

3.7 THREE PHASE SEVEN LEVEL CMLI

The three phase seven level cascaded multilevel inverter is

constructed by combining the six H bridges i.e. (n-1) numbers. The three

phase output is obtained by combining the H bridges for individual phases

shown as in Figure 3.7.The individual H bridges are powered by separate DC

sources. Each SDC is associated with a single-phase full-bridge inverter. The

output AC terminal of each inverter is connected in series to obtain the seven

levels. The stepped AC output voltages are obtained across the individual

phases by applying the proper gating signals for the individual power

switches. The output magnitude depends on the voltage level of the separate

DC sources.

Figure 3.7 Three phase seven level cascaded multilevel inverter

69

The pulse generation algorithms are modeled and the pulses are

generated for each level of cascaded topology. The pulse patterns are verified.

Once the pulse sequence is correct the pulses are fed to the power switches

and the stepped output voltages are obtained across the individual phases. The

modeling and simulation of the proposed control algorithm is described in the

forthcoming topic.

3.8 MATLAB/SIMULINK MODELING AND SIMULATION OF

CASCADED MULTILEVEL INVERTERS

The goal of the drive system is to perform highly efficient power

conversion, sustain the ease and flexibility in the control method, reliability

for wide range of operation. This is critical for important drive applications.

Some additional advantages of the motor drive systems using the cascade

inverter are redundant switching operation to balance battery use, worst case

operability which maintains operation at reduced performance. The separate

DC sources can be switched on by using various ways to synthesize the

output voltage, thus enhancing the drive system operability and system

management flexibility. The cascaded H-bridge has drawn considerable

interest since the mid 1990s, and has been used for ASD and reactive power

compensation. The modular structure provides advantages in power

scalability and maintenance and fault tolerance can be achieved by bypassing

the fault modules.

MATLAB is a high performance language for technical computing.

It integrates computation, visualization, and programming in an easy to use

environment where problems and solutions are expected in familiar

mathematical notation. MATLAB is an interactive system whose basic data

element is an array that does not require dimensioning. This allows solving

many technical problems, especially those with matrix and vector

formulations in a fraction of time.

70

3.8.1 Single Phase Three Level CMLI

In order to obtain the three level cascaded inverter configuration the

two H bridges are connected in series as shown in Figure 3.8 in the

MATLAB/SIMULINK environment. The output of the first H bridge is

connected in series with the second bridge. The switching pulses for the

power switches in the H bridge is provided by the four pulse generation units

from P0 to P2. For the second H bridge the pulse generation units P5 to P7

provides the switching pulses. The individual pulse generation units will have

its own subsystems interlinked with other pulse generation units to avoid the

short circuit problems among the switches present in the same leg. For the

positive half cycle of the stepped output ac voltage the power switches M0,

M3, M4 and M7 are turned ON with the suitable firing pulses. For the negative

half cycle of the output ac the switches M1, M2, M5 and M6 are turned ON

with suitable firing pulses. The power circuit and pulse circuits are as shown

in Figure 3.8.

Figure 3.8 MATLAB/SIMULINK model of three level CMLI

The input pulse patterns applied to the respective power switches

and the generated stepped output AC voltage are captured using the scopes at

the appropriate points on the circuit.

71

3.8.2 Single Phase Five Level CMLI

The MATLAB/SIMULINK model of a single phase five level

CMLI is shown in Figure 3.9. It consists of four single phase H bridge

inverter connected in series. The individual switch is supplied with the firing

pulses from pulse generation subsystem model which are all interconnected to

avoid the short circuit problem among the switches and the bridges. The

interconnection of various levels and the subsystem for pulse generation is as

shown in Figure 3.9. The stepped output voltage across the output terminals

are capture with the aid of scope in MATLAB/SIMULINK environment.

In the similar way the higher levels such as 7, 9, 11 and 13 were

modeled and the subsystems for pulse generation were developed and the

output waveforms are analyzed. As the level increases the obtained output

voltage follows the pattern of sinusoidal, but in real time implementation the

complexity involved is more hence the higher level multilevel inverters are

not presented here.

Figure 3.9 MATLAB/SIMULINK model of five level CMLI

72

3.9 THREE PHASE THREE LEVEL CMLI

In many practical applications the power requirement is very high.

For high power applications, single phase is not sufficient to cater the load

requirements. For high power application like electrical drives three phase

inverters are required, therefore simulations and modeling are done for

different levels of three phase cascaded multilevel inverter.

Figure 3.10 shows the three phase three level inverter configuration. The three

single phase inverters are bundled to obtain the three phase inverter topology.

The switching pulse sequence decides the phase sequence and the magnitude

of the inverters output.

Figure 3.10 MATLAB/SIMULINK model of three phase three level

CMLI

To construct the three level inverter (n-1) number of H bridges are

connected in cascaded manner. The switching pulses for the individual power

switches are generated with the pulse generating blocks as shown in

Figure 3.10. There are twenty four pulse generating units which feeds the

pulses to the eight switches in each phase. The pulse generating blocks are

73

interlinked such that no two switches in the same leg get triggered

simultaneously and in the same way the switches at different legs. This avoids

the source short circuit problem and the phase to phase short circuits. The

three phase output phase voltages as well as the switching pulses can be

captured for various magnitudes and different load conditions with the aid of

respective scope connected across the points. The modeling were done for

different levels up to thirteen level of three phase cascaded multilevel inverter

topology and the results were analyzed, considering the cost factor the main

thrust is given for the reduction of output percentage THD for three and five

levels alone.

3.10 FOURIER SERIES ANALYSIS FOR THREE PHASE

WAVEFORM

The various levels of cascaded configuration is modeled in

MATLAB/SIMULINK environment to confirm the obtained results the

obtained waveforms are subjected Fourier analysis, since the obtained

waveforms are non sinusoidal one discussed Boys et al (1990). The phase

sequence of three phase output voltage is assumed as A, B and C. The

instantaneous line to line voltage Vab can be expressed in Fourier series

Vab= 2

0a+

¥

n n

n=1

(a cos(nωt) + b sin(nωt))∑ (3.2)

Due to the quarter- wave symmetry along the x-axis both a0 and an

are zero. Assuming symmetry along the y axis at ω = π /6, and bn is defined

as

bn = -π /6 5π/6

s s

-5π/6 π /6

1-v (dωt) + v (dωt)

π⎡ ⎤⎢ ⎥⎣ ⎦∫ ∫ (3.2a)

74

by reorganizing the equation Vab is phase shifted by ω = π /6 and the even

order harmonics will become zero and gives the instantaneous line to line

voltage Vab.

Vab = s

n=1,3,5

4v nπ πsin sinn(ωt + )

nπ 3 6

∞∑ (3.3)

Both Vbc and Vca are phase shifted from Vab by 120 o and

240 o respectively.

Vbc= s

n=1,3,5

4v nπ πsin sinn(ωt - )

nπ 3 2

∞∑ (3.4)

Vca= s

n=1,3,5

4v nπ 7πsin sinn(ωt - )

nπ 3 6

∞∑ (3.5)

In the above Equations triplen harmonics (n= 3, 6, 9, 12) would be

zero in the output line to line voltages.

The line to line rms voltage can be found from the Equation

VL =

1 / 22 π / 3

2

0

2d (ω t )

s2 πv

⎡ ⎤⎢ ⎥⎣ ⎦∫ (3.6)

=s

v3

2 = 0.8165Vs (3.7)

The rms of nth

component line voltage is

VLn=s4v nπ

sin32nπ

(3.8)

75

For n=1, represents the fundamental rms line voltage

VL1= osin60π2

4Vs (3.9)

= 0.7797 Vs (3.10)

The rms value of line to neutral voltage i.e. phase voltage can be

found from the line voltage component

Vp= LV

3 (3.11)

= s2V

3 (3.12)

= 0.4714 Vs (3.13)

The output THD component can be found from the equation

THD = L1

212

1L

2

L

V

)V(V − (3.14)

% THD = L1

212

1L

2

L

V

)V(V − x 100 (3.15)

Equation 3.15 gives the percentage THD for the output voltage of

the multilevel inverter system. The above equations are incorporated in the

MATLAB/SIMULINK environment to assess the output voltage of the

proposed algorithm for the cascaded multilevel inverter topology.

76

3.11 MODELING OF PROPOSED SVPWM PULSE GENERATION

FOR MULTILEVEL INVERTER

Waveforms of practical inverters are non sinusoidal and contain

higher magnitude of certain lower order harmonics. For low and medium

power applications, square wave and quasi square waveforms may be

acceptable, but for high power applications sinusoidal waveforms with lower

distortions are required. Harmonic contents present in the output of DC to AC

inverters can be eliminated either by using filter circuit or by employing pulse

width modulation circuits. Use of filters has the disadvantages of larger unit

size, increased losses and hence the poor efficiency which results in higher

cost for realization, whereas use of PWM techniques reduces the filter

requirements to minimum or to zero, depending upon the type of applications

and the control technique employed for the generation of firing pulses for the

power switches and depending upon the type of application. Harmonics are

divided into voltage and current harmonics. Current harmonics is usually

generated by the harmonics contained in the voltage supply and depends on

the type of load such as resistive load, inductive and capacitive type load.

Both harmonics can be generated by either the source or the load side.

Traditional two level high frequency PWM inverters have several problems

associated with high frequency switching, which produces high dv/dt stress

across the power switches. While employing the certain control techniques to

the multilevel inverters the output voltage harmonics are reduced significantly

when compared to the conventional high frequency PWM techniques. Here

the proposed SVPWM technique is implemented in MATLAB/ SIMULINK

and the output waveforms were presented for different levels. The steps

involved for implementation of the proposed SVPWM technique was already

discussed in the previous chapter.

77

Figure 3.11 MATLAB/SIMULINK model of proposed SVPWM block

The equations involved in the proposed SVPWM pulse generation

for multilevel inverter configuration are incorporated in the

MATLAB/SIMULINK blocks as shown in Figure 3.7. Here SVPWM signals

are generated based on the sampled amplitude of reference phase voltages.

The crossing of the individual references are sorted as first cross, second cross

and third cross and the final switching periods are obtained as Tga, Tgb and

Tgc. The offset voltage is added to the reference phase voltages and referred as

modified SVPWM technique for different levels of cascaded multilevel

inverter and the pulses obtained are shown in subsequent sections.

3.12 THREE PHASE THREE LEVEL CASCADED MULTILEVEL

INVERTER WITH PROPOSED SVPWM

The individual H bridges are modelled and it is connected such that

the three phase three level cascaded multilevel inverter configuration is

obtained and the pulse generation circuit is linked with the power circuit

block. The model used for simulation is as shown in Figure 3.12. The

78

simulation is done for resistive load. The output waveforms associated with

this model is presented in the subsequent sections.

Figure 3.12 MATLAB/SIMULINK model of three phase three level

CMLI with proposed SVPWM

3.13 THREE PHASE FIVE LEVEL CASCADED MULTILEVEL

INVERTER WITH PROPOSED SVPWM

The individual H bridges are modelled with the proposed control

technique and it is connected such that the three phase five level cascaded

multilevel inverter configuration is obtained and the pulse generation circuit is

linked with the power switches block. The model used for simulation is as

shown in Figure 3.13.

79

Figure 3.13 MATLAB/SIMULINK model of three phase five level

cascaded multilevel inverter with proposed SVPWM

3.14 SIMULATION RESULTS

3.14.1 Three Phase Three Level CMLI with Proposed SVPWM

The simulation is done with the SVPWM technique and the carrier

frequency is varied in between 3 to 35 kHz and after analyzing the output

parameters for the different frequencies the carrier frequency is fixed at 5 kHz

where the output shows the optimum results in terms of output THD

discussed by Fei Wang (2002). The simulation is done for the output supply

frequency of 50Hz and the voltage of 100V. The same control technique is

applied for different levels of three phase cascaded configurations. For the

three level configuration the simulated three phase voltage waveforms are as

shown in Figure 3.10. The line voltage is shown in Figure 3.14. The phase

sequence is A, B and C. The output waveform confirms the proper phase

displacements and steady magnitude throughout the simulation profile

without any transients.

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Figure 3.14 Simulated output phase voltage waveform for three phase

three level CMLI

Figure 3.15 Simulated output line voltage waveform for three phase

three level CMLI

3.14.2 Three Phase Five Level CMLI with Proposed SVPWM

The simulation is done for different levels in order to obtain the

optimum solution on the quality of the output waveforms. The same control

technique is used to simulate the different levels with different carrier

frequencies irrespective of the levels, 5 kHz results better performance when

compared to other carrier frequencies. Therefore the same carrier frequency is

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considered for the simulation irrespective of the levels of the cascaded

configuration.

The offset voltage waveform for the proposed five level cascaded

configuration is as shown in Figure 3.16. Figure 3.17 shows the effective

voltage waveforms obtained from the proposed SVPWM method for the

individual phase. The phase sequence is A, B and C indicated in red, green

and blue respectively.

Figure 3.16 OFFSET voltage waveform

Figure 3.17 Effective voltage waveform for five level with four carriers

Time (Seconds)

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(V)

Time (Seconds)

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Figure 3.18 The four triangular waveforms and the time equivalents of

the phase voltages

Figure 3.19 Output phase voltage waveforms

The time equivalents for individual phase voltages are obtained for

five level cascaded multilevel inverter topology. The four reference

waveforms are generated and compared with the sampled phase voltages to

obtain the switching pulses for five level configuration, i.e. (n-1) carrier

waveforms as shown in Figure 3.18. The obtained output phase voltages are

as shown in Figure 3.19. The output waveform for individual phases confirms

the constant magnitude over the wide range of operation and the phase

displacements are 1200 apart from each others.

Time (Seconds)

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(V)

Time (Seconds)

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(V)

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Figure 3.20 Output line voltage waveforms

Figures 3.19 and 3.20 shows the output phase voltage and line

voltage waveforms respectively, for the three phase five level CMLI with the

proposed space vector pulse width modulation technique. The phase voltages

consist of five levels phase shifted by 1200

apart from each other.

Figure 3.21 Effective voltage waveforms

Figure 3.21 shows the effective voltage waveform. The effective

voltage is obtained from the addition of offset voltage and time equivalent of

reference phase voltages. Figure 3.22 shows the time equivalents of Tas, Tbs

and Tcs for phase voltages. The simulation is done for various modulation

index and the output voltage parameters are noted for different levels of

cascaded configurations.

Time (Seconds)

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(V)

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Figure 3.22 Time equivalents of the phase voltages

The simulation is done for various frequency and voltage levels. The

FFT analysis for 45Hz is as shown in Figure 3.23.

Figure 3.23 FFT Spectrum for output THD at 45Hz output frequency

Similarly the output wave forms are obtained for three phase seven

level, nine level and eleven level cascaded configurations, based on the

outputs the chart is plotted between the levels and the output percentage THD

as shown in Figure 3.24. From Figure 3.24 it is inferred that as the level

increases the output THD level approaches zero with the implemented

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proposed SVPWM technique, as level increases the number of power

switches required to construct the power circuit will also get increased. The

control of individual switches will become a complex issue and it is not an

economical solution for the power quality issues.

Figure 3.24 Percentage THD Vs CMLI various levels

3.15 CONCLUSION

The three, five and seven levels of cascaded multi level inverters are

modeled and simulated using MATLAB/SIMULINK model for different

carrier frequencies and the corresponding values of total harmonic distortion

were obtained and analyzed for magnitude and linearity. The carrier

frequency with 5 kHz yields better results in terms of the output THD and it is

fixed for all the levels. From the values of percentage total harmonic

distortion it can be concluded that as the number of levels of the inverter

increases the percentage of the output THD value decreases. As the number of

levels reach infinity, the output percentage of THD approaches zero but the

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cost involved in constructing the higher level inverter is high. Since the

number of power switches used to construct the power circuit increases and

hence the complexity in generating the firing pulses for the individual power

switches.

Five level inverters have more advantages than the standard two

level inverters. AC link voltage harmonics are lower due to increase in output

voltage levels. The cascaded inverter does not require any voltage balancing

capacitors on the input side and the high voltage fast recovery diodes are not

required across the power switches. Hence the three phase five level cascaded

multilevel inverter is considered for hardware implementation. Hence the

output percentage total harmonics distortion is optimized by the proposed

SVPWM technique effectively without any additional cost on the hardware

fabrication. Based on the simulation results obtained a hardware prototype

model of an induction motor drive with a three phase five level cascaded

multilevel inverter is constructed the output parameters are analyzed.