chap8-mos memory and storage circuits

7/27/2019 Chap8-MOS Memory and Storage Circuits

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Jaeger/Blaloc Microelectronic Circuit DesignChap 8 - 1

Chapter 8

MOS Memory and Storage Circuits

Microelectronic Circuit Design

Richard C. JaegerTravis N. Blalock


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Chapter Goals

Overall memory chip organization

Static memory circuits using the six-transistor cell

Dynamic memory circuits

Sense amplifier circuits used to read data from memorycells

Learn about row and address decoders

Implementation of CPU registers via flip-flops

Pass transistor logic Read Only Memory


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A 256-Mbit Memory Chip

The figure shows theblock structure of a 256-Mb memory

There are sets of column

and row decoders that areused for memory arrayselection

The column decoder splitsthe memory into upperand lower halves

The row decoder andwordline drivers bisecteach 32-Mb subarrayNote that the basic building block for this

memory is a 128Kb cell


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A 256-Mbit Memory Chip

The memory blockdiagram contains 2M+Nstorage locations

When a bit has been

selected, the set of senseamplifiers are used toread/write to thememory location

Horizontal rows arereferred to as wordlines,whereas the verticallines are called bitlines


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Static Memory Cells

Inverters configured as shown in the above figureform the basic static storage building block

These cross-coupled inverters are often referred toas a latch

The circuit uses positive feedback


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Static Memory Cells VTC

The previous latch has

only two stable states

and is termed bistable

However, it is possiblefor it to be held at an

unstable equilibrium

point where slight

changes in the voltagewill cause it to latch in

one of the stable states


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The 6-T Cell

With the addition of two control transistors it is

possible to create the 6-T cell which stores both

the true and complemented values of the data


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The Read Operation of a 6-T Cell

Initial state of the 6-T cell storinga 0 with the bitlines initialconditions assumed to VDD/2

Conditions after the WLtransistors have beenturned on


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Final read state condition of

the 6-T cellWaveforms of the 6-T

cell read operation


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Reading a 6-T cell that is storing a 1 follows the

same concept as before, except that the sources

and drains of the WL transistors are switched

Note that the delay is approximately 20ns for this

particular cell


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The Write Operation of a 6-T Cell

It can be seen that not much happens while writing a 0

into a cell that already stores a 0


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The Write Operation of a 6-T Cell

While writing a 0 to a cell that is storing a 1, the

bitlines must be able to overpower the output drive of

the latch inverters to force it to store the new condition


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Dynamic Memory Cells

The 1-T cell uses a capacitor for its storage element (data

is represented as either a presence or absence of a charge)

Due to leakage currents of MA, the data will eventually be

corrupted, hence it needs to be refreshed


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Data Storage in a 1-T Cell

Storing a 0

Storing a 1


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Notice that the voltage stored on the storage

capacitor on the previous slide does not reach VDD

It instead is determined by the following:

VC =VG VTN

VC =VGVTO + VC + 2F

2F( )[ ]


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To read a DRAM cell, the bitline is precharged to

either VDD

or VDD/2, and then M

Ais turned on


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The charge stored on CCwill be shared with C

BL

through the process of charge sharing, where the

read voltage varies slightly

Normally CBL>> C

C, and the charging time constant

is:

VF =CBLVBL +CCVC

CBL +CCVBL

= RONCBLCC

CBL +CCRONCC


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The Four-Transistor (4-T) Cell

Since the 6-T SRAM provides a large signal current drive

to the sense amplifier, it generally has shorter a access

time as compared to a DRAM

The 4-T DRAM cell is an alternative that increases accesstime, and automatically refreshes itself


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Sense Amplifiers

Sense amplifiers are used to detect the small

currents that flow through the access transistors or

the small voltage differences that occur during

charge sharing


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A Sense Amplifier for the 6-T Cell

MPCis the precharge

transistor whose main

purpose is to force the

latch to operate at the

unstable point

previously mentioned


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Sense Amplifier Example

For the figure on the previous slide, find the currents in thelatch transistors when M

PCis turned on under the following

conditions:

VDD = 5V

W

L

All =2

1

NMOS:

Kn

'= 25A/V

2

VTO

=1V

= 0.5V1/ 2

2F= 0.6V V

VVV

VAK

PMOS

F

TO

n

6.02

75.0

1

/10

:

2/1

2'

=

=

=

=


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Since the output voltage should equal on both sides of the

latch when MPC

is on, it is known that VGS

= VDS

for the latch

NMOS devices and VSG

= VSD

for the latch PMOS devices.

Therefore these transistors are saturated Due to the symmetry of the situation, the drain currents are

equal giving the following:Kp

'

2

W

L

VSG +VTP( )

2=Kn

'

2

W

L

VGS VTN( )

2

1

2

10A

V2

2

1

5VO 1( )

2=

1

2

25A

V2

2

1

VO 1( )

2

1.5VO2+ 3VO 13.5 = 0VO = 2.162V


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The drain currents are then found by:

Note that the PMOS and NMOS drain currents are

equal

The power dissipation is given by:

iD =1

2

25A

V2

2

1

2.1621( )

2= 33.8A

( )( ) mWVAViP DDD 338.058.3322 ===


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A Sense Amplifier for the 1-T Cell

The same sense

amplifier used in the

6-T cell can be used

for the 1-T cell inmanner shown in the

figure


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Sense Amplifier for the 1-T Cell

The sense amplifier works the same as it did for the 6-T

cell, but takes longer to reach steady state after precharge


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The Boosted Wordline Circuit

Obviously it is desired to have a fast access in

many DRAM applications. By driving the

wordline to a higher voltage (referred to as a

boosted wordline), say 5V instead of 3V, it ispossible to increase the amount of current supplied

to the storage capacitors


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Clocked CMOS Sense Amplifiers

The sense amplifier can definitely be a major source of

power dissipation, but by using a clocking scheme, it is

possible to reduce the power dissipated


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Clocked CMOS Sense Amplifiers

Clocking the previous

circuit in the manner

shown in the figure will

eliminate static currents

in the latch during the

precharge state, and only

transient currents will

appear


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Address Decoders

The following figures are examples of commonly used

decoders for row and column address decoding

NMOS NOR Decoder NMOS NAND Decoder


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Address Decoders

Complete 3-bit domino

CMOS NAND decoder


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Address Decoders

3-bit column data

selector using pass-

transistor logic


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Read-Only Memory (ROM)

ROM is often needed in digital systems such as:

Holding the instruction set for a microprocessor

Firmware

Calculator plug-in modules Cartridge style video games


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The basic structure ofthe NMOS static ROMis shown in the figure

The existence of an

NMOS transistor meansa 0 is stored at thataddress otherwise a 1is stored

The major downfall tothis particular circuit isthat it dissipates a lot ofpower


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The domino

CMOS ROM is

one technique

used to lower theamount of power

dissipation


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Another ROM

option is the

NAND array

ROM whichcan be directly

used with a

NAND decoder


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The main problem with these previous ROMs is that they

must be designed at the mask level, meaning that it is not a

versatile product.

To solve this problem, the programmable ROM (PROM)was introduced

The standard PROM cannot be erased, so the erasable

ROM (EPROM), and later, electrically erasable ROM

(EEPROM) were introduced

High density flash memories allow for electrical erasure

and reprogramming of memory cells


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RS Flip-Flop

The reset-set (RS) flip-flop can be easily realized by using

either two cross-coupled NOR or NAND gates

The RSFF has the following truth tables

R S Q Q

0 0 Q Q

0 1 1 0

1 0 0 1

1 1 0 0

NOR RSFF

R S Q Q

0 0 Q Q

0 1 0 1

1 0 1 0

1 1 1 1

NAND RSFF


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RS Flip-Flop

NOR RSFF

NAND RSFF


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RS Flip-Flop

Simplified RS flip-flop


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D-Latch using T-Gates

A very important circuit of digital systems is the D-Latchwhich is used for a D Flip-Flop

Whenever clock C goes high in the D-Latch, the data on Dis passed through to Q


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End of Chapter 8

chap8-mos memory and storage circuits

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