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CONTENTS

TOPIC PAGE NUMBER

Abstract 1

Introduction 2

GPP 6

Chameleon chip 9

Application 12

Design style 13

Classification of design 14

FPGA 15

Reconfigurable Architecture 19

Reconfigurable Processor 20

Advantage 25

Disadvantage 26

Comparison 27

ASIC 28

Design process 29

Conclusion 30

Future Scope 31

References 32

FAQS 33

Glossary 34

Seminar guide interaction report 35

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ABSTRACT

Chameleon chips are able to rewire themselves on the fly to create the exact hardware needed

to run a piece of software at the utmost speed. an example of such kind of a chip is achameleon chip.this can also be called a chip on demand

Highly flexible processors that can be reconfigured remotely in the field, Chameleon's chips

are designed to simplify communication system design while delivering increased

price/performance numbers. The chameleon chip is a high bandwidth reconfigurable

communications processor (RCP).it aims at changing a system's design from a remote

location.

These new chips are able to rewire themselves on the fly to create the exact hardware

needed to run a piece of software at the utmost speed. an example of such kind of a chip is a

chameleon chip. This can also be called a chip on demand Reconfigurable computing

goes a step beyond programmable chips in the matter of flexibility. It is not only possible

but relatively commonplace to "rewrite" the silicon so that it can perform new functions in a

split second. Reconfigurable chips are simply the extreme end of programmability.

The overall performance of the ACM can surpass the DSP because the ACM only

constructs the actual hardware needed to execute the software, whereas DSPs and

microprocessors force the software to fit its given architecture.

ADVANTAGES OF CHAMELEON CHIP:

can create customized communications signal processors

increased performance and channel count

can more quickly adapt to new requirements and standards

lower development costs and reduce risk.

These new chips are able to rewire themselves on the fly to create the exact

hardware needed to run a piece of software at the utmost speed. an example of such kind of

a chip is a chameleon chip.this can also be called a chip on demand Reconfigurablecomputing goes a step beyond programmable chips in the matter of flexibility. It is not only

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possible but relatively commonplace to "rewrite" the silicon so that it can perform new

functions in a split second. Reconfigurable chips are simply the extreme end of

programmability.

INTRODUCTION

Today's microprocessors sport a general-purpose design which has its

own advantages and disadvantages.

Advantage: One chip can run a range of programs. That's why you don't

need separate computers for different jobs, such as crunching spreadsheets or

editing digital photos

Disadvantage: For any one application, much of the chip's circuitry isn't

needed, and the presence of those "wasted" circuits slows things down.

Suppose, instead, that the chip's circuits could be tailored specifically for the problem at

hand--say, computer-aided design--and then rewired, on the fly, when you loaded a tax-

preparation program. One set of chips, little bigger than a credit card, could do almost

anything, even changing into a wireless phone. The market for such versatile marvels would

be huge, and would translate into lower costs for users. So computer scientists are hatching

a novel concept that could increase number-crunching power--and trim costs as well. Call it

the chameleon chip. Chameleon chips would be an extension of what can already be done

with field-programmable gate arrays (FPGAS).

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The new chips can be called a "chip on demand." In practical terms, this ability can translate

to immense flexibility in terms of device functions. For example, a single device could

serve as both a camera and a tape recorder (among numerous other possibilities): you would

simply download the desired software and the processor would reconfigure itself to

optimize performance for that function.

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An FPGA is covered with a grid of wires. At each crossover, there's a switch that can be

semipermanently opened or closed by sending it a special signal. Usually the chip must first

be inserted in a little box that sends the programming signals. But now, labs in Europe,

Japan, and the U.S. are developing techniques to rewire FPGA-like chips anytime--and even

software that can map out circuitry that's optimized for specific problems.The chips still won't change colors. But they may well color the way we use computers in

years to come. it is a fusion between custom integrated circuits and programmable logic.in

the case when we are doing highly performance oriented tasks custom chips that do one or

two things spectacularly rather than lot of things averagely is used. Now using field

programmed chips we have chips that can be rewired in an instant. Thus the benefits of

customization can be brought to the mass market.

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A reconfigurable processor is a microprocessor with erasable hardware that can rewire itself

dynamically. This allows the chip to adapt effectively to the programming tasks demanded

by the particular software they are interfacing with at any given time. Ideally, the

reconfigurable processor can transform itself from a video chip to a central processing unit

(cpu) to a graphics chip, for example, all optimized to allow applications to run at the

highest possible speed. The new chips can be called a "chip on demand." In practical

terms, this ability can translate to immense flexibility in terms of device functions. For

example, a single device could serve as both a camera and a tape recorder (among numerous

other possibilities): you would simply download the desired software and the processor

would reconfigure itself to optimize performance for that function.

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Reconfigurable processors, competing in the market with traditional hard-wired chips and

several types of programmable microprocessors. Programmable chips have been in

existence for over ten years. Digital signal processors (DSPs), for example, are high-

performance programmable chips used in cell phones, automobiles, and various types of

music players.

Another version, programmable logic chips are equipped with arrays of memory cells that

can be programmed to perform hardware functions using software tools. These are more

flexible than the specialized DSP chips but also slower and more expensive. Hard-wired

chips are the oldest, cheapest, and fastest - but also the least flexible - of all the options.

GENARAL PURPOSE PROCESSOR

Processor technology relates to the architecture of the computation engine used to implement

a system's desired functionality.

General Purpose Processors: The designer of a general purpose processor or a

microprocessor builds a programmable device that is suitable for a variety of applications to

maximize the devices sold.

Single Purpose Processor: A single purpose processor is a digital circuit designed to

execute exactly one program.

Application Specific Processor: An application specific instruction set processor

(ASIP) can serve as a compromise between the general purpose processor and the single

purpose processor. As ASIP is a programmable processor optimized for a particular class of

applications having common characteristics, such as embedded control, digital-signal

processing, or telecommunications.

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Using a general purpose processor in an embedded system may result in several design

benefits. Flexibility is high because changing functionality requires changing only the

program. Time to market would be low, and unit cost would be low in small quantities

compared to designing your own processors. Performance may not be as great for some more

computation intensive applications.

Using a single purpose processor in an embedded system results in several design metric

benefits. Performance may be fast, size and power may be small, and unit cost may be low

for large quantities.

Using an ASIP in an embedded system can provide the benefit of flexibility while still

achieving good performance, power and size. Microcontrollers and digital signal processorsare two well known types of ASIPs that have been used for several decades. A

microcontroller is a microprocessor that has been optimized for embedded control

applications.

Digital signal processors (DSPs) are another common type of ASIP. A DSP is a

microprocessor designed to perform common operations on digital signals, which are the

digital encoding of analog signals likes video and audio.

We will be more concentrating on general purpose processors.

Basic Architecture

A general purpose processor consists of a data path and a control unit tightly linked with a

memory.

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Datapath:

The datapath consists of the circuitry for transforming data from and for storing temporary

data. It consists of an arithmetic logic unit (ALU) capable of transforming data through

operations such as addition, subtraction, logical AND, logical OR, inverting and shifting.

The datapath also contains registers capable of storing temporary data. Processors are

typically distinguished by their size, and we usually measure the size of the processor as the

bit width of the datapaths components. Common processor sizes include, 4-bit, 8-bit, 16-bit,

32-bit and 64-bit. The processor which we will be using for our robot construction is a 16-bit

general purpose processor.

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In some cases a particular processor may have different sizes among its registers, ALU,

internal bus or external bus. For example, a processor may have a 16-bit internal bus, ALU

and registers, but have old 8-bits of external but to reduce the number of pins on the

processor's IC.

The control unit consists of circuitry for retrieving program instructions and for moving data

to, from and through the data path according to those instructions.

For each instruction the controller typically sequences through several stages, such as

fetching the instruction from memory, decoding it, fetching operands, executing the

instruction in the datapath, and storing the results. Each stage may consists of one or more

clock cycles. A clock cycle is usually the longest time required for data to travel from oneregister to another.

Memory:

While registers server a processor's short-term storage requirements, memory server the

processor's medium and long-term information-storage requirements. We can classify storage

information as either program or data.

Program information consists of the sequence of instruction that cause the processor to carry

out the desired system functionality. Data information requests the values being input, output

and transformed by the program.

CHAMELEON CHIPS

Highly flexible processors that can be reconfigured remotely in the field, Chameleon's chips

are designed to simplify communication system design while delivering increased

price/performance numbers. The chameleon chip is a high bandwidth reconfigurable

communications processor (RCP).it aims at changing a system's design from a remote

location.

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needed to run a piece of software at the utmost speed. an example of such kind of a chip is a

chameleon chip. This can also be called a chip on demand Reconfigurable computing

goes a step beyond programmable chips in the matter of flexibility. It is not only possible

but relatively commonplace to "rewrite" the silicon so that it can perform new functions in a

split second. Reconfigurable chips are simply the extreme end of programmability.

The overall performance of the ACM can surpass the DSP because the ACM only

constructs the actual hardware needed to execute the software, whereas DSPs and

microprocessors force the software to fit its given architecture.

One reason that this type of versatility is not possible today is that handheld gadgets are

typically built around highly optimized specialty chips that do one thing really well. These

chips are fast and relatively cheap, but their circuits are literally written in stone -- or at least

in silicon. A multipurpose gadget would have to have many specialized chips -- a costly and

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clumsy solution. Alternately, you could use a general-purpose microprocessor, like the one

in your PC, but that would be slow as well as expensive. For these reasons, chip designers

are turning increasingly to reconfigurable hardwareintegrated circuits where the

architecture of the internal logic elements can be arranged and rearranged on the fly to fit

particular applications.

Designers of multimedia systems face three significant challenges in today's ultra-

competitive marketplace: Our products must do more, cost less, and be brought to the

market quicker than ever. Though each of these goals is individually attainable, the hat trick

is generally unachievable with traditional design and implementation techniques.

Fortunately, some new techniques are emerging from the study of reconfigurable computing

that make it possible to design systems that satisfy all three requirements simultaneously.

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Although originally proposed in the late 1960s by a researcher at UCLA, reconfigurable

computing is a relatively new field of study. The decades-long delay had mostly to do with

a lack of acceptable reconfigurable hardware. Reprogrammable logic chips like field

programmable gate arrays (FPGAs) have been around for many years, but these chips have

only recently reached gate densities making them suitable for high-end applications. (The

densest of the current FPGAs have approximately 100,000 reprogrammable logic gates.)

With an anticipated doubling of gate densities every 18 months, the situation will only

become more favorable from this point forward.

The primary product is a ground station equipment for satellite communications. This

application involves high-rate communications, signal processing, and a variety of network

protocols and data formats. Chameleon chips are chips whose circuitry can be tailored

specifically for the problem at hand. Chameleon chips would be an extension of what can

already be done with field-programmable gate arrays (FPGAS). An FPGA is covered with a

grid of wires. At each crossover, theres a switch that can be semipermanently opened or

closed by sending it a special signal. Usually the chip must first be inserted in a little box that

sends the programming signals. But now, labs in Europe, Japan, and the U.S. are developing

techniques to rewire FPGA-like chips anytimeand even software that can map out circuitry

thats optimized for specific problems.

The chips still wont change colors. But they may well color the way we use computers in

years to come. It is a fusion between custom integrated circuits and programmable logic.in

the case when we are doing highly performance oriented tasks custom chips that do one or

two things spectacularly rather than lot of things averagely is used. Now using field

programmed chips we have chips that can be rewired in an instant. Thus the benefits of

customization can be brought to the mass market.

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ADVANTAGES AND APPLICATIONS

Its applications are:

data-intensive Internet

DSP

wireless basestations

voice compression

software-defined radio

high-performance embedded telecom and datacom applications

Its advantages are:

can create customized communications signal processors

increased performance and channel count

can more quickly adapt to new requirements and standards

lower development costs and reduce risk.

DESIGN STYLES

ASIC design starts with an initial concept of the required IC parts. Early in this product

conceptualization phases, it is important to decide the design style that will be most suitable

for the design and validation of

The eventual ASIC chip. A design style refers to a broad method of design circuit, which

uses specific technique and technology for the design implementation and validation.

Design style are broadly into custom and semi-custom design.

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(1) Custom designs

Custom designs, as the name suggests, involve the complete design to be hand-crafted so as

to optimize the circuit for performance and/or area of given application. although this is an

expensive design styles in volume production.

(2) Semi-custom design:

The semi-custom design style limits the circuit primitives and uses pre-designed blocks

which cannot be further fine-tuned. These pre-design primitive blocks are usually

optimized, well designed, and well characterized, and ultimately help rise the level of

abstraction in the design. The pre-designed cells can be characterized and optimized for the

various process technologies that library target.

(a)Cell-Based Design:It can be based on standard-cell design, in which basic primitive cell are designed once and

available in a library for each process technology or foundry used. Each cell in library is

parameterized in terms of area, delay and power. These libraries have to be update

whenever the foundry technology changed.

(b)Array Based Design:

In contrast to cell-based designs, array-based designs uses a prefabricated matrix of non-

connected components known as sites. These sites are wired together o create the circuit

required.

(1)Classification Of Design Styles:

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(2)Classification Of Design Styles Of Semi Custom:

FPGA

One of the most promising approaches in the realm of reconfigurable architecture is a

technology called "field-programmable gate arrays." The strategy is to build uniform arrays

of thousands of logic elements, each of which can take on the personality of different,

fundamental components of digital circuitry; the switches and wires can be reprogrammed

to operate in any desired pattern, effectively rewiring a chip's circuitry on demand. A

designer can download a new wiring pattern and store it in the chip's memory, where it can

be easily accessed when needed.

Not so hard after all Reconfigurable hardware first became practical with the introduction a

few years ago of a device called a field-programmable gate array (FPGA) by Xilinx, an

electronics company that is now based in San Jose, California. An FPGA is a chip

consisting of a large number of logic cells. These cells, in turn, are sets of transistors

wired together to perform simple logical operations.

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FPGAs are arrays of logic blocks that are strung together through software commands to

implement higher-order logic functions. Logic blocks are similar to switches with multiple

inputs and a single output, and are used in digital circuits to perform binary operations.

Unlike with other integrated circuits, developers can alter both the logic functions

performed within the blocks and the connections between the blocks of FPGAs by sending

signals that have been programmed in software to the chip. FPGA blocks can perform the

same high-speed hardware functions as fixed-function ASICs, andto distinguish them

from ASICsthey can be rewired and reprogrammed at any time from a remote location

through software. Although it took several seconds or more to change connections in the

earliest FPGAs, FPGAs today can be configured in milliseconds.

Field-programmable gate arrays have historically been applied as what is called glue logic

in embedded systems, connecting devices with dissimilar bus architectures. They have often

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been used to link digital signal processorscpus used for digital signal processingto

general-purpose cpus.

The growth in FPGA technology has lifted the arrays beyond the simple role of providingglue logic. With their current capabilities, they clearly now can be classed as system-level

components just like cpus and DSPs. The largest of the FPGA devices made by the

company with which one of the authors of this article is affiliated, for example, has more

than 150 billion transistors, seven times more than a Pentium-class microprocessor. Given

today's time-to-market pressures, it is increasingly critical that all system-level components

be easy to integrate, especially since the phase involving the integration of multiple

technologies has become the most time-consuming part of a product's development cycle.

To Integrating Hardware and Software systems designers producing mixed cpu and FPGA

designs can take advantage of deterministic real-time operating systems (RTOSs).

Deterministic software is suited for controlling hardware. As such, it can be used to

efficiently manage the content of system data and the flow of such data from a cpu to an

FPGA. FPGA developers can work with RTOS suppliers to facilitate the design and

deployment of systems using combinations of the two technologies. FPGAs operating in

conjunction with embedded design tools provide an ideal platform for developing high-

performance reconfigurable computing solutions for medical instrument applications. The

platform supports the design, development, and testing of embedded systems based on the C

language.

Integration of FPGA technology into systems using a deterministic RTOS can be

streamlined by means of an enhanced application programming interface (API). The

blending of hardware, firmware, application software, and an RTOS into a platform-based

approach removes many of the development barriers that still limit the functionality of

embedded applications. Development, profiling, and analysis tools are available that can be

used to analyze computational hot spots in code and to perform low-level timing analysis in

multitasking environments.

One way developers can use these analytical tools is to determine when to design a

function in hardware or software. Profiling enables them to quickly identify functionality

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that is frequently used or computationally intensive. Such functions may be prime

candidates for moving from software to FPGA hardware. An integrated suite of run-time

analysis tools with a run-time error checker and visual interactive profiler can help

developers create higher-quality, higher-performance code in little time.

An FPGA consists of an array of configurable logic blocks that implement the logical

functions. In FPGA's, the logic functions performed within the logic blocks, and sending

signals to the chip can alter the connections between the blocks. These blocks are similar

in structure to the gate arrays used in some ASIC's, but whereas standard gate arrays are

configured and fixed during manufacture, the configurable logic blocks in new FPGA's

can be rewired and reprogrammed repeatedly in around a microsecond. One advantages of

FPGA is that it needs small time to market Flexibility and Upgrade advantages Cheap to

make .We can configure an FPGA using Very High Density Language [VHDL] Handel

C Java .FPGAs are used presently in Encryption Image Processing Mobile

Communications .FPGAs can be used in 4G mobile communication

The advantages of FPGAs are that Field programmable gate arrays offer companies the

possibility of developing a chip very quickly, since a chip can be configured by software.

A chip can also be reconfigured, either during execution time, or as part of an upgrade to

allow new applications, simply by loading new configuration into the chip. The

advantages can be seen in terms of cost, speed and power consumption. The added

functionality of multi-parallelism allows one FPGA to replace multiple ASICs.

The applications of FPGAs are in

image processing

encryption

mobile communication

memory management and digital signal processing

telephone units

mobile base stations.

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Although it is very hard to predict the direction this technology will take, it seems more than

likely that future silicon chips will be a combination of programmable logic, memory blocks

and specific function blocks, such as floating point units.

It is hard to predict at this early stage, but it looks likely that the technology will have to

change over the coming years, and the rate of change for major players in todays

marketplace such as Intel, Microsoft and AMD will be crucial to their survival.

The precise behavior of each cell is determined by loading a string of numbers into a

memory underneath it. The way in which the cells are interconnected is specified by loading

another set of numbers into the chip. Change the first set of numbers and you change what

the cells do. Change the second set and you change the way they are linked up. Since even

the most complex chip is, at its heart, nothing more than a bunch of interlinked logic

circuits, an FPGA can be programmed to do almost anything that a conventional fixed piece

of logic circuitry can do, just by loading the right numbers into its memory. And by loading

in a different set of numbers, it can be reconfigured in the twinkling of an eye.

Basic reconfigurable circuits already play a huge role in telecommunications. For instance,

relatively simple versions made by companies such as Xilinx and Altera are widely used for

network routers and switches, enabling circuit designs to be easily updated electronically

without replacing chips. In these early applications, however, the speed at which the chips

reconfigure themselves is not critical. To be quick enough for personal information devices,

the chips will need to completely reconfigure themselves in a millisecond or less. "That

kind of chameleon device would be the killer app of reconfigurable computing" These

experts predict that in the next couple of years reconfigurable systems will be used in cell

phones to handle things like changes in telecommunications systems or standards as users

travel between calling regions -- or between countries.

As it is getting more expensive and difficult to pattern, or etch, the elaborate circuitry used

in microprocessors; many experts have predicted that maintaining the current rate of putting

more circuits into ever smaller spaces will, sometime in the next 10 to 15 years, result in

features on microchips no bigger than a few atoms, which would demand a nearly

impossible level of precision in fabricating circuitry But reconfigurable chips don't need

that type of precision and we can make computers that function at the nanoscale level.

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One of the most promising approaches in the realm of reconfigurable architecture is a

technology called "field-programmable gate arrays." The strategy is to build uniform arrays

of thousands of logic elements, each of which can take on the personality of different,

fundamental components of digital circuitry; the switches and wires can be reprogrammed to

operate in any desired pattern, effectively rewiring a chip's circuitry on demand. A designer

can download a new wiring pattern and store it in the chip's memory, where it can be easily

accessed when needed.

Not so hard after all Reconfigurable hardware first became practical with the introduction a

few years ago of a device called a field-programmable gate array (FPGA) by Xilinx, an

electronics company that is now based in San Jose, California. An FPGA is a chip consisting

of a large number of logic cells. These cells, in turn, are sets of transistors wired together to

perform simple logical operations.

Evolving FPGAs

FPGAs are arrays of logic blocks that are strung together through software commands to

implement higher-order logic functions. Logic blocks are similar to switches with multiple

inputs and a single output, and are used in digital circuits to perform binary operations.

Unlike with other integrated circuits, developers can alter both the logic functions performed

within the blocks and the connections between the blocks of FPGAs by sending signals that

have been programmed in software to the chip. FPGA blocks can perform the same high-

speed hardware functions as fixed-function ASICs, andto distinguish them from ASICs

they can be rewired and reprogrammed at any time from a remote location through software.

CS2112

RCP architecture is designed to be as flexible as an FPGA, and as easy to program as a

digital signal processor (DSP), with real-time, visual debugging capability. The

development environment, comprising Chameleon's C-SIDE software tool suite and

CT2112SDM development kit, enables customers to develop and debug communication and

signal processing systems running on the RCP. The RCP's development environment helps

overcome a fundamental design and debug challenge facing communication system

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designers.In order to build sufficient performance, channel capacity, and flexibility into

their systems, today's designers have been forced to employ an amalgamation of DSPs,

FPGAs and ASICs, each of which requires a unique design and debug environment.

The RCP platform was designed from the ground up to alleviate this problem: first by

significantly exceeding the performance and channel capacity of the fastest DSPs; second

by integrating a complete SoC subsystem, including an embedded microprocessor, PCI

core, DMA function, and high-speed bus; and third by consolidating the design and debug

environment into a single platform-based design system that affords the designer

comprehensive visibility and control.

The C-SIDE software suite includes tools used to compile C and assembly code forexecution on the CS2112's embedded microprocessor, and Verilog simulation and synthesis

tools used to create parallel datapath kernels which run on the CS2112's reconfigurable

processing fabric.

In addition to code generation tools, the package contains source-level debugging tools that

support simulation and real-time debugging. Chameleon's design approach leverages the

methods employed by most of today's communications system designers. The designer

starts with a C program that models signal processing functions of the baseband system.

Having identified the dataflow intensive functional blocks, the designer implements them in

the RCP to accelerate them by 10- to 100-fold. The designer creates equivalent functions for

those blocks, called kernels, in Chameleon's reconfigurable assembly language-like design

entry language. The assembler then automatically generates standard Verilog for thesekernels that the designer can verify with commercial Verilog simulators. Using these tools,

the designer can compare testbench results for the original C functions with similar results

for the Verilog kernels. In the next phase, the designer synthesises the Verilog kernels using

Chameleon's synthesis tools targeting Chameleon technology. At the end, the tools output a

bit file that is used to configure the RCP.The designer then integrates the application level C

code with Verilog kernels and the rest of the standard C function.Chameleon's C-SIDE

compiler and linker technology makes this integration step transparent to the designer.

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The CS2112 development environment makes all chip registers and memory locations

accessible through a development console that enables full processor-like debugging,

including features like single-stepping and setting breakpoints. Before actually productising

the system, the designer must often perform a system-level simulation of the data flow

within the context of the overall system. Chameleon's development board enables the

designer to connect multiple RCPs to other devices in the system using the PCI bus and/or

programmable I/O pins.

This helps prove the design concept, and enables the designer to profile the performance of

the whole basestation system in a real-world environment. With telecommunications OEMs

facing shrinking product life cycles and increasing market pressures, not to mention the

constant flux of protocols and standards, it's more necessary than ever to have a platform

that's reconfigurable. This is where the chameleon chips are going to make its effect felt.

The Chameleon CS2112 Package is a high-bandwidth, reconfigurable communications

processor aimed at

second- and third-generation wireless base stations

fixed point wireless local loop (WLL)

voice over IP

DSL(digital subscriber line)

High end dsp operations

2G-3G wireless base stations

software defined radio

security processing

"Traditional solutions such as FPGAs and DSPs lack the performance for high-bandwidth

applications, and fixed function solutions like ASICs incur unacceptable limits Each

product in the CS2000 family has the same fundamental functional blocks: a 32-bit RISC

processor, a full-featured memory controller, a PCI controller, and a reconfigurable

processing fabric, all of which are interconnected by a high-speed system bus. The above

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mentioned fabric comprises an array of reconfigurable tiles used to implement the desired

algorithms. Each tile contains seven 32-bit reconfigurable datapath units, four blocks of

local store memory, two 16x24-bit multipliers, and a control logic unit.

BASIC ARCHITECTURE

Components:

32-bit Risc ARC processor @125MHz

64 bit memory controller

32 bit PCI controller

reconfigurable processing fabric (RPF)

high speed system bus

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programmable I/O (160 pins)

DMA Subsystem

Configuration Subsystem

More on the architecture of RPF:-

4 Slices with 3 Tiles in each. Each tile can be reconfigured at runtime

Tiles contain :

Datapath Units

Local Store Memories

16x24 multipliers

Control Logic Unit

The C-SIDE design system is a fully integrated tool suite, with C compiler, Verilog

synthesizer, full-chip simulator, as well as a debug and verification environment -- an

element not readily found in ASIC and FPGA design flows, according to Chameleon. Still,

reconfigurable chips represent an attempt to combine the best features of hard-wired

custom chips, which are fast and cheap, and programmable logic device (PLD) chips,

which are flexible and easily brought to market.

Unlike PLDs, QuickSilver's reconfigurable chips can be reprogrammed every few

nanoseconds, rewiring circuits so they are processing global positioning satellite signals

one moment or CDMA cellular signals the next, Think of the chips as consisting oflibraries with preset hardware designs and chalkboards. Upon receiving instructions from

software, the chip takes a hardware component from the library (which is stored as

software in memory) and puts it on the chalkboard (the chip). The chip wires itself

instantly to run the software and dispatches it. The hardware can then be erased for the

next cycle. With this style of computing, its chips can operate 80 times as fast as a custom

chip but still consume less power and board space, which translates into lower costs. The

company believes that "soft silicon," or chips that can be reconfigured on the fly, can be

the heart of multifunction camcorders or digital television sets.

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With programmable logic devices, designers use inexpensive software tools to quickly

develop, simulate, and test their designs. Then, a design can be quickly programmed into a

device, and immediately tested in a live circuit. The PLD that is used for this prototyping

is the exact same PLD that will be used in the final production of a piece of end

equipment, such as a network router, a DSL modem, a DVD player, or an automotive

navigation system.

The two major types of programmable logic devices are field programmable gate arrays

(FPGAs) and complex programmable logic devices (CPLDs). Of the two, FPGAs offer the

highest amount of logic density, the most features, and the highest performance FPGAs are

used in a wide variety of applications ranging from data processing and storage, to

instrumentation, telecommunications, and digital signal processing.

To overcome these limitations and offer a flexible, cost-effective solution, many new

entrants to the DSP market are extolling the virtues of configurable and reconfigurable

DSP designs. This latest breed of DSP architectures promises greater flexibility to quickly

adapt to numerous and fast-changing standards. Plus, they claim to achieve higher

performance without adding silicon area, cost, design time, or power consumption. In

essence, because the architecture isn't rigid, the reconfigurable DSP lets the developer

tailor the hardware for a specific task, achieving the right size and cost for the target

application. Moreover, the same platform can be reused for other applications.

Because development tools are a critical part of this solutionin fact, they're true enablers

the newcomers also ensure that the tools are robust and tightly linked to the devices'

flexible architectures. While providing an intuitive, integrated development environment

for the designers, the manufacturers ensure affordability as well.

RECONFIGURING THE ARCHITECTURE

Some of the new configurable DSP architectures are reconfigurable toothat is, developers

can modify their landscape on the fly, depending on the incoming data stream. This

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capability permits dynamic reconfigurability of the architecture as demanded by the

application. Proponents of such chips are proclaiming an era of "chip-on-demand," wherein

new algorithms can be accommodated on-chip in real time via software. This eliminates the

cumbersome job of fitting the latest algorithms and protocols into existing rigid hardware. A

reconfigurable communications processor (RCP) can reconfigured for different processing

algorithms in one clock cycle. Chameleon designers are revising the architecture to create a

chip that can address a much broader range of applications. Plus, the supplier is preparing a

new, more user-friendly suite of tools for traditional DSP designers. Thus, the company is

dropping the term reconfigurability for the new architecture and going with a more

traditional name, the streaming data processor (SDP).

Though the SDP will include a reconfigurable processing fabric, it will be substantially

altered, the company says. Unlike the older RCP, the new chip won't have the ARM RISC

core, and it will support a much higher clock rate. Additionally, it will be implemented in a

0.13-m CMOS process to meet the signal processing needs of a much broader market.

Further details await the release of SDP sometime in the first quarter of 2003. While

Chameleon is in the redesign mode, QuickSilver Technologies is in the test mode. This

reconfigurable proponent, which prefers to call its architecture an adaptive computing

machine or ACM, has realized its first silicon test chip. In fact, the tests indicate that it

outperforms a hardwired, fixed-function ASIC in processing compute-intensive cdma2000

algorithms, like system acquisition, rake finger, and set maintenance. For example, the

ASIC's nominal speed for searching 215 phase offsets in a basic multipath search algorithm

is 3.4 seconds. The ACM test chip took just one second at a 25-MHz clock speed to perform

the same number of searches in a cdma2000 handset. Likewise, the device accomplishes

over 57,000 adaptations per second in rake-finger operation to cycle through all operations

in this application every 52 s (Fig. 1). In the set-maintenance application, the chip is

almost three times faster than an ASIC, claims QuickSilver.

THE power of a computer stems from the fact that its behaviour can be changed with little

more than a dose of new software. A desktop PC might, for example, be browsing the

Internet one minute, and running a spreadsheet or entering the virtual world of a computer

game the next. But the ability of a microprocessor (the chip that is at the heart of any PC) to

handle such a variety of tasks is both a strength and a weaknessbecause hardware

dedicated to a particular job can do things so much faster. Recognising this, the designers of

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modern PCs often hand over such tasks as processing 3-D graphics, decoding and playing

movies, and processing soundthings that could, in theory, be done by the basic

microprocessorto specialist chips. These chips are designed to do their particular jobs

extremely fast, but they are inflexible in comparison with a microprocessor, which does its

best to be a jack-of-all-trades. So the hardware approach is faster, but using software is

more flexible.

At the moment, such reconfigurable chips are used mainly as a way of conjuring up

specialist hardware in a hurry. Rather than designing and building an entirely new chip to

carry out a particular function, a circuit designer can use an FPGA instead. This speeds up

the design process enormously, because making changes becomes as simple as downloading

a new configuration into the chip. Chameleon Systems also develops reconfigurable chips

for the high-end telecom-switching market.

A microprocessor adapting itself to the actual use and environment. Thats the way to keep

the energy consumption of future mobile companions within limits and be flexible at the

same time. Paul Heysters, who finishes his PhD-research at the University of Twente on

September 24, developed a new type of processor. His Montium is a reconfigurable

processor adapting itself towards low energy consumption. It is possible to get ten times

better performance, with ten times lower energy consumption at the same time, according to

Heysters. He did his research at the Centre for Telematics and Information Technology of the

University of Twente in The Netherlands.

Without energy-saving measures, they get real miniature stoves in your pocket, the mobile

equipment of the future. They will be packed with a lot of functions, for which users need

separate devices now. Including broadband mobile communication, GPS, navigation, camera,

audio and video, ranging to full electronic driving license and passport. Fully profit from all

these features means using a lot of energy. An application-specific chip (ASIC) would be the

most energy-economic solution, but it is not flexible at all. Thats why Heysters chooses

reconfigurability: he lets the hardware adapt itself to the use thats made of it. The Montium

in animal world a rare chameleon species- is a processor that is capable of this. And it

consumes far less power. Future mobile equipment has to, for example, be able to adapt to

the network environment it is currently working is. Do you prefer a broadband connection

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and do you happen to be in a WiFi environment, than the chip will enable a WiFi connection.

The approach Heysters chooses is a tiled one. His processor is not a huge generic one,

capable of every possible task, but it consists of tiles that can be switched on or off depending

on the desired function. Tiles are available for digital signal processing (DSP), for specific

tasks and small general purpose processors. Every type of tiles is available in a repeated

pattern.

This approach is really different from developing an economic or mobile version of a

regular processor, Heysters states. In those cases, usually some adjustments are made to the

power supply voltage or clock frequency. But in essence, the processor still is highly

overdimensioned for the tasks it has to perform. What Heysters proposes is changing the

hardware architecture based on the algorithm. This works: in a complex task like calculating

a fast Fourier Transform, the Montium performs ten times better than a generic processor for

mobile use, while it consumes ten times less energy.

Worldwide, there are efforts going on for these energy-saving strategies. The Montium

approach can be succesful in this, according to Heysters. One of the true success factors is

that good design tools become available: designers have to be able to do their work on a high

level of abstraction, without having to bother about the hardware underneath. Promising steps

have been made in the group Heysters is working in. Industry is interested in his approach,

and in fabricating a prototype chameleon-chip consisting of nine Montium tiles.

RECONFIGURABLE PROCESSORS

A reconfigurable processor is a microprocessor with erasable hardware that can rewire itself

dynamically. This allows the chip to adapt effectively to the programming tasks demanded

by the particular software they are interfacing with at any given time. Ideally, the

reconfigurable processor can transform itself from a video chip to a central processing unit

(cpu) to a graphics chip, for example, all optimized to allow applications to run at the

highest possible speed. The new chips can be called a "chip on demand." In practical

terms, this ability can translate to immense flexibility in terms of device functions. For

example, a single device could serve as both a camera and a tape recorder (among numerous

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other possibilities): you would simply download the desired software and the processor

would reconfigure itself to optimize performance for that function.

Reconfigurable processors, competing in the market with traditional hard-wired chips and

severaltypes of programmable microprocessors. Programmable chips have been in existence

for over ten years. Digital signal processors (DSPs), for example, are high-performance

programmable chips used in cell phones, automobiles, and various types of music players.

While microprocessors have been the dominant devices in use for general-purpose

computing for the last decade, there is still a large gap between the computational efficiency

of microprocessors and custom silicon. Reconfigurable devices, such as FPGAs, have come

closer to closing that gap, offering a 10x benefit in computational density over

microprocessors, and often offering another potential 10x improvement in yielded

functional density on low granularity operations. On highly regular computations,

reconfigurable architectures have a clear superiority to traditional processor architectures.

On tasks with high functional diversity, microprocessors use silicon more efficiently than

reconfigurable devices. The BRASS project is developing a coupled architecture which

allow a reconfigurable array and processor core to cooperate efficiently on computational

tasks, exploiting the strengths of both architectures.

We are developing an architecture and a prototype component that will combine a processor

and a high performance reconfigurable array on a single chip. The reconfigurable array

extends the usefulness and efficiency of the processor by providing the means to tailor its

circuits for special tasks. The processor improves the efficiency of the reconfigurable array

for irregular, general-purpose computation.

We anticipate that a processor combined with reconfigurable resources can achieve a

significant performance improvement over either a separate processor or a separate

reconfigurable device on an interesting range of problems drawn from embedded computing

applications. As such, we hope to demonstrate that this composite device is an ideal system

element for embedded processing.

Reconfigurable devices have proven extremely efficient for certain types of processing

tasks. The key to their cost/performance advantage is that conventional processors are often

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limited by instruction bandwidth and execution restrictions or by an insufficient number or

type of functional units. Reconfigurable logic exploits more program parallelism. By

dedicating significantly less instruction memory per active computing element,

reconfigurable devices achieve a 10x improvement in functional density over

microprocessors. At the same time this lower memory ratio allows reconfigurable devices to

deploy active capacity at a finer grained level, allowing them to realize a higher yield of

their raw capacity, sometimes as much as 10x, than conventional processors.

The high functional density characteristic of reconfigurable devices comes at the expense of

the high functional diversity characteristic of microprocessors. Microprocessors have

evolved to a highly optimized configuration with clear cost/performance advantages over

reconfigurable arrays for a large set of tasks with high functional diversity. By combining a

reconfigurable array with a processing core we hope to achieve the best of both worlds.

While it is possible to combine a conventional processor with commercial reconfigurable

devices at the circuit board level, integration radically changes the i/o costs and design point

for both devices, resulting in a qualitatively different system. Notably, the lower on-chip

communication costs allow efficient cooperation between the processor and array at a finer

grain than is sensible with discrete designs.

ADVANTAGES OF RECONFIGURABILITY

The term reconfigurable computing has come to refer to a loose class of embedded

systems. Many system-on-a-chip (SoC) computer designs provide reconfigurability

options that provide the high performance of hardware with the flexibility of software. To

most designers, SoC means encapsulating one or more processing elementsthat is,

general-purpose embedded processors and/or digital signal processor (DSP) coresalong

with memory, input/output devices, and other hardware into a single chip. These versatile

chips can perform many different functions. However, while SoCs offer choices, the user

can choose only among functions that already reside inside the device. Developers also

create ASICschips that handle a limited set of tasks but do them very quickly.

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The limitation of most types of complex hardware devicesSoCs, ASICs, and general-

purpose cpusis that the logical hardware functions cannot be modified once the silicon

design is complete and fabricated. Consequently, developers are typically forced to

amortize the cost of SoCs and ASICs over a product lifetime that may be extremely short

in today's volatile technology environment.

Solutions involving combinations of cpus and FPGAs allow hardware functionality to be

reprogrammed, even in deployed systems, and enable medical instrument OEMs to

develop new platforms for applications that require rapid adaptation to input. The

technologies combined provide the best of both worlds for system-level design. Careful

analysis of computational requirements reveals that many algorithms are well suited to

high-speed sequential processing, many can benefit from parallel processing capabilities,

and many can be broken down into components that are split between the two. With this in

mind, it makes sense to always use the best technology for the job at hand.

Processors are best suited to general-purpose processing and high-speed sequential

processing (as are DSPs), while FPGAs excel at high-speed parallel processing. The

general-purpose capability of the cpu enables it to perform system management very well,

and allows it to be used to control the content of the FPGAs contained in the system. This

symbiotic relationship between cpus and FPGAs also means that the FPGA can off-load

computationally intensive algorithms from the cpu, allowing the processor to spend more

time working on general-purpose tasks such as data analysis, and more time

communicating with a printer or other equipment.

RECONFIGURABLE COMPUTING

When we talk about reconfigurable computing were usually talking about FPGA-based

system designs. Unfortunately, that doesnt qualify the term precisely enough. System

designers use FPGAs in many different ways. The most common use of an FPGA is for

prototyping the design of an ASIC. In this scenario, the FPGA is present only on the

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prototype hardware and is replaced by the corresponding ASIC in the final production

system. This use of FPGAs has nothing to do with reconfigurable computing.

However, many system designers are choosing to leave the FPGAs as part of the production

hardware. Lower FPGA prices and higher gate counts have helped drive this change. Such

systems retain the execution speed of dedicated hardware but also have a great deal of

functional flexibility. The logic within the FPGA can be changed if or when it is necessary,

which has many advantages. For example, hardware bug fixes and upgrades can be

administered as easily as their software counterparts. In order to support a new version of a

network protocol, you can redesign the internal logic of the FPGA and send the

enhancement to the affected customers by email. Once theyve downloaded the new logic

design to the system and restarted it, theyll be able to use the new version of the protocol.

This is configurable computing; reconfigurable computing goes one step further.

Reconfigurable computing involves manipulation of the logic within the FPGA at run-time.

In other words, the design of the hardware may change in response to the demands placed

upon the system while it is running. Here, the FPGA acts as an execution engine for a

variety of different hardware functions some executing in parallel, others in serial

much as a CPU acts as an execution engine for a variety of software threads. We might even

go so far as to call the FPGA a reconfigurable processing unit (RPU).

Reconfigurable computing allows system designers to execute more hardware than they

have gates to fit, which works especially well when there are parts of the hardware that

are occasionally idle. One theoretical application is a smart cellular phone that supports

multiple communication and data protocols, though just one a time. When the phone

passes from a geographic region that is served by one protocol into a region that is served

by another, the hardware is automatically reconfigured. This is reconfigurable computing

at its best, and using this approach it is possible to design systems that do more, cost less,

and have shorter design and implementation cycles.

Reconfigurable computing has several advantages.

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First, it is possible to achieve greater functionality with a simpler hardware design.

Because not all of the logic must be present in the FPGA at all times, the cost of

supporting additional features is reduced to the cost of the memory required to store

the logic design. Consider again the multiprotocol cellular phone. It would be possibleto support as many protocols as could be fit into the available on-board ROM. It is

even conceivable that new protocols could be uploaded from a base station to the

handheld phone on an as-needed basis, thus requiring no additional memory.

The second advantage is lower system cost, which does not manifest itself exactly as

you might expect. On a low-volume product, there will be some production cost

savings, which result from the elimination of the expense of ASIC design and

fabrication. However, for higher-volume products, the production cost of fixed

hardware may actually be lower. We have to think in terms of lifetime system costs to

see the savings. Systems based on reconfigurable computing are upgradable in the

field. Such changes extend the useful life of the system, thus reducing lifetime costs.

The final advantage of reconfigurable computing is reduced time-to-market. The fact

that youre no longer using an ASIC is a big help in this respect. There are no chip

design and prototyping cycles, which eliminates a large amount of development effort.

In addition, the logic design remains flexible right up until (and even after) the product

ships. This allows an incremental design flow, a luxury not typically available to

hardware designers. You can even ship a product that meets the minimum

requirements and add features after deployment. In the case of a networked product

like a set-top box or cellular telephone, it may even be possible to make such

enhancements without customer involvement.

RECONFIGURABLE HARDWARE

Traditional FPGAs are configurable, but not run-time reconfigurable. Many of the older

FPGAs expect to read their configuration out of a serial EEPROM, one bit at a time. And

they can only be made to do so by asserting a chip reset signal. This means that the FPGAmust be reprogrammed in its entirety and that its previous internal state cannot be captured

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beforehand. Though these features are compatible with configurable computing

applications, they are not sufficient for reconfigurable computing.

In order to benefit from run-time reconfiguration, it is necessary that the FPGAs involved

have some or all of the following features. The more of these features they have, the more

flexible can be the system design. Deciding which hardware objects to execute and when

Swapping hardware objects into and out of the reconfigurable logic Performing routing

between hardware objects or between hardware objects and the hardware object

framework. Of course, having software manage the reconfigurable hardware usually means

having an embedded processor or microcontroller on-board. (We expect several vendors to

introduce single-chip solutions that combine a CPU core and a block of reconfigurable logic

by years end.) The embedded software that runs there is called the run-time environment

and is analogous to the operating system that manages the execution of multiple software

threads. Like threads, hardware objects may have priorities, deadlines, and contexts, etc. It

is the job of the run-time environment to organize this information and make decisions

based upon it.

The reason we need a run-time environment at all is that there are decisions to be made

while the system is running. And as human designers, we are not available to make these

decisions. So we impart these responsibilities to a piece of software. This allows us to

write our application software at a very high level of abstraction. To do this, the run-time

environment must first locate space within the RPU that is large enough to execute the

given hardware object. It must then perform the necessary routing between the hardware

objects inputs and outputs and the blocks of memory reserved for each data stream. Next,

it must stop the appropriate clock, reprogram the internal logic, and restart the RPU. Once

the object starts to execute, the run-time environment must continuously monitor the

hardware objects status flags to determine when it is done executing. Once it is done, the

caller can be notified and given the results. The run-time environment is then free to

reclaim the reconfigurable logic gates that were taken up by that hardware object and to

wait for additional requests to arrive from the application software.

The principal benefits of reconfigurable computing are the ability to execute larger

hardware designs with fewer gates and to realize the flexibility of a software-based

solution while retaining the execution speed of a more traditional, hardware-based

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approach. This makes doing more with less a reality. In our own business we have seen

tremendous cost savings, simply because our systems do not become obsolete as quickly

as our competitors because reconfigurable computing enables the addition of new features

in the field, allows rapid implementation of new standards and protocols on an as-needed

basis, and protects their investment in computing hardware.

Whether you do it for your customers or for yourselves, you should at least consider using

reconfigurable computing in your next design. You may find, as we have, that the benefits

far exceed the initial learning curve. And as reconfigurable computing becomes more

popular, these benefits will only increase.

ADVANTAGES

When a particular software is loaded the present hardware design is erased and a new

hardware design is generated by making a particular number of connections active while

making others idle.

It is possible to get ten times better performance, with ten times lower energy consumption

at the same time, according to heysters. He did his research at the centre for telematics and

information technology of the university of twente in the netherlands.

Can create customized communications signal processors

Increased performance and channel count

Can more quickly adapt to new requirements and standards

Lower development costs and reduce risk.

Reducing power

Reducing manufacturing cost.

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DISADVANTAGES

Inertia engineers slow to change

Inertia is the worst problem facing reconfigurable computing

RCP designs requires comprehensive set of tools

'Learning curve' for designers unfamiliar with reconfigurable logic

COMPARISON WITH DEDICATED HARDWARE

Asic provide ultimate Performance but fail in Time-to-market and Unable to satisfy the

Need of flexibility.

Reconfiguration versus Dedicated hardware -Higher performance, Lower cost and lower

Power consumption.

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WHAT IS THE ADVANTAGE OF ASIC?

Asic-like performance with programmable systems

Asics typically get 100x better performance per unit area than microprocessors

Application-specific memory systems in a programmable chip

Transform memory references into communication

Create natural division of programs into regular and irregular blocks

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DESIGN PROCESS OF CHIP

In designing process , an initial idea describes the charasteristics of a circuit:which

wire will bring what information and which wires will get results.this is then refined

into an architectural design that shows the major functional units of the circuit and how

they interact.each unit is then designed at a more detailed but still abstract level.the

final refinement converts this schematic specification into an integrated circuit layoutin whatever semiconductor technology will be used to build the chip.

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CONCLUSION

These new chips called chameleon chips are able to rewire themselves on the fly to create

the exact hardware needed to run a piece of software at the utmost speed.an example of

such kind of a chip is a chameleon chip.this can also be called a chip on demand

Reconfigurable computing goes a step beyond programmable chips in the matter of

flexibility. It is not only possible but relatively commonplace to "rewrite" the silicon so

that it can perform new functions in a split second. Reconfigurable chips are simply the

extreme end of programmability.

Highly flexible processors that can be reconfigured remotely in the field, Chameleon's

chips are designed to simplify communication system design while delivering increased

price/performance numbers.

The chameleon chip is a high bandwidth reconfigurable communications processor

(RCP).it aims at changing a system's design from a remote location.this will mean more

versatile handhelds.

Its applications are in, data-intensive Internet,DSP,wireless basestations, voice

compression, software-defined radio, high-performance embedded telecom and datacom

applications, xDSL concentrators,fixed wireless local loop, multichannel voice

compression, multiprotocol packet and cell processing protocols. Its advantages are that it

can create customized communications signal processors ,it has increased performance

and channel count, and it can more quickly adapt to new requirements and standards and

it has lower development costs and reduce risk.

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A FUTURISTIC DREAM

One day, someone will make a chip that does everything for the ultimate consumer device.

The chip will be smart enough to be the brains of a cell phone that can transmit or receive

calls anywhere in the world. If the reception is poor, the phone will automatically adjust so

that the quality improves. At the same time, the device will also serve as a handheld

organizer and a player for music, videos, or games.

Unfortunately, that chip doesn't exist today.

It would require

flexibility

high performance

low power

and low cost

But we might be getting closer. Now a new kind of chip may reshape the semiconductor

landscape. The chip adapts to any programming task by effectively erasing its hardware

design and regenerating new hardware that is perfectly suited to run the software at hand.

These chips, referred to as reconfigurable processors, could tilt the balance of power that

has preserved a decade-long standoff between programmable chips and hard-wired custom

chips.


needed to run a piece of software at the utmost speed.an example of such kind of a chip is a

chameleon chip.this can also be called a chip on demand

Reconfigurable computing goes a step beyond programmable chips in the matter of

flexibility. It is not only possible but relatively commonplace to "rewrite" the silicon so that

it can perform new functions in a split second. Reconfigurable chips are simply the extreme

end of programmability.

If these adaptable chips can reach a cost-performance parity with hard-wired chips,

customers will chuck the static hard-wired solutions. And if silicon can indeed become

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dynamic, then so will the gadgets of the information age. No longer will you have to buy a

camera and a tape recorder. You could just buy one gadget, and then download a new

function for it when you want to take some pictures or make a recording. Just think of the

possibilities for the fickle consumer.

Programmable logic chips, which are arrays of memory cells that can be programmed to

perform hardware functions using software tools, are more flexible than DSP chips but

slower and more expensive For consumers, this means that the day isn't far away when a

cell phone can be used to talk, transmit video images, connect to the Internet, maintain a

calendar, and serve as entertainment during travel delays -- without the need to plug in

adapter hardware

REFERENCES

BOOKS

Wei Qin Presentation , Oct 2000 (The part of the presentation

regarding CS2000 is covered in this page)

IEEE conference on Tele-communication, 2001.

WEBSITES

www.chameleonsystems.com

www.thinkdigit.com

www.ieee.org

www.entecollege.com

www.iec.org

www.quicksilvertechnologies.com

www.xilinx.com

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http://www.chameleon/http://www.chameleon/http://www.thinkdigit.com/http://www.ieee.org/http://www.iec.org/http://www.quicksilver/http://www.chameleon/http://www.thinkdigit.com/http://www.ieee.org/http://www.iec.org/http://www.quicksilver/


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FAQS

What is chameleon chip?

What is the need of chameleon chip?

What is Reconfigurable processor?

What are the application of chameleon chip?

What is FPGA?

How can it use for the work stations?

What is the need of reconfigurable processor?

GLOSSARY

FPGA : Field Programmable Logic Array

ASIC : Application Specific Integrated Circuit

GPP : General Purpose Processor

RCP : Reconfigurable Communication Processor

API : Application Programming Interface

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SEMINAR GUIDE INTERACTION REPORT

xliv

Phase Interaction Remarks

Topic Decision

Resource search

Compilation of resources

Abridged report

Rough draft

Intermediate draft


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chamelion chip

Documents