challenges for non volatile memory (nvm) for automotive ... › eu › sites › semi.org › files...

Alexander Muffler

Challenges for Non Volatile Memory (NVM) for Automotive High Temperature Operating Conditions

Product Marketing Manager Automotive, X-FAB

Outline

• Introduction

• NVM Technology & Design

• NVM Product Integration & Application

• NVM Test in Production

• Conclusions

The More than

Moore Foundry.

X-FAB - Who we are

• 25 years proven track record of

experience in pure-play foundry

services for analog/mixed-signal

semiconductor applications

• Specialty foundry with a

comprehensive set of robust

technologies serving automotive

needs such as high temperature, high

voltage and non volatile memories

Manufacturing

excellence

• 6 wafer fab facilities in Germany,

France, Malaysia and US

• Capacity: 94,000 wafer starts per

month (200mm equiv.)

• ISO 16949 certification for all sites

(in transition to IATF 16949)

• Audited and approved by major OEMs

• More than 3,800 employees worldwide

Technologies interfacing

the real world

• Expertise in analog/mixed-signal IC

production, MEMS and SiC with a focus

on high-growth automotive, medical and

industrial end markets with long

lifecycles

• Strong design support to drive customer

engagement over the long-term with

successful technology leaders

• Technologies qualified according to AEC-

Q100

Semicon Europa 2017 4

Introduction

Overview of typical NVM applications in modern cars, especially in high-temperature environments (close to engine, exhaust etc.)

High temperature spots in different zones of a car

(source: www.eetimes.com)

Hall sensorPressure sensorInertial/gyro sensorTemperature sensor Optical sensorTouch panel sensor

Battery Fuel GaugesBattery MonitorsBattery Protectors

LIN & CAN bus transceiver

Voltage regulator ICBLDC motor controller Full Bridge MOSFET Pre-DriverMid.-Power 3 Phase BLDC Pre-Driver


Introduction

Micro-electronic devices with embedded non volatile memory (NVM) for certain automotive applications are expected to be highly reliable within an extended operating temperature range (e.g. AEC-Q100 Grade 0: Tamb,max = 150°C).

The kind of NVM application (data storage, program storage etc.) and mission profile have a strong impact on the actual reliability requirements e.g. in terms of program endurance and data retention.

Different aspects related to the chosen NVM technology and design, its integration in a product and application as well as the quality control by dedicated tests in production need special attention in order to enable robust and high-temperature capable NVM solutions for sub-micron nodes.


NVM Technology & Design

Technology: memory principle, technology node, wafer process architecture, materials, primitive devices etc.

NVM technology determines possible performance and reliability (performance over use time) with their dependencies e.g. on operating conditions (T, V, …).

Design: memory cell architecture, memory size, bias conditions for memory operations (write, erase, read), address mapping, trimming, etc.

NVM design determines actual performance and reliability.

Both NVM technology and design refer to the pure NVM part and its periphery (e.g. charge pumps, read-out circuitry).



Challenge: How to realize high-temperature capable NVM technology & design?

Performance

• Temperature-dependent electrical parameters (compensation via design)

• Parasitic effects (e.g. increasing junction leakage at higher temperatures)

• Material properties (e.g. CTE mismatch, thermal limitations)

Reliability (-> next slides)



Typical NVM specific reliability failure mechanisms

NVM type Failure mechanism Corresp. failure modes Countermeasures

Floating gate OTP • Charge de-trapping and SILC, thermionic emission

• Electrical disturb effects

• Data loss over time

• Data corruption during operation

High gate oxide quality,adjusted programming conditions

Floating gate EEPROM • Charge de-trapping and SILC, thermionic emission

• Interface / oxide charge trapping



• Asymmetrical VT

window narrowing • Data corruption during

operation

High tunnel and gate oxide quality, adjusted programming conditions and number of cycles, reference trimming

Charge trapping EEPROM(e.g. SONOS)

• Charge de-trapping and vertical leakage



• Asymmetrical VT

window narrowing

High oxide quality, adjusted programming conditions, reference trimming














• Asymmetrical VT


operation






• Asymmetrical VT

window narrowing


strong temperature impact














• Asymmetrical VT


operation






• Asymmetrical VT

window narrowing




EEPROM endurance: VT window lowering during w/e cycling due to different mechanisms that all may occur in parallel; in addition: temperature dependence of VT levels and read threshold. Partial compensation by NVM design possible.

Source: A. Spinelli, Tutorial at ESREF 2010.














• Asymmetrical VT


operation






• Asymmetrical VT

window narrowing




EEPROM data retention: intrinsic retention limited by oxide tunneling and thermionic emission; retention after w/e cycling additionally affected by charge de-trapping (strong thermal acceleration) and SILC (strong field acceleration).

Source: A. Spinelli, Tutorial at ESREF 2010.



Other, CMOS related failure mechanism that can influence the reliability of NVM

Affected structure Failure mechanism

FEOL Process Gate oxide, MOS

NMOS, PMOS

HV MOS

Stress induced leakage current (SILC)Time dependent dielectric breakdown (TDDB)Plasma process induced damage (P2ID)Hot carrier injection (HCI)Bias temperature instability (BTI)Latch-up (LU)Thermal runaway

BEOL Process Metallization

Capacitor, ILD, IMD

Passivation

Electro / stress migration (EM / SM or SIV)CorrosionDelaminationTime dependent dielectric breakdown (TDDB)Plasma process induced damage (P2ID)Cracking



Other, CMOS related failure mechanism that can influence the reliability of NVM

Affected structure Failure mechanism

FEOL Process Gate oxide, MOS

NMOS, PMOS

HV MOS

Stress induced leakage current (SILC)Time dependent dielectric breakdown (TDDB)Plasma process induced damage (P2ID)Hot carrier injection (HCI)Bias temperature instability (BTI)Latch-up (LU)Thermal runaway

BEOL Process Metallization

Capacitor, ILD, IMD

Passivation

Electro / stress migration (EM / SM or SIV)CorrosionDelaminationTime dependent dielectric breakdown (TDDB)Plasma process induced damage (P2ID)Cracking

strong temperature impact


NVM Product Integration & Application

Good matching of embedded NVM and surrounding circuitry

• Suitable interface for access to NVM

• Good control and high stability of memory biasing conditions

Implementation of advanced safety measures

• E.g. data error detection, data error correction (ECC), redundancy of data or memory

Adjustment of NVM mission profile (“load management”) based on knowledge of reliability models and limitations

• E.g. de-rating of programming conditions, wear levelling, duty cycle adjustment

Product reliability risk assessment with respect to potential NVM failures

• E.g. functional safety (ISO26262): determination of ASIL, FMEDA, failure rate evaluation


NVM Product Integration & Application

Even for ready-to-use NVM IP it is essential to consider specific requirements and guidelines for the product integration and application, e.g.

• Defined operating conditions

• IP specification

• IP test specification

• Specific application notes

Common design integration reviews between NVM IP provider and user can help to identify issues at an early stage and to mitigate the risks.


NVM Test in Production

Design for testability (DfT)

• Measurement access to quality and reliability relevant parameters at test

• High test coverage with respect to critical circuitry elements and paths

• Implementation of on-chip test features (e.g. BIST)

• Enablement of electrical (over-) stressing for screening purpose

Advanced production test flow

• Test of all relevant NVM operating modes within full required operating temperature range

• Data retention test for complementary NVM data patterns

• Parallel testing for cost reasons required

• Statistical data analysis for outlier detection

Wafer probe 1 @ T1 (e.g 25°C)

Bake

Wafer probe 2 @ T2 e.g. 175°C

Bake

Final test @ T3 e.g. -40°C

Fig. 1: Example test flow


Conclusions

Realization of high-temperature capable NVM for automotive applications and their successful process and product integration are feasible.

• Example: NVM in 0.18 Micron Analog Mixed Signal HV CMOS Technology ( www.xfab.com)


Conclusions

In order to achieve this, a couple of challenges have to be mastered through appropriate measures:

1. Baseline technology setup

2. NVM module integration

3. NVM design

4. NVM integration in product

5. NVM test implementation

NVM development Product development

Thank You!

Alexander MufflerProduct Marketing Manager AutomotiveE-Mail: alexander.muffler[at]xfab.com

Abbreviations

ASIL … Automotive Safety Integrity Level

BIST … Built-In Self-Test

EEPROM … Electrically Erasable Programmable Read-Only Memory

FMEDA … Failure Modes, Effects and Diagnostics Analysis

HV … High Voltage

IP … Intellectual Property

MOS … Metal Oxide Semiconductor

NVM … Non Volatile Memory

OTP … One Time Programmable (Memory)

SILC … Stress Induced Leakage Current

SONOS … Silicon Oxide Nitride Oxide Silicon

challenges for non volatile memory (nvm) for automotive ... › eu › sites › semi.org › files...

Documents