Cell Design and Layout

Kenneth YunUC San Diego

Adapted from EE271 notes,Stanford University

Overviewn Wiresn FPGAn Gate Arrayn Standard Celln Datapath Cellsn Cell Layoutn Reading

n W&E 6.3-6.3.6, 5.3

Wiresn Part of capacitive load

n Need to know the length to size (driver) gates

n Need to plan for it

n Resistancen Long wires have RC time constants

n Special wiresn Power, ground, and clockn Need to have low resistance

Wire Properties

S/D,M1HighMediumpdiff

S/D,M1HighMediumndiff

gate,M1LowMediumpoly

diff,poly,M2LowLowM1

M1LowLowM2

Connects toCapacitanceResistanceLayer

Wire Characteristics

1/30005Ωpdiff115KΩnMOS230KΩpMOS

1/30005Ωndiff1/30005Ωpoly1/1.5x1050.1ΩmetalR•/RtransR•Layer

Wt

L

W

LR

W

L

tR sq==

ρ

Wire Usagen Diffusion

n Bad wire (high capacitance)n Only used to connect to transistors

n Polyn Resistance high: good for short, local

interconnectsn Do not use to route outside cells or as jumpers in

long wires

n Metaln M1: only conductor that can connect to poly and

diffn M1,…,Mn−1 for general wiringn Mn for Vdd, Ground, and clock routing

Cell Implementation Technologiesn Field programmable gate arrays (FPGA)

n Chips prefabricated; program fuses/anti-fuses

n Gate arrays (mask programmable)n Transistors prefabricated; customize metal to

generate cells

n Standard cellsn All cells have fixed heightn Wiring may be restricted to channels

n Macro cellsn Similar to standard cells butn Wiring done over cells

n Memory (2D array)

FPGAn Logic is programmed into chip after

fabricationn Programming done using

n Memory cells and CMOS switchesn Fuse/anti-fusen EPROM cells hold values for 10 years

n Customizing wiresn To program connections, need switchesn Switches have R and C; slows down signals on

wires

n Completely prefabricated in large volumen Cost effective for certain applications

FPGA Wiringn Standard cell like wiring (with channels)

n Each channel has wires of different lengthn How many of each length determined by design

statisticsn Use logic blocks as repeaters when necessaryn Problem: switches in wires (high resistance)

Gate Arrayn Transistors predefined

n W/L all the same (or choice limited)n Transistors prefabricatedn Chip covered with transistors (sea of gates)

n Designer provides metal patterns that form logic gates by connecting transistorsn Transistors under wiring channels not used. Why?

n Cheaper and faster to manufacture than standard cells. Why?

Gate Array Layout

2-input NAND

out

Vdd Vdd

Gnd

A B

Gnd

Standard Celln Appropriate for all or part of a custom chipn All cells have the same height (with abutting

power and ground)n Cells tiled into rowsn Rows separated by routing channels

n Channel height variable

CellHeight

(includesVdd, Gnd) Channel

height

Standard Cell Layout Example

Macro Celln Standard cell with wiring done

inside celln 1D – datapathn 2D – memory

n Wires kept short and regularn Less wiring arean Less wire load (drivers can be

smaller)n Order cells to minimize wire

lengths

bitslice

control (word line)

bit line

regmux adder

Datapathn Fixed height cells with bit pitch set to

n height of tallest celln accommodate the total number of over-the-cell

wires per bitn 128λ a good choicen Often, cells are mirrored (every other cell is

flipped vertically) to share Vdd and Gnd rails. Why?n Some cells take up multiple bit pitches

n E.g., 4-bit Manchester carry chain

n Variable widthn Depends on functionality of cells

Datapath (continued)n Wires over cells

n Bit lines for datan Word lines for control, clock

n Place cells to minimize number of horizontal tracks and wire lengths

Registers

ΦA ΦB

Adder

ΦAΦB

LAR R R R LB MX LB AddLA

Slice Plan

Requires3 Tracks

Basic Layout Guidelinesn Do wire planning before cell layout

n Assign preferred direction to each layern Group p’s and n’sn Determine input/output port locationsn Power, ground, and clock wires must be wide

n Determine cell pitchn Height of tallest celln Number of over-the-cell tracks and wire lengths

n Use metal for wiringn Use poly for intra-cell wiring onlyn Use diffusion for connection to transistors only

n Do stick diagram first!

Basic Cell Layout Guidelinesn P-N spacing is large, so keep pMOS

together and nMOS togethern Mirror cells, if necessary. How does it help?

n Vdd and ground distribution must be in wide metaln Vdd runs near pMOS groupsn Ground runs near nMOS groups

n Layers in alternate directionsn M1 and M2 should run in (predominantly)

orthogonal directions. Why?

Transistor Layout

n Transistors should be at least as wide as contacts (4λ)

n Use as many contacts as possible for wider transistors

n Don’t use 3λ device except for weak devices

Good bad bad bad

Transistor Foldingn Better aspect ratio for large transistorsn Reduces diffusion area

32/2

16/2 16/2

32/2 16/2 16/2 8/2 8/2 8/2 8/2

8/2 8/2 8/2 8/2

Folding Series Gatesn Fold the whole stack, not individual

transistors

Example: Standard Cell Latchn Static designn Φ’ generated internallyn Feedback isolated from output

Φ

outin

Standard Cell Stick Diagram

clk in out

Transistors share diffusionLocal poly routing

Vdd

Gnd

Room for M2 track over cell

Standard Cell Layout

Datapath Cell Layout Optionsn Data/control

n Data bus in M1 and control in M2n Data bus in M2 and control in M1

n Power/Groundn in control direction (vertical)n in data direction (horizontal)

Stick Diagram (1)n Start with just wires

Vdd

Gnd

DIN

DOUT

ST ST’ RD RD’

Stick Diagram (2)n Draw transistors connected to inputs

and outputs

Vdd

Gnd

DIN

DOUT

ST ST’ RD RD’

Stick Diagram (3)n Draw remaining transistors

Vdd

Gnd

DIN

DOUT

ST ST’ RD RD’

Power and Groundn Resistance of power supply line must be

very smalln If too large, then the voltage supplied to

gates will drop (why?), which may cause malfunction of gates

n So, power supply lines must be wide metaln Rtrans >> Rmetal

n Not so easy since wires are long and transistors are large

Power IR Dropn Example: for 100K gate chip

n Each gate drives 1mm wire (200fF) in 500psn I = C dV/dt = 200fF x 2.5V / 500ps = 1mAn If all switch at once, 100A!n Even if only 10% switch at once, still 10A peak

current!

n Considerable IR drop!n Need many supply pins, wide power supply

wiresn Grids are good for low R

Power Distributionn Distribute power on thickest metal

Gnd

Vdd

local buses