casper workshop tut4

8/9/2019 Casper Workshop Tut4

1/16

2010 CASPER WorkshopTutorial 4: Wideband Poco

Author: W. New

Expected completion time: 2hrs

Contents:

• Introduction

• Setup• Backround

• Creatin !our "esin

• So#t$are

Introduction

In this tutorial, you will create a simple Simulink desin which uses the i!"# board on $%!#& andthe #!SPE$ "SP blockset to process a wideband sinal, channeli'e it and output the () *isibilitiesthrouh $%!#&+s PP#.

y this stae, it is expected that you ha*e completed tutorials - and 2 and are reasonablycomortable with Simulink and basic Python. We will ocus here on hiher/le*el desin concepts,and will pro*ide you with low/le*el detail preimplemented.

2 Setup

0he lab at the workshop is preconiured with the #!SPE$ libraries, 1atlab and ilinx tools. Start1atlab.

3 Background

Some o this desin is similar to that o the pre*ious tutorial, 0he Wideband Spectrometer. Socompletion o 0utorial 3 is recommended.

3. The Correlator

0he correlator we will be desinin is a 4 input correlator. It uses 2 inputs rom each !"#, althouhyou do not need to populate $%!#& with the second !"#.

Page 1 of 16


2/16

3.2 Antennae and Baselines

When doin correlation on a set o antennae we introduce the term baseline. ! baseline is theproduct o the sinal rom two antennas. We calculate all baselines. 5or example, i we ha*e 3antennae, !, and #, we need to perorm correlation across each baseline, !, !# and #. Wealso need to do auto/correlations, which will i*e us the power in each sinal. ie !!, , ##. We will

see this implemented later.

3.3 Polarization

"ish type recei*ers are typically dual polari'ed 6hori'ontal and *ertical eeds7. Each polari'ation ised into separate !"# inputs. When correlatin these antennae, we dierentiate between ull Stokescorrelation or a hal Stokes method. ! ull Stokes correlator does cross correlation between thedierent polari'ations 6ie or a i*en two antennas, ! and , it multiplies the hori'ontal eed rom !with the *ertical eed rom and *ice/*ersa7. ! hal stokes correlator only correlates like polari'ationswith each other, thereby hal*in the compute re8uirements.

%ur correlator here perorms all cross correlations and so can be thouht o as a 2/input ull Stokescorrelator or as a our input sinle polari'ation correlator.

4 Creating Your esign

4. Create a ne! "odel#

Start 1atlab and open Simulink 6either by typin simulink on the 1atlab command line, or by clickinthe Simulink icon in the taskbar7. #reate a new model and add the Xilinx System Generator and

XSG core config blocks as beore in 0utorial -.

4. . S$ste" %enerator and &S% Blocks

y now you should ha*e used these blocks a number o times. Pull the S%ste&'enerator block into your desin rom the ilinx lockset menu under asicElements. 0he settins can be let on deault.

0he (S' block can be ound under the EE9PS System lockset. Set the&ardware platorm to $%!#&:sx;t, the #lock Source to adc< to supply the 5P?!+s clock@

Page 2 of 16


3/16

4. .2 S$nc %enerator

0he Sync ?enerator puts out a sync pulse which is used to synchroni'e the blocks in the desin.See the #!SPE$ memo on sync pulse eneration or a detailed explanation and the i% i!"#tutorial or an example on its basic use.

0his sync enerator is able to synchroni'e with an external trier input. 0ypically we connect this toa ?PS+s -pps output to allow the system to reset on a second boundary ater a sotware arm and

thus know precisely the time at which an accumulation was started. 0o do this you can input the-pps sinal into either !"#s+ sync input.

Page 3 of 16


4/16

4. .3 ACs

#onnection o the !"#s is as in tutorial 3 except or the sync outputs. &ere we %$ all our outputstoether to produce a sync pulse at one 8uarter the rate o the !"#+s sample clock. 0his means,howe*er, that our system can only be synchroni'ed to within 3 !"# sample clocks.

We will not use the -pps in this tutorial althouh the desin has the acility to do this hardwaresync+in.

Page 4 of 16


5/16

Set up the !"#s as ollows and chane the second !"# board+s mask parameter to adc1...

0o create the concat blocks, construct the subsystem shown below. 0he unnamed blocks areReinterpret and Concat blocks.

Page 5 of 16


6/16

5or the purposes o simulation 6and to satisy Simulink+s re8uirements that all inputs be connected7,we need to put input sinals into the !"#s. 0hese blocks are pulse enerators in the case o syncinputs and any analoue source or the $5 inputs 6noise, #W tones etc7.

Page 6 of 16


7/16

4. .4 Control 'egister

0his part o the Simulink desin sets up a sotware reister which can be coniured in sotware tocontrol the correlator. Set the yellow so#t$are reister)s I% direction as #ro& processor* Aou canind it in the EE9PS System blockset. 0he constant block input to this reister is used only orsimulation.

0he output o the sotware reister oes to three slice blocks, which will pull out the indi*idualparameters or use with coniuration. 0he irst slice block 6top7 is setup as ollows:

0he slice block can be ound under the ilinx lockset B #ontrol Coic. 0he only chane with thesubse8uent slice blocks is the %set o the bottom bit. 0hey are, rom top to bottom, respecti*ely,-D,- F -G.

!ter each slice block we put a posede +lock, this outputs true i a boolean input sinal is true this

clock and was alse last clock. 5ound under #!SPE$ "SP lockset B 1isc.

Next are the delay blocks. 0hey can be let with their deault settins and can be ound under ilinxlockset B #ommon.

0he 'oto and ,ro& bocks can be ound under Simulink/H Sinal $outin. Cabel them as in theblock diaram abo*e.

Page 7 of 16


8/16

4. .( Clip etect and status reporting

0o detect and report sinal saturation 6clippin7 to sotware, we will create a subsystem with latchininputs.

0he internals o this subsystem 6riht7 consist o delayblocks, reisters and cast blocks.

0he delays 6inputs 2 / 7 can be keep as deault. #astblocks are re8uired as only unsined inteers can beconcatenated. Set their parameters to (nsined, - bit, <binary points 0runcated uanti'ation, Wrapped %*erlowand < Catency.

0he $eisters 6inputs -< / 337 must be set up with an initial*alue o < and with enable and reset ports enabled.

0he status reister on the output o the clip detect is set to

processor in with unsined data type and < binary pointwith a sample period o -.

Page 8 of 16


9/16

4. .) P*Bs+ **Ts and ,uantisers

0he P5 5I$, 550 and the uanti'er are the heart o this desin, there is one set o each or the 4outputs o the !"#s. 0his system consists o our copies o tut3.

5or the adc


10/16

Setup the slice blocks to return the oriinal sinals that we ot rom the !"#s.

#oniure the P595I$9real blocks as shown below:

0here is potential to o*erlow the irst 550 stae i the input is periodic or sinal le*els are hih asshitin inside the 550 is only perormed ater each butterly stae calculation. 5or this reason, werecommend castin any inputs up to -G bits with the binary point at position - 6thus keepin therane o *alues /- to -7, and then downshitin by - bit to place the sinal in one less than the mostsiniicant bits.

0he t9wide9band9real block should be coniured as ollows:

Page 10 of 16


11/16

0he uanti'er Subsystem is desined as seen below. 0he 8uanti'er remo*es the bit rowth thatwas introduced in the P5 and 550. We can do this because we do not need the ull dynamic rane.

Page 11 of 16


12/16

4. .- /s

0he ollowin sections are more periphery to the desin and will only be touched on. y now youshould be comortable puttin the blocks toether and be able to iure out many o the *alues andparameters. !lso eel ree to consult the reerence desin which sits in the tutorial 4 proJect directory

or ask any 8uestions o the tutorial helpers.

!s a kind o debu output we can wire up the CE"s to certain sinals. We liht an CE" with e*erysync pulse. 0his is a sort o heartbeat showin that the desin is clockin and the 5P?! is runnin.

We liht an error CE" in case any !"# o*erlows and another i the system is reset. 0he ourth CE"i*es a *isual indication o when an accumulation is complete.

$%!#&+s CE"s are neati*e loic, so when the input to the yellow block is hih, the CE" is o.Since this is the opposite o what you+d normally expect, we in*ert the loic sinals with a -.T ate.

Since the sinals miht be too short to liht up an CE" and or us to actually see it 6consider thecase where a sinle !"# sample o*erlowsK -LG


13/16


14/16

#%N0$%C:

desin starts by itsel. %nly control reister is or resettin counters and optionally sync+in toexternal sinal.

Sync CE" pro*ides a Oheartbeat sinal to instantly see i your desin is clocked sensibly.

New accumulation CE" i*es a *isual indication o data rates and dump times.

!ccumulation counter pro*ides simple mechanism or checkin i a new spectrum output isa*ailable. 6poll and compare to last *alue7

( Sot!are

0he python scripts are located in the proJect directory. We irst need to run poco9init.py to proramthe 5P?! and coniure the desin. 0hen we can run either the auto or the cross correlations scripts6plot9poco9auto.py and plot9poco9cross.py7.

poco/init*p%

print('Connecting to server %s on port %i... '%(roach,katcp_port)),fpga = corr.katcp_wrapper.FpgaClient(roach, katcp_port,

timeout=1,logger=logger)time.sleep(1)

if fpga.is_connecte!()"print 'ok#n'

else"print '$& connecting to server %s on port %i.#n'%

(roach,katcp_port)eit_fail()

print ''print 'rogramming F*+...',

if not opts.skip"fpga.prog!ev(offile)print '!one'

else"print '-kippe!.'

print 'Configuring fft_shift...',fpga.write_int('fft_shift',(//0)1)print '!one'

print 'Configuring accumulation perio!...',fpga.write_int('acc_len',opts.acc_len)print '!one'

print 'esetting oar!, software triggering an! resetting error

counters...',fpga.write_int('ctrl',112) 3armfpga.write_int('ctrl',114) 3software triggerfpga.write_int('ctrl',)fpga.write_int('ctrl',114) 3issue a secon! triggerprint '!one'

In pre*ious tutorials you will probably ha*e seen *ery similar code to the code abo*e. 0his initiatesthe katcp wrapper named fpga which manaes the interace between the sotware and the

Page 14 of 16


15/16

hardware. fpga.prog!ev prorams the boile onto the 5P?! and fpga.write_int writes to areister.

poco/adc/a&plitudes*p%

0his script outputs in the amplitudes 6or power7 o each sinal as well as the bits used. It updates

itsel e*er second or so.

ADC amplitudes

---------------

ADC0 input I: 0.060 (3.93 bits used)

ADC0 input Q: 0.006 (0.70 bits used)

ADC1 input I: 0.622 (7.32 bits used)

ADC1 input Q: 0.709 (7.50 bits used)

-----------------------------------

poco/plot/auto*p%

0his script rabs auto/correlations rom the brams and plots them. Since there are 4 inputs, 2 oreach !"# there are 4 plots. Some plots will be random i there is no noise source or tone beininputted into !"#. Ie plots 3 and 4.

poco/plot/cross*p%

Page 15 of 16


16/16

0his script rabs cross/correlations rom the brams and plots them. 0his plotshows the cross/correlation o !.

Page 16 of 16

casper workshop tut4

Documents