CA‐basedRandomNumberGenerator

Bang‐NingHsuDarrellGasparYan‐YouLin

ECE261ProfessorMorizio1

XOR[A,OR[B,C]]

ANewKindofScienceS.Wolfram,2002

AC [B XOR D] AC [B XOR D]

FPGA implementation of neighborhood-of-four cellular automata random number generatorsShackleford et al., 2002 ACM Symposium on FPGA, 106-112

2

logic

MUX

flip‐flop

seed

1

10

5

62

s=0 s=1

101

562

0

‐3 4 9

3

2:1TGMUX

DSTCFF

logic

3

7

6

2 2

2 2

4 4

6 6

6

6

4

New TSPC Latches and Flipflops Minimizing Delay and PowerYuen and Svensson, 1996 Symposium on VLSl Circuits Digest of Technical Papers

4

logic

2:1TGMUX

DSTCFF

s

seed

Φ

49

0

‐3

op\mizedfortpdr=tpdf

5

VDDGND

outputsoftheupperhalfofcells

outputsofthelowerhalfofcells

768.56µm

707.2µm

sΦ

6

550

825

1,100

7:3 7:4 7:6 7:7 6:7

FF + 4 inv

950

1,225

1,500

7:3 6:7 6:5 6:4

RNG

pdrpdf

ps

wp:wn

FFoutputbufferop\miza\on

7

tpdr,tpdf=1.2ns

loadingseedintoFF(#64=1,else=0)

1stcycle

Φ 10 ns

8

first10cyclesELDO=VHDL→Javaparser→2.5millionnumbers→DIEHARD

Φ 22 ns

9

typeoftest

p

0.99730.0070

DIEHARD

pass:0.0000001~0.9999999

10

technologyclock(MHz)

transistorarea

(mm2)power

HP2002

0.22µ FPGA5-layer metal2.5 V

219

us0.5µ3-layer metal5 V

1003840

(logic40+MUX6+FF14)x64

0.54 86 nW

Hortensius1989

3µ1-layer metal

20 0.72

ImportanceSamplingforIsingComputersUsingOne‐DimensionalCellularAutomataHortensiusetal.(1989)IEEETransac\onsonComputers38769

input:VDDGNDΦSoutput:32‐bit/10nscycle

11

12

13

loadingseedintoFF(#64=1,else=0)

1stcycle

Φ 22 ns

14